JP4712686B2 - 半導体デバイス製造方法 - Google Patents
半導体デバイス製造方法 Download PDFInfo
- Publication number
- JP4712686B2 JP4712686B2 JP2006502973A JP2006502973A JP4712686B2 JP 4712686 B2 JP4712686 B2 JP 4712686B2 JP 2006502973 A JP2006502973 A JP 2006502973A JP 2006502973 A JP2006502973 A JP 2006502973A JP 4712686 B2 JP4712686 B2 JP 4712686B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- silicon
- nitrogen
- semiconductor device
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
- H01L21/0276—Photolithographic processes using an anti-reflective coating
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/004—Photosensitive materials
- G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
- G03F7/091—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers characterised by antireflection means or light filtering or absorbing means, e.g. anti-halation, contrast enhancement
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Structural Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Architecture (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Formation Of Insulating Films (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
従って、半導体デバイス製造のための改良されたARC層が必要とされている。
異なる図面中の同一の参照番号は、特に記述しない限り同一の部材を示す。
図1〜図5は、その厚さ方向において様々なケイ素含有率を有する、本発明によるARC層を用いた半導体デバイスを製造する方法の一実施形態を示す部分断面図である。
点で蒸着される層201の部分は、T1〜T2の間で蒸着された層201部分と比較すると高いケイ素含有率を有する。T3において、窒素/ケイ素比はDに減少している。この時点で蒸着される層201の部分は、T2〜T3間で蒸着された層201部分と比較すると高いケイ素含有率を有する。T4において、窒素/ケイ素比はEに減少している。この時点で蒸着される層201部分は、T3〜T4間で蒸着された層201の部分と比較すると高いケイ素含有率を有する。
T1=2秒、T2=2秒、T3=3秒、T4=3秒、T5=3秒、T6=3秒、T7=2秒、T8=2秒、及びT9=2秒。
図7は、図6に示したプロセスの詳細に従って形成されたARC層のケイ素含有率を示すグラフである。図7に示すように、ケイ素含有率はARC層201の底部と頂部とにおいて最も低く、期間T4〜T5(図6参照)にて蒸着される中間部705において最も高い。異なるプロセスにより形成されるARC層は、異なるケイ素含有率のプロファイルを有し得る。
工程を含む方法によって、金属層上にARC層を蒸着させる工程とを含む。ケイ素反応物は、酸素及び窒素の少なくとも一方からなる。ARC層を蒸着させる方法は、第一の部分を形成した後、ケイ素/ケイ素反応物が第二の比を有するARC層の第二の部分を形成する工程も含む。第二の比は、第一の比と比較して大きい。
Claims (4)
- 半導体デバイス製造方法であって:
半導体基板(103)上にゲート誘電体層(105)を形成するステップと;
前記ゲート誘電体層(105)上にゲート形成用の金属ゲート形成層(107)を形成するステップであって、前記金属ゲート形成層(107)は、窒化チタン、窒化ケイ素タンタル、イリジウム、酸化イリジウム、ルテニウム、酸化ルテニウム、タングステン、窒化タングステン、および窒化ケイ素チタンのうち少なくとも1つを有することと;
前記金属ゲート形成層(107)上に窒化ケイ素からなる反射防止膜(201)を、窒素含有ガスとケイ素含有ガスから形成するステップであって、前記反射防止膜(201)は前記金属ゲート形成層(107)に隣接する底部と、その上の中間部と、その上の頂部とを有し、前記底部および前記頂部は、前記中間部と比較して高い窒素含有率を有することと;
前記反射防止膜(201)上にフォトレジスト層(301)を形成するステップと;
前記フォトレジスト層(301)をパターン化するステップと;
パターン化された前記フォトレジスト層(301)にしたがって、前記反射防止膜(201)と前記金属ゲート形成層(107)をエッチングすることによって、トランジスタの金属ゲート(403)を形成するステップと
を備えることを特徴とする、半導体デバイス製造方法。 - 前記底部の窒素濃度は、化学量論的な窒化ケイ素の窒素濃度以上である、請求項1記載の半導体デバイス製造方法。
- 前記反射防止膜(201)の屈折率は、前記フォトレジスト層(301)をパターン化するステップに使用される紫外光の波長248nmにおいて、全体として2.44である、請求項1記載の半導体デバイス製造方法。
- 前記半導体デバイス製造方法は更に:
前記トランジスタのソース(503)とドレイン(507)を形成するステップ
を備える、請求項1記載の半導体デバイス製造方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/353,886 US6908852B2 (en) | 2003-01-29 | 2003-01-29 | Method of forming an arc layer for a semiconductor device |
US10/353,886 | 2003-01-29 | ||
PCT/US2004/001924 WO2004070471A2 (en) | 2003-01-29 | 2004-01-23 | Arc layer for semiconductor device |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2006516823A JP2006516823A (ja) | 2006-07-06 |
JP2006516823A5 JP2006516823A5 (ja) | 2007-03-08 |
JP4712686B2 true JP4712686B2 (ja) | 2011-06-29 |
Family
ID=32736279
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006502973A Expired - Fee Related JP4712686B2 (ja) | 2003-01-29 | 2004-01-23 | 半導体デバイス製造方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US6908852B2 (ja) |
JP (1) | JP4712686B2 (ja) |
KR (1) | KR101085279B1 (ja) |
CN (1) | CN100481418C (ja) |
TW (1) | TW200508805A (ja) |
WO (1) | WO2004070471A2 (ja) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4186725B2 (ja) * | 2003-06-24 | 2008-11-26 | トヨタ自動車株式会社 | 光電変換素子 |
US7271464B2 (en) * | 2004-08-24 | 2007-09-18 | Micron Technology, Inc. | Liner for shallow trench isolation |
US7202164B2 (en) | 2004-11-19 | 2007-04-10 | Chartered Semiconductor Manufacturing Ltd. | Method of forming ultra thin silicon oxynitride for gate dielectric applications |
US7629256B2 (en) * | 2007-05-14 | 2009-12-08 | Asm International N.V. | In situ silicon and titanium nitride deposition |
US20080299775A1 (en) * | 2007-06-04 | 2008-12-04 | Applied Materials, Inc. | Gapfill extension of hdp-cvd integrated process modulation sio2 process |
US7867921B2 (en) * | 2007-09-07 | 2011-01-11 | Applied Materials, Inc. | Reduction of etch-rate drift in HDP processes |
US7745350B2 (en) * | 2007-09-07 | 2010-06-29 | Applied Materials, Inc. | Impurity control in HDP-CVD DEP/ETCH/DEP processes |
US7972968B2 (en) * | 2008-08-18 | 2011-07-05 | Applied Materials, Inc. | High density plasma gapfill deposition-etch-deposition process etchant |
JP5155070B2 (ja) * | 2008-09-02 | 2013-02-27 | 株式会社日立国際電気 | 半導体装置の製造方法、基板処理方法及び基板処理装置 |
US20110151222A1 (en) * | 2009-12-22 | 2011-06-23 | Agc Flat Glass North America, Inc. | Anti-reflective coatings and methods of making the same |
CN102810504A (zh) * | 2011-05-31 | 2012-12-05 | 无锡华润上华半导体有限公司 | 厚铝生长工艺方法 |
US8497211B2 (en) | 2011-06-24 | 2013-07-30 | Applied Materials, Inc. | Integrated process modulation for PSG gapfill |
US9018108B2 (en) | 2013-01-25 | 2015-04-28 | Applied Materials, Inc. | Low shrinkage dielectric films |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07130650A (ja) * | 1993-07-06 | 1995-05-19 | Motorola Inc | 半導体基板上に集積回路パターンを形成する方法および構造 |
JPH07326608A (ja) * | 1994-04-05 | 1995-12-12 | Sony Corp | 半導体装置の製造方法 |
JPH08274023A (ja) * | 1995-03-29 | 1996-10-18 | Motorola Inc | 反射防止層を備えた半導体装置を製作する方法 |
US6100559A (en) * | 1998-08-14 | 2000-08-08 | Advanced Micro Devices, Inc. | Multipurpose graded silicon oxynitride cap layer |
JP2000299380A (ja) * | 1998-11-12 | 2000-10-24 | Hyundai Electronics Ind Co Ltd | 半導体素子のコンタクト形成方法 |
US6294820B1 (en) * | 1998-02-23 | 2001-09-25 | Motorola, Inc. | Metallic oxide gate electrode stack having a metallic gate dielectric metallic gate electrode and a metallic arc layer |
-
2003
- 2003-01-29 US US10/353,886 patent/US6908852B2/en not_active Expired - Lifetime
- 2003-12-15 TW TW092135422A patent/TW200508805A/zh unknown
-
2004
- 2004-01-23 WO PCT/US2004/001924 patent/WO2004070471A2/en active Application Filing
- 2004-01-23 JP JP2006502973A patent/JP4712686B2/ja not_active Expired - Fee Related
- 2004-01-23 KR KR1020057013929A patent/KR101085279B1/ko not_active IP Right Cessation
- 2004-01-23 CN CNB2004800031339A patent/CN100481418C/zh not_active Expired - Fee Related
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07130650A (ja) * | 1993-07-06 | 1995-05-19 | Motorola Inc | 半導体基板上に集積回路パターンを形成する方法および構造 |
JPH07326608A (ja) * | 1994-04-05 | 1995-12-12 | Sony Corp | 半導体装置の製造方法 |
JPH08274023A (ja) * | 1995-03-29 | 1996-10-18 | Motorola Inc | 反射防止層を備えた半導体装置を製作する方法 |
US6294820B1 (en) * | 1998-02-23 | 2001-09-25 | Motorola, Inc. | Metallic oxide gate electrode stack having a metallic gate dielectric metallic gate electrode and a metallic arc layer |
US6100559A (en) * | 1998-08-14 | 2000-08-08 | Advanced Micro Devices, Inc. | Multipurpose graded silicon oxynitride cap layer |
JP2000299380A (ja) * | 1998-11-12 | 2000-10-24 | Hyundai Electronics Ind Co Ltd | 半導体素子のコンタクト形成方法 |
Also Published As
Publication number | Publication date |
---|---|
JP2006516823A (ja) | 2006-07-06 |
CN1765019A (zh) | 2006-04-26 |
WO2004070471A2 (en) | 2004-08-19 |
KR20050096957A (ko) | 2005-10-06 |
TW200508805A (en) | 2005-03-01 |
KR101085279B1 (ko) | 2011-11-22 |
US20040145029A1 (en) | 2004-07-29 |
US6908852B2 (en) | 2005-06-21 |
CN100481418C (zh) | 2009-04-22 |
WO2004070471A3 (en) | 2005-11-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6596636B2 (en) | ALD method to improve surface coverage | |
US7884022B2 (en) | Multiple deposition for integration of spacers in pitch multiplication process | |
US8123968B2 (en) | Multiple deposition for integration of spacers in pitch multiplication process | |
JP4712686B2 (ja) | 半導体デバイス製造方法 | |
JP2012142574A (ja) | 金属酸化物のハードマスクの形成方法 | |
US20080057733A1 (en) | Method of fabricating a semiconductor integrated circuit device | |
CN110875176A (zh) | 半导体装置的形成方法 | |
US10867794B2 (en) | Patterning method for semiconductor devices and structures resulting therefrom | |
US6323139B1 (en) | Semiconductor processing methods of forming photoresist over silicon nitride materials | |
US6620745B2 (en) | Method for forming a blocking layer | |
US6670695B1 (en) | Method of manufacturing anti-reflection layer | |
JP2000058830A (ja) | 反射防止構造体とその製造法 | |
US6130146A (en) | In-situ nitride and oxynitride deposition process in the same chamber | |
KR100995829B1 (ko) | 반도체 소자 및 그의 제조방법 | |
TW200928589A (en) | Method for manufacturing a semiconductor device | |
US5946599A (en) | Method of manufacturing a semiconductor IC device | |
TW202312270A (zh) | 含碳材料的循環電漿蝕刻 | |
CN117438408A (zh) | 半导体装置及其制备方法 | |
US20030219961A1 (en) | Method to reduce reflectivity of polysilicon layer |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20070119 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20070119 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20091016 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20091027 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20100127 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20100203 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20100226 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20100305 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100312 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20110301 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20110323 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 4712686 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |