JP4700967B2 - チップ・パッケージの内の複数の基板の階層システム - Google Patents
チップ・パッケージの内の複数の基板の階層システム Download PDFInfo
- Publication number
- JP4700967B2 JP4700967B2 JP2004564625A JP2004564625A JP4700967B2 JP 4700967 B2 JP4700967 B2 JP 4700967B2 JP 2004564625 A JP2004564625 A JP 2004564625A JP 2004564625 A JP2004564625 A JP 2004564625A JP 4700967 B2 JP4700967 B2 JP 4700967B2
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- Japan
- Prior art keywords
- master
- substrate
- subset
- net list
- chip package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2113/00—Details relating to the application field
- G06F2113/18—Chip packaging
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5382—Adaptable interconnections, e.g. for engineering changes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12044—OLED
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Geometry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- General Engineering & Computer Science (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Description
上記したように、本発明は、必要とされる設計時間と労力の量を減らし、これによって、新製品がより速やかに市場に提供されるようにし、これら製品の製造にかかる経費を削減するものである。一般的に言えば、本発明は、パッケージが汎用的に多種多様な半導体チップに用いられるようにするパッケージの配線接続を設計するものである。本発明は、基板のメニュー内に含まれることになる最大基板(チップ・パッケージ)のマスタ(又はスーパー基板)設計を作成する。マスタ基板より小さい基板が、マスタ設計のサブセットである。すなわち、本発明は、スーパー基板設計の再利用がそのための設計サブセットの全てにおいて役立つようにする改良された設計手法と、共通の(I/O及び機能的)ネット・リスト階層の考慮に基づく異なる大きさの多数のダイ(チップ)のための多数の新しいパッケージを、ネットの簡単なプログラム的削除によってスーパー基板から得ることができる改良されたパッケージの両方を表現するものである。
Claims (1)
- 配線ネットリストを有するマスタ基板と、前記マスタ基板から不要な前記配線ネットリストを削除することによって、前記マスタ基板から派生した、前記マスタ基板より小さいチップパッケージであって、前記マスタ基板より小さいチップパッケージの配線ネットの全てが、前記マスタ基板の前記配線ネットリストのサブセットに共通であり、かつ合同であるサブセット基板とを含む、チップパッケージの階層システムにおいて、前記マスタ基板は、当該階層システムにおける最大の論理的及び物理的配線を有する最大基板である、チップ・パッケージ内の複数の基板の階層システム。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/US2002/040671 WO2004061726A1 (en) | 2002-12-18 | 2002-12-18 | Nested design approach |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006511954A JP2006511954A (ja) | 2006-04-06 |
JP4700967B2 true JP4700967B2 (ja) | 2011-06-15 |
Family
ID=32710256
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004564625A Expired - Fee Related JP4700967B2 (ja) | 2002-12-18 | 2002-12-18 | チップ・パッケージの内の複数の基板の階層システム |
Country Status (5)
Country | Link |
---|---|
EP (1) | EP1573602A4 (ja) |
JP (1) | JP4700967B2 (ja) |
CN (1) | CN1695149A (ja) |
AU (1) | AU2002360668A1 (ja) |
WO (1) | WO2004061726A1 (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006202977A (ja) * | 2005-01-20 | 2006-08-03 | Sony Corp | 基板及び基板の製造方法、並びに半導体パッケージ及び半導体パッケージの製造方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10150120A (ja) * | 1996-11-19 | 1998-06-02 | Denso Corp | プリント配線基板,bga型lsiパッケージ及び電子装置 |
JPH11345908A (ja) * | 1998-03-31 | 1999-12-14 | Altera Corp | 互換性を有するicパッケ―ジおよびマイグレ―ション経路を確保する方法 |
JP2000171965A (ja) * | 1998-12-08 | 2000-06-23 | Toshiba Corp | 半導体装置の製造方法、フォトマスクの製造方法および原板 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5608638A (en) * | 1995-02-06 | 1997-03-04 | Advanced Micro Devices | Device and method for automation of a build sheet to manufacture a packaged integrated circuit |
US5953236A (en) * | 1995-10-31 | 1999-09-14 | Vlsi Technology, Inc. | Method and apparatus for implementing engineering change orders in integrated circuit designs |
US5777383A (en) * | 1996-05-09 | 1998-07-07 | Lsi Logic Corporation | Semiconductor chip package with interconnect layers and routing and testing methods |
-
2002
- 2002-12-18 CN CNA02829968XA patent/CN1695149A/zh active Pending
- 2002-12-18 JP JP2004564625A patent/JP4700967B2/ja not_active Expired - Fee Related
- 2002-12-18 WO PCT/US2002/040671 patent/WO2004061726A1/en active Application Filing
- 2002-12-18 AU AU2002360668A patent/AU2002360668A1/en not_active Abandoned
- 2002-12-18 EP EP02795945A patent/EP1573602A4/en not_active Withdrawn
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10150120A (ja) * | 1996-11-19 | 1998-06-02 | Denso Corp | プリント配線基板,bga型lsiパッケージ及び電子装置 |
JPH11345908A (ja) * | 1998-03-31 | 1999-12-14 | Altera Corp | 互換性を有するicパッケ―ジおよびマイグレ―ション経路を確保する方法 |
JP2000171965A (ja) * | 1998-12-08 | 2000-06-23 | Toshiba Corp | 半導体装置の製造方法、フォトマスクの製造方法および原板 |
Also Published As
Publication number | Publication date |
---|---|
JP2006511954A (ja) | 2006-04-06 |
CN1695149A (zh) | 2005-11-09 |
EP1573602A1 (en) | 2005-09-14 |
WO2004061726A1 (en) | 2004-07-22 |
EP1573602A4 (en) | 2009-08-26 |
AU2002360668A1 (en) | 2004-07-29 |
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