JP4699704B2 - 配線基板 - Google Patents
配線基板 Download PDFInfo
- Publication number
- JP4699704B2 JP4699704B2 JP2004063023A JP2004063023A JP4699704B2 JP 4699704 B2 JP4699704 B2 JP 4699704B2 JP 2004063023 A JP2004063023 A JP 2004063023A JP 2004063023 A JP2004063023 A JP 2004063023A JP 4699704 B2 JP4699704 B2 JP 4699704B2
- Authority
- JP
- Japan
- Prior art keywords
- plating layer
- electroless
- layer
- solder
- plating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Chemically Coating (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
図3は本発明の一実施形態に係る配線基板1の断面構造を模式的に示すものである。該配線基板は、耐熱性樹脂板(例えばビスマレイミド−トリアジン樹脂板)や、繊維強化樹脂板(例えばガラス繊維強化エポキシ樹脂)等で構成された板状コア2の両表面に、所定のパターンに配線金属層をなすコア導体層M1,M11がそれぞれ形成される。これらコア導体層M1,M11は板状コア2の表面の大部分を被覆する面導体パターンとして形成され、電源層又は接地層として用いられるものである。他方、板状コア2には、ドリル等により穿設されたスルーホール12が形成され、その内壁面にはコア導体層M1,M11を互いに導通させるスルーホール導体30が形成されている。また、スルーホール12は、エポキシ樹脂等の樹脂製穴埋め材31により充填されている。
シアン化第1金カリウム:2g/L(金イオンとして)
エチレンジアミンテトラメチレンホスホン酸:0.15モル/L
ポリエチレンイミン(分子量2000):5g/L
pH:7.0
6 誘電体層
7 内層導体層
8,18 ソルダーレジスト層
8a,18a 開口
L1,L2 配線積層部
CP 第一主表面
10,17 金属端子パッド
34 ビア
51 メッキ用下地導電層
52 Cuメッキ層
53 Niメッキ層
20,21,22,121 バリア金属層
54 Auメッキ層
Claims (2)
- 第一主表面が誘電体層にて形成されるように、高分子材料からなる誘電体層と導体層とが交互に積層された配線積層部と、該配線積層部の前記誘電体層にて形成された前記第一主表面上に配置され、液相線温度が200℃以上のPbを含有しないSn合金からなる高温半田ボールを介してチップやマザーボードに接続される複数の金属端子パッドとを有し、
前記金属端子パッドは、前記第一主表面側にCuメッキ層が配置され、他方最表層部に無電解還元Auメッキ層が配置された構造を有し、それらCuメッキ層と無電解還元Auメッキ層との間にバリア金属層として、前記Cuメッキ層と接するNi−P無電解Niメッキ層と、該Ni−P無電解Niメッキ層と前記無電解還元Auメッキ層との間に配置され、前記Ni−P無電解Niメッキ層から前記無電解還元Auメッキ層へのP拡散を阻止又は抑制するPバリア用無電解金属メッキ層とが配置されてなり、
前記配線積層部の第一主表面は、ソルダーレジスト層にて覆われてなり、該ソルダーレジスト層の開口の内周縁が、前記金属端子パッドの主表面外周縁よりも内側に張り出すように配置され、
前記Cuメッキ層は、面粗し処理が施された外周縁部にて前記ソルダーレジスト層の内周縁部と直接接触し、前記Pバリア用無電解金属メッキ層は、前記ソルダーレジスト層の開口の内側に位置する領域のみ前記無電解還元Auメッキ層にて覆われ、
前記Pバリア用無電解金属メッキ層が白金族金属無電解メッキ層であることを特徴とする配線基板。 - 前記高温半田ボールはSnAg合金又はSnCu合金からなる請求項1に記載の配線基板。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004063023A JP4699704B2 (ja) | 2003-03-18 | 2004-03-05 | 配線基板 |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003073767 | 2003-03-18 | ||
JP2003073767 | 2003-03-18 | ||
JP2004063023A JP4699704B2 (ja) | 2003-03-18 | 2004-03-05 | 配線基板 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2004300570A JP2004300570A (ja) | 2004-10-28 |
JP4699704B2 true JP4699704B2 (ja) | 2011-06-15 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2004063023A Expired - Fee Related JP4699704B2 (ja) | 2003-03-18 | 2004-03-05 | 配線基板 |
Country Status (1)
Country | Link |
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JP (1) | JP4699704B2 (ja) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5145626B2 (ja) * | 2005-02-03 | 2013-02-20 | 凸版印刷株式会社 | 配線基板 |
JP2007067147A (ja) * | 2005-08-31 | 2007-03-15 | Shinko Electric Ind Co Ltd | プリント配線基板およびその製造方法 |
KR100744930B1 (ko) * | 2006-02-01 | 2007-08-01 | 삼성전기주식회사 | Ltcc 모듈의 제조 방법 |
JP5214139B2 (ja) * | 2006-12-04 | 2013-06-19 | 新光電気工業株式会社 | 配線基板及びその製造方法 |
JP4798451B2 (ja) * | 2006-12-12 | 2011-10-19 | 日立化成工業株式会社 | 配線板とその製造方法 |
JP5305787B2 (ja) * | 2008-08-27 | 2013-10-02 | セイコーインスツル株式会社 | 電子部品パッケージの製造方法 |
JP5714361B2 (ja) * | 2011-03-01 | 2015-05-07 | 日本碍子株式会社 | 端子電極形成方法及びそれを用いた圧電/電歪素子の製造方法 |
KR20150040577A (ko) * | 2013-10-07 | 2015-04-15 | 삼성전기주식회사 | 패키지 기판 |
JP6485777B2 (ja) * | 2016-05-31 | 2019-03-20 | 大口マテリアル株式会社 | 多列型半導体装置用配線部材及びその製造方法 |
JP6485776B2 (ja) * | 2016-05-31 | 2019-03-20 | 大口マテリアル株式会社 | 多列型半導体装置用配線部材及びその製造方法 |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61104085A (ja) * | 1984-10-26 | 1986-05-22 | Kyocera Corp | 電子部品のメタライズ金属層の被覆構造 |
JPH09270342A (ja) * | 1996-03-29 | 1997-10-14 | Tokin Corp | 電子部品及びその製造方法 |
JPH10242640A (ja) * | 1996-12-27 | 1998-09-11 | Ibiden Co Ltd | プリント配線板 |
JPH11140659A (ja) * | 1997-11-05 | 1999-05-25 | Hitachi Chem Co Ltd | 半導体搭載用基板とその製造方法 |
JP2000340951A (ja) * | 1999-05-31 | 2000-12-08 | Ngk Spark Plug Co Ltd | プリント配線基板 |
JP2001177254A (ja) * | 1999-12-21 | 2001-06-29 | Ibiden Co Ltd | スルーホールの充填方法および多層プリント配線板の製造方法 |
JP2002203925A (ja) * | 2000-12-28 | 2002-07-19 | Fujitsu Ltd | 外部接続端子及び半導体装置 |
JP2002327279A (ja) * | 2001-05-02 | 2002-11-15 | Furukawa Electric Co Ltd:The | 電子部品の接合方法 |
JP2002374058A (ja) * | 2001-06-13 | 2002-12-26 | Yazaki Corp | 電子部品の実装構造 |
-
2004
- 2004-03-05 JP JP2004063023A patent/JP4699704B2/ja not_active Expired - Fee Related
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61104085A (ja) * | 1984-10-26 | 1986-05-22 | Kyocera Corp | 電子部品のメタライズ金属層の被覆構造 |
JPH09270342A (ja) * | 1996-03-29 | 1997-10-14 | Tokin Corp | 電子部品及びその製造方法 |
JPH10242640A (ja) * | 1996-12-27 | 1998-09-11 | Ibiden Co Ltd | プリント配線板 |
JPH11140659A (ja) * | 1997-11-05 | 1999-05-25 | Hitachi Chem Co Ltd | 半導体搭載用基板とその製造方法 |
JP2000340951A (ja) * | 1999-05-31 | 2000-12-08 | Ngk Spark Plug Co Ltd | プリント配線基板 |
JP2001177254A (ja) * | 1999-12-21 | 2001-06-29 | Ibiden Co Ltd | スルーホールの充填方法および多層プリント配線板の製造方法 |
JP2002203925A (ja) * | 2000-12-28 | 2002-07-19 | Fujitsu Ltd | 外部接続端子及び半導体装置 |
JP2002327279A (ja) * | 2001-05-02 | 2002-11-15 | Furukawa Electric Co Ltd:The | 電子部品の接合方法 |
JP2002374058A (ja) * | 2001-06-13 | 2002-12-26 | Yazaki Corp | 電子部品の実装構造 |
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