JP4686580B2 - 電力用半導体装置 - Google Patents
電力用半導体装置 Download PDFInfo
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- JP4686580B2 JP4686580B2 JP2008208910A JP2008208910A JP4686580B2 JP 4686580 B2 JP4686580 B2 JP 4686580B2 JP 2008208910 A JP2008208910 A JP 2008208910A JP 2008208910 A JP2008208910 A JP 2008208910A JP 4686580 B2 JP4686580 B2 JP 4686580B2
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- 239000004065 semiconductor Substances 0.000 title claims description 99
- 239000012535 impurity Substances 0.000 claims description 54
- 230000015556 catabolic process Effects 0.000 description 28
- 230000000694 effects Effects 0.000 description 8
- 239000000758 substrate Substances 0.000 description 8
- 230000005684 electric field Effects 0.000 description 6
- 239000000463 material Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000000370 acceptor Substances 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
図1は、第1実施例の電力用半導体装置101の側方断面図である。図1A及び図1Bには、オン時に電流が流れる素子部111が示されており、図1Cには、素子部111の周辺に位置する終端部112が示されている。図1の電力用半導体装置101は、素子部111と、終端部112とを有している。図1Aの領域と図1Bの領域との関係については、後述する。
図3は、第2実施例の電力用半導体装置101の上面図である。図3において、素子部111は、n+ドレイン層121の表面に垂直な境界面Yにより、nリッチ領域111Aとpリッチ領域111Bとに分割されている。図3の矢印Xは、図1の矢印Xと同様、nピラー層122とpピラー層123とが交互に配置されている方向を表す。
図4は、第3実施例の電力用半導体装置101の上面図である。図4において、素子部111は、n+ドレイン層121の表面に垂直な境界面Yにより、nリッチ領域111Aとpリッチ領域111Bとに分割されている。図4の矢印Xは、図1の矢印Xと同様、nピラー層122とpピラー層123とが交互に配置されている方向を表す。
図5は、第4実施例の電力用半導体装置101の上面図である。図5において、素子部111は、n+ドレイン層121の表面に垂直な境界面Yにより、nリッチ領域111Aとpリッチ領域111Bとに分割されている。図5の矢印Xは、図1の矢印Xと同様、nピラー層122とpピラー層123とが交互に配置されている方向を表す。
111 素子部
112 終端部
121 n+ドレイン層
122 nピラー層
123 pピラー層
124 pベース層
125 nソース層
131 ゲート絶縁膜
132 ゲート電極
133 ソース電極
134 ドレイン電極
201 リサーフ層
211 フィールド絶縁膜
212 フィールドプレート電極
213 フィールドストップ電極
Claims (5)
- 素子部と終端部とを有する電力用半導体装置であって、
第1導電型の第1半導体層と;
前記第1半導体層上に形成され、前記第1半導体層の表面に平行な方向に沿って交互に配置された、第1導電型の第2半導体層及び第2導電型の第3半導体層であって、
前記素子部には、前記第2及び第3半導体層を有する第1領域と、前記第2及び第3半導体層を有する第2領域とが設けられており、前記第1領域と前記第2領域は、前記第1半導体層の表面に平行な方向に隣接しており、
前記第2半導体層の単位長さあたりの不純物量NAから前記第3半導体層の単位長さあたりの不純物量NBを引いた差分値ΔN(=NA−NB)については、前記素子部の前記第1領域の差分値ΔNC1と、前記素子部の前記第2領域の差分値ΔNC2と、前記終端部の差分値ΔNTとの間に、ΔNC1>ΔNT>ΔNC2の関係が成り立つ、
第2及び第3半導体層と;
前記第2及び第3半導体層の表面に選択的に形成された第2導電型の第4半導体層と;
前記第4半導体層の表面に選択的に形成された第1導電型の第5半導体層と;
前記第2、第4、及び第5半導体層上に絶縁膜を介して形成された制御電極と;
前記第4及び第5半導体層に電気的に接続された第1の主電極と;
前記第1半導体層に電気的に接続された第2の主電極とを備えることを特徴とする電力用半導体装置。 - 前記素子部の前記第1領域の差分値ΔNC1は、0よりも大きく、
前記素子部の前記第2領域の差分値ΔNC2は、0よりも小さいことを特徴とする請求項1に記載の電力用半導体装置。 - 前記終端部では、前記第2半導体層の単位長さあたりの不純物量と、前記第3半導体層の単位長さあたりの不純物量とが等しいことを特徴とする請求項1又は2に記載の電力用半導体装置。
- 前記第1領域と前記第2領域は、前記第2半導体層と前記第3半導体層とが交互に配置された方向の平行方向又は垂直方向に隣接していることを特徴とする請求項1から3のいずれか1項に記載の電力用半導体装置。
- 前記素子部には、前記第2及び第3半導体層を有する1つ以上の前記第1領域と、前記第2及び第3半導体層を有する1つ以上の前記第2領域とが設けられていることを特徴とする請求項1から4のいずれか1項に記載の電力用半導体装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008208910A JP4686580B2 (ja) | 2008-08-14 | 2008-08-14 | 電力用半導体装置 |
US12/540,192 US8030706B2 (en) | 2008-08-14 | 2009-08-12 | Power semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008208910A JP4686580B2 (ja) | 2008-08-14 | 2008-08-14 | 電力用半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2010045238A JP2010045238A (ja) | 2010-02-25 |
JP4686580B2 true JP4686580B2 (ja) | 2011-05-25 |
Family
ID=41680705
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008208910A Expired - Fee Related JP4686580B2 (ja) | 2008-08-14 | 2008-08-14 | 電力用半導体装置 |
Country Status (2)
Country | Link |
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US (1) | US8030706B2 (ja) |
JP (1) | JP4686580B2 (ja) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5629994B2 (ja) * | 2009-09-04 | 2014-11-26 | ソニー株式会社 | 半導体装置及び半導体装置の製造方法 |
US8829640B2 (en) * | 2011-03-29 | 2014-09-09 | Alpha And Omega Semiconductor Incorporated | Configuration and method to generate saddle junction electric field in edge termination |
CN104638004B (zh) * | 2013-11-15 | 2018-04-17 | 上海华虹宏力半导体制造有限公司 | 超级结mosfet器件的结构 |
JP6583700B2 (ja) * | 2015-12-02 | 2019-10-02 | サンケン電気株式会社 | 半導体装置 |
CN108181564A (zh) * | 2016-12-07 | 2018-06-19 | 无锡同方微电子有限公司 | 一种uis测试电路及其测试方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001298191A (ja) * | 2000-02-09 | 2001-10-26 | Fuji Electric Co Ltd | 半導体装置 |
JP2007235095A (ja) * | 2006-01-31 | 2007-09-13 | Denso Corp | 半導体装置および半導体基板の製造方法 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4524539B2 (ja) | 2002-08-13 | 2010-08-18 | 富士電機システムズ株式会社 | 半導体素子 |
JP4997715B2 (ja) | 2005-05-18 | 2012-08-08 | 富士電機株式会社 | 半導体装置およびその製造方法 |
JP2008182054A (ja) * | 2007-01-25 | 2008-08-07 | Toshiba Corp | 半導体装置 |
JP4564509B2 (ja) * | 2007-04-05 | 2010-10-20 | 株式会社東芝 | 電力用半導体素子 |
-
2008
- 2008-08-14 JP JP2008208910A patent/JP4686580B2/ja not_active Expired - Fee Related
-
2009
- 2009-08-12 US US12/540,192 patent/US8030706B2/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001298191A (ja) * | 2000-02-09 | 2001-10-26 | Fuji Electric Co Ltd | 半導体装置 |
JP2007235095A (ja) * | 2006-01-31 | 2007-09-13 | Denso Corp | 半導体装置および半導体基板の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
US8030706B2 (en) | 2011-10-04 |
US20100038712A1 (en) | 2010-02-18 |
JP2010045238A (ja) | 2010-02-25 |
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