JP4674477B2 - 半導体モジュール - Google Patents
半導体モジュール Download PDFInfo
- Publication number
- JP4674477B2 JP4674477B2 JP2005058776A JP2005058776A JP4674477B2 JP 4674477 B2 JP4674477 B2 JP 4674477B2 JP 2005058776 A JP2005058776 A JP 2005058776A JP 2005058776 A JP2005058776 A JP 2005058776A JP 4674477 B2 JP4674477 B2 JP 4674477B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- mounting substrate
- mounting
- semiconductor device
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Description
図1(a)、(b)は、本発明の実施の形態1における複数の半導体装置209が実装基板210に実装された半導体モジュールを示す断面図及び斜視図であり、図2(a)、(b)は、半導体装置209の断面図及び斜視図であり、図3(a)、(b)及び図4(a)、(b)は、図1における複数実装された半導体装置209のうち、一個の半導体装置209を実装基板210に実装した状態を示す断面図及び斜視図であり、図6は、本実施の形態1の他の実施例を示す斜視図である。
図7は、本発明の実施の形態2における複数の半導体装置209が実装基板210に実装された半導体モジュールを示す断面図である。図7において、図1〜図4と同じ構成要素については同じ符号を使い、説明を省略する。
図9は、本発明の実施の形態3における複数の半導体装置209が実装基盤210に実装された半導体モジュールを示す斜視図である。図9において、図1〜図4と同じ構成要素については同じ符号を用い、説明を省略する。
210 実装基板
211 半導体チップ
212 突起電極
213 保護部材
214 電極部
215 半導体チップ211の接続部
216 実装基板210の露出部
217 封止樹脂
321 半導体支持部材
410 外部端子
411 外部パッケージ
510 インタポーザ基板
512 スペーサ基板
513 ベース基板
Claims (1)
- 回路形成面を有する半導体チップと前記半導体チップ上に設けられた複数の突起電極とからなる半導体装置を、複数の電極部を備えた基板上に前記回路形成面が対向するように傾けて、前記複数の突起電極と前記複数の電極部を電気的に接続した半導体モジュールであって、
前記半導体装置を複数個並設し、隣り合う前記半導体装置を、前記複数の突起電極の配設方向に前記複数の突起電極の間隔の4分の1から4分の3までの間でずらして配設したことを特徴とする半導体モジュール。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005058776A JP4674477B2 (ja) | 2005-03-03 | 2005-03-03 | 半導体モジュール |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005058776A JP4674477B2 (ja) | 2005-03-03 | 2005-03-03 | 半導体モジュール |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006245278A JP2006245278A (ja) | 2006-09-14 |
JP4674477B2 true JP4674477B2 (ja) | 2011-04-20 |
Family
ID=37051376
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005058776A Expired - Fee Related JP4674477B2 (ja) | 2005-03-03 | 2005-03-03 | 半導体モジュール |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4674477B2 (ja) |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01217996A (ja) * | 1988-02-26 | 1989-08-31 | Hitachi Ltd | 電子装置 |
JPH06291248A (ja) * | 1993-04-05 | 1994-10-18 | Toshiba Corp | 半導体装置 |
JPH09326543A (ja) * | 1996-06-04 | 1997-12-16 | Hitachi Ltd | 電子部品 |
JPH11186489A (ja) * | 1997-12-17 | 1999-07-09 | Hitachi Ltd | 半導体装置およびそれを用いた電子装置 |
JP2001035992A (ja) * | 1999-07-22 | 2001-02-09 | Seiko Epson Corp | 半導体装置の製造方法および半導体装置、ならびに半導体基板、電子機器 |
-
2005
- 2005-03-03 JP JP2005058776A patent/JP4674477B2/ja not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01217996A (ja) * | 1988-02-26 | 1989-08-31 | Hitachi Ltd | 電子装置 |
JPH06291248A (ja) * | 1993-04-05 | 1994-10-18 | Toshiba Corp | 半導体装置 |
JPH09326543A (ja) * | 1996-06-04 | 1997-12-16 | Hitachi Ltd | 電子部品 |
JPH11186489A (ja) * | 1997-12-17 | 1999-07-09 | Hitachi Ltd | 半導体装置およびそれを用いた電子装置 |
JP2001035992A (ja) * | 1999-07-22 | 2001-02-09 | Seiko Epson Corp | 半導体装置の製造方法および半導体装置、ならびに半導体基板、電子機器 |
Also Published As
Publication number | Publication date |
---|---|
JP2006245278A (ja) | 2006-09-14 |
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