JP4621645B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP4621645B2 JP4621645B2 JP2006229627A JP2006229627A JP4621645B2 JP 4621645 B2 JP4621645 B2 JP 4621645B2 JP 2006229627 A JP2006229627 A JP 2006229627A JP 2006229627 A JP2006229627 A JP 2006229627A JP 4621645 B2 JP4621645 B2 JP 4621645B2
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- wiring layer
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- 239000004065 semiconductor Substances 0.000 title claims description 23
- 238000004519 manufacturing process Methods 0.000 title claims description 20
- 229910052782 aluminium Inorganic materials 0.000 claims description 25
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 25
- 230000001681 protective effect Effects 0.000 claims description 25
- 229910000838 Al alloy Inorganic materials 0.000 claims description 22
- 238000000034 method Methods 0.000 claims description 20
- 238000010438 heat treatment Methods 0.000 claims description 10
- 238000000059 patterning Methods 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 59
- 230000035882 stress Effects 0.000 description 27
- 239000003870 refractory metal Substances 0.000 description 11
- 230000015572 biosynthetic process Effects 0.000 description 8
- 238000001816 cooling Methods 0.000 description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 4
- 238000004380 ashing Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- 230000008646 thermal stress Effects 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000008034 disappearance Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000001552 radio frequency sputter deposition Methods 0.000 description 1
- 238000005546 reactive sputtering Methods 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
102 高融点金属層
104 アルミ合金層(配線層)
106 高融点金属層106
107 レジスト
108 保護絶縁膜層(パッシベーション膜)
110 SiN膜
200 層間絶縁膜
202 高融点金属層
204 アルミ合金層(配線層)
206 高融点金属層106
207 レジスト
208 SiO2層
210 SiN膜
Claims (8)
- 半導体基板上に配線層を形成する工程と;
前記配線層をパターニングする工程と;
前記配線層を保護絶縁膜で覆う工程と;
前記配線層のパターニング後、前記保護絶縁膜で覆う前に、当該配線層を加熱して塑性変形を起こさせる工程とを含み、
前記配線層を塑性変形させた後、当該配線層の温度を塑性変形温度以上に保持したまま、前記保護絶縁層で覆うことを特徴とする半導体装置の製造方法。 - 前記配線層のパターニング後、前記保護絶縁膜で覆う前に、当該配線層を350℃〜400℃程度加熱して塑性変形を起こさせる工程を更に含むことを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記保護絶縁層は、10000Å以上の膜厚を有することを特徴とする請求項1又は2に記載の半導体装置の製造方法。
- 前記配線層の厚さは、2μm以上であることを特徴とする請求項1乃至3の何れか1項に記載の半導体装置の製造方法。
- 前記熱処理工程は、前記配線層をパターニングする際のエッチング工程と、前記配線層をパターニングする際に使用したレジストの除去工程とを含むことを特徴とする請求項1乃至4の何れか1項に記載の半導体装置の製造方法。
- 前記配線層は、多層配線構造の最上配線層であることを特徴とする請求項1乃至5の何れか1項に記載の半導体装置の製造方法。
- 半導体基板上にアルミニウム又はアルミニウム合金層を含む配線層を、膜厚2μm以上で形成する工程と;
前記配線層をパターニングする工程と;
前記配線層を保護絶縁膜で覆う工程と;
前記配線層のパターニング後、前記保護絶縁膜で覆う前に、当該配線層を350℃〜400℃程度加熱して塑性変形を起こさせる工程とを含み、
前記配線層を塑性変形させた後、当該配線層の温度を塑性変形温度以上に保持したまま、前記保護絶縁層で覆うことを特徴とする半導体装置の製造方法。 - 前記保護絶縁層は、10000Å以上の膜厚を有することを特徴とする請求項7に記載の半導体装置の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006229627A JP4621645B2 (ja) | 2006-08-25 | 2006-08-25 | 半導体装置の製造方法 |
US11/822,213 US7816260B2 (en) | 2006-08-25 | 2007-07-03 | Method for fabricating semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006229627A JP4621645B2 (ja) | 2006-08-25 | 2006-08-25 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008053551A JP2008053551A (ja) | 2008-03-06 |
JP4621645B2 true JP4621645B2 (ja) | 2011-01-26 |
Family
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JP2006229627A Expired - Fee Related JP4621645B2 (ja) | 2006-08-25 | 2006-08-25 | 半導体装置の製造方法 |
Country Status (2)
Country | Link |
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US (1) | US7816260B2 (ja) |
JP (1) | JP4621645B2 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
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GB0819942D0 (en) | 2008-10-30 | 2008-12-10 | Indian Ocean Medical Inc | Guiding device for use with laryngoscope |
GB0906688D0 (en) | 2009-04-17 | 2009-06-03 | Indian Ocean Medical Inc | Laryngoscope |
GB0915107D0 (en) | 2009-08-28 | 2009-10-07 | Indian Ocean Medical Inc | Laryngoscope |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5934646A (ja) * | 1982-08-23 | 1984-02-25 | Oki Electric Ind Co Ltd | 半導体集積回路装置の製造方法 |
JPS62165328A (ja) * | 1985-10-29 | 1987-07-21 | トムソン コンポーネンツーモステック コーポレーション | 酸化後の金属合金化方法 |
JPH0653216A (ja) * | 1991-02-26 | 1994-02-25 | Nec Corp | 半導体装置およびその製造方法 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR960011865B1 (ko) * | 1993-06-10 | 1996-09-03 | 삼성전자 주식회사 | 반도체 장치의 금속층 형성방법 |
TW347570B (en) * | 1996-12-24 | 1998-12-11 | Toshiba Co Ltd | Semiconductor device and method for manufacturing the same |
US6531388B2 (en) * | 2001-07-26 | 2003-03-11 | Samsung Electronics Co., Ltd. | Method of forming an aluminum film for use in manufacturing a semiconductor device |
JP3792635B2 (ja) | 2001-12-14 | 2006-07-05 | 富士通株式会社 | 電子装置 |
JP3973467B2 (ja) * | 2002-03-20 | 2007-09-12 | Necエレクトロニクス株式会社 | 半導体装置の製造方法 |
US7211502B2 (en) * | 2003-03-26 | 2007-05-01 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
DE102004003538B3 (de) * | 2004-01-23 | 2005-09-08 | Infineon Technologies Ag | Integrierte Halbleiterschaltung mit einer Logik- und Leistungs-Metallisierung ohne Intermetall-Dielektrikum und Verfahren zu ihrer Herstellung |
WO2006117954A1 (ja) * | 2005-04-26 | 2006-11-09 | Mitsui Mining & Smelting Co., Ltd. | Al-Ni-B合金配線材料及びそれを用いた素子構造 |
-
2006
- 2006-08-25 JP JP2006229627A patent/JP4621645B2/ja not_active Expired - Fee Related
-
2007
- 2007-07-03 US US11/822,213 patent/US7816260B2/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5934646A (ja) * | 1982-08-23 | 1984-02-25 | Oki Electric Ind Co Ltd | 半導体集積回路装置の製造方法 |
JPS62165328A (ja) * | 1985-10-29 | 1987-07-21 | トムソン コンポーネンツーモステック コーポレーション | 酸化後の金属合金化方法 |
JPH0653216A (ja) * | 1991-02-26 | 1994-02-25 | Nec Corp | 半導体装置およびその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
US7816260B2 (en) | 2010-10-19 |
US20080050914A1 (en) | 2008-02-28 |
JP2008053551A (ja) | 2008-03-06 |
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