JP4605613B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP4605613B2
JP4605613B2 JP2009247256A JP2009247256A JP4605613B2 JP 4605613 B2 JP4605613 B2 JP 4605613B2 JP 2009247256 A JP2009247256 A JP 2009247256A JP 2009247256 A JP2009247256 A JP 2009247256A JP 4605613 B2 JP4605613 B2 JP 4605613B2
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terminal pad
semiconductor chip
power mosfet
mosfet
gate
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JP2010022069A (en
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光造 坂本
功 吉田
正敏 森川
成雄 大高
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Renesas Electronics Corp
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Renesas Electronics Corp
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Priority to JP5031579A priority Critical patent/JP3018816B2/en
Priority to JP17505599A priority patent/JP3446665B2/en
Priority to JP2003093135A priority patent/JP4007450B2/en
Priority to JP2007025328A priority patent/JP4437823B2/en
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
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    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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    • H01L2924/3011—Impedance
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

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  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Electronic Switches (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Protection Of Static Devices (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

本発明は大電力を扱う半導体素子に係り、特に、大電力用半導体素子の過熱並びに過電流保護回路並びにこれを有する半導体装置に関する。   The present invention relates to a semiconductor element that handles high power, and more particularly, to an overheat and overcurrent protection circuit for a semiconductor element for high power and a semiconductor device having the same.

過熱遮断回路を内蔵するパワーＭＯＳＦＥＴの例としては、特開昭６３−２２９７５８号公報がある。この従来例では本体のパワーＭＯＳＦＥＴのゲート端子と外部ゲート端子の間にゲート抵抗を、ゲート端子に保護回路用ＭＯＳＦＥＴを設け、本体パワーＭＯＳＦＥＴが過熱状態になったとき保護回路用ＭＯＳＦＥＴをオンし、ゲート抵抗に電流を流すことにより、本体パワーＭＯＳＦＥＴのゲート端子電圧を下げて本体パワーＭＯＳＦＥＴを遮断し、過熱による素子破壊を防止していた。   An example of a power MOSFET having a built-in overheat cutoff circuit is disclosed in Japanese Patent Laid-Open No. 63-229758. In this conventional example, a gate resistance is provided between the gate terminal of the power MOSFET of the main body and the external gate terminal, a protection circuit MOSFET is provided at the gate terminal, and when the main power MOSFET is overheated, the protection circuit MOSFET is turned on. By flowing a current through the gate resistor, the gate terminal voltage of the main body power MOSFET is lowered to shut off the main body power MOSFET, thereby preventing element destruction due to overheating.

特開昭６３−２２９７５８号公報JP-A 63-229758

この従来の過熱遮断回路内蔵パワーＭＯＳＦＥＴの回路例では、外部ゲート端子の電圧を５〜１０Ｖ程度降圧して、本体のパワーＭＯＳＦＥＴを遮断する必要からゲート抵抗が大きく、遮断用電流も大きくなるという問題があった。例えばこの場合、ゲート抵抗を５ｋΩ程度にする必要があり、保護回路用ＭＯＳＦＥＴには過熱遮断動作時に１〜２ｍＡ程度の大電流を流す必要があった。このため、従来の過熱遮断回路用パワーＭＯＳＦＥＴは高周波パルス駆動ではゲート遅延時間が大きくなりスイッチング損失が大きくなるという問題があった。また、過熱遮断動作時には保護回路用ＭＯＳＦＥＴがオンとなるので、外部ゲート端子のゲート電流が大きくなり、駆動回路の消費電力が大きくなるという問題があった。   In this conventional circuit example of a power MOSFET with a built-in overheat cutoff circuit, the voltage of the external gate terminal is lowered by about 5 to 10 V to cut off the power MOSFET of the main body, so that the gate resistance is large and the cutoff current is also large. was there. For example, in this case, the gate resistance needs to be about 5 kΩ, and a large current of about 1 to 2 mA needs to flow through the protection circuit MOSFET during the overheat cutoff operation. For this reason, the conventional power MOSFET for the overheat cutoff circuit has a problem in that the gate delay time is increased and the switching loss is increased in the high-frequency pulse drive. Further, since the protection circuit MOSFET is turned on during the overheat shut-off operation, there is a problem that the gate current of the external gate terminal increases and the power consumption of the drive circuit increases.

従って本発明の目的とするところは、高周波パルス駆動が可能でスイッチング損失が小さく、過熱遮断動作後のゲート電流も小さい、パワーＭＯＳＦＥＴの保護回路ならびに保護回路を有する保護回路内蔵パワーＭＯＳＦＥＴを提供することにある。   Accordingly, an object of the present invention is to provide a power MOSFET protection circuit and a power MOSFET with a built-in protection circuit, which can be driven by high frequency pulses, have low switching loss, and have a small gate current after an overheat cutoff operation. It is in.

上記目的を達成するために、本発明の一実施形態によれば、
第１のスイッチング素子（Ｍ０）の入力端子（４）とこの駆動回路（１０）の間に第２のスイッチング素子（Ｍ７）または可変抵抗素子を設け、
前記第１のスイッチング素子（Ｍ０）の入力端子（４）に第３のスイッチング素子（Ｍ５）を設け、
さらに、前記第１のスイッチング素子（Ｍ０）の温度検出回路または電流検出回路（１２）を設け、
この温度検出回路または電流検出回路（１２）により、前記第３のスイッチング素子（Ｍ５）をオン、前記第２のスイッチング素子（Ｍ７）をオフまたは高インピーダンスとせしめることを特徴とするものである（図１参照）。 In order to achieve the above object, according to one embodiment of the present invention,
A second switching element (M7) or a variable resistance element is provided between the input terminal (4) of the first switching element (M0) and the drive circuit (10),
A third switching element (M5) is provided at the input terminal (4) of the first switching element (M0);
Furthermore, a temperature detection circuit or a current detection circuit (12) of the first switching element (M0) is provided,
By this temperature detection circuit or current detection circuit (12), the third switching element (M5) is turned on and the second switching element (M7) is turned off or has a high impedance. (See FIG. 1).

さらに、本発明の他の一実施形態によれば、前記第１のスイッチング素子（Ｍ０）と、前記第３のスイッチング素子（Ｍ５）と前記温度検出回路または電流検出回路（１２）を第１の半導体チップ（１０４）に内蔵し、前記第２のスイッチング素子（Ｍ７）または前記可変抵抗素子を有する第２の半導体チップ（１０６）と同一パッケージに内蔵したことを特徴とするものである（図５参照）。   Furthermore, according to another embodiment of the present invention, the first switching element (M0), the third switching element (M5), and the temperature detection circuit or current detection circuit (12) are connected to the first switching element (M0). Built in a semiconductor chip (104) and built in the same package as the second semiconductor chip (106) having the second switching element (M7) or the variable resistance element (FIG. 5). reference).

さらに、本発明の好適な他の実施形態によれば、前記第２のスイッチング素子（Ｍ７）または前記可変抵抗素子が前記第１のスイッチング素子（Ｍ０）と絶縁層（１００６または１００２）を介して、同一チップ上に設けたことを特徴とするものである（図３と図４を参照）。   Furthermore, according to another preferred embodiment of the present invention, the second switching element (M7) or the variable resistance element is interposed between the first switching element (M0) and the insulating layer (1006 or 1002). Are provided on the same chip (see FIGS. 3 and 4).

本発明の代表的な実施形態では、負荷短絡事故または放熱条件の悪化によりパワーＭＯＳＦＥＴが過熱状態または過電流状態になった場合でもドレイン電流を制限するか遮断することにより素子破壊を防止するパワーＭＯＳＦＥＴの保護回路として、従来のゲート抵抗の代わりにＰチャネルＭＯＳＦＥＴ（Ｍ７）を用いていることが特徴である（図１参照）。
本実施形態では、第１のスイッチング素子であるパワーＭＯＳＦＥＴ（Ｍ０）が正常動作している場合には第２のスイッチング素子であるＰチャネルＭＯＳＦＥＴ（Ｍ７）がオン状態、第３のスイッチング素子であるＮチャネルＭＯＳＦＥＴ（Ｍ５）がオフ状態である。このため、駆動回路１０の出力電圧はそのまま等価的に低いゲート抵抗を介して、第１のスイッチング素子であるパワーＭＯＳＦＥＴ（Ｍ０）のゲート端子（４）に印加される。
ところが、パワーＭＯＳＦＥＴが過熱状態または過電流状態になった場合には制御回路（１１）により、第２のスイッチング素子であるＰチャネルＭＯＳＦＥＴ（Ｍ７）がオフ状態、第３のスイッチング素子であるＮチャネルＭＯＳＦＥＴ（Ｍ５）がオン状態になる。この時、駆動回路１０の出力端子は、第１のスイッチング素子であるパワーＭＯＳＦＥＴ（Ｍ０）のゲート端子と遮断される。このため、保護動作時の低いドレイン電流がＮチャネルＭＯＳＦＥＴ（Ｍ５）によりバイパスされパワーＭＯＳＦＥＴ（Ｍ０）を高速に遮断できる。
本発明の他の実施形態では、パワーＭＯＳＦＥＴの温度をできるだけ正確に測定するため、またはパワーＭＯＳＦＥＴの電流をカレントミラー構成で検出するために、温度検出回路または電流検出回路は本体のパワーＭＯＳＦＥＴ（Ｍ０）と同一の第１の半導体チップ（１０４）に形成し、第２のスイッチング素子であるＰチャネルＭＯＳＦＥＴ（Ｍ７）はパワーＭＯＳＦＥＴ（Ｍ０）のドレイン領域（図３の１０００）に形成することが不可能なため、第２の半導体チップ（１０６）に形成し、両チップの分離のため絶縁板（１０５）を前記第２の半導体チップ（１０６）の下に設けて同一パッケージに実装した。このため、前述の高性能な過熱保護回路または過電流保護回路を内蔵したパワーＭＯＳＦＥＴを従来と同じ小型のパッケージに実装できるという利点がある（図５参照）。
また、他の実施形態として、ＰチャネルＭＯＳＦＥＴを絶縁層（１００６または１００２）を介してパワーＭＯＳＦＥＴのドレイン領域（１０００）と分離することも可能である（図３または図４参照）。
本発明のその他の目的と特徴は、以下の実施例から明らかとなろう。 In a typical embodiment of the present invention, a power MOSFET that prevents element breakdown by limiting or blocking drain current even when the power MOSFET is overheated or overcurrent due to a load short circuit accident or deterioration of heat dissipation conditions. As a protection circuit, a P-channel MOSFET (M7) is used instead of the conventional gate resistance (see FIG. 1).
In this embodiment, when the power MOSFET (M0) that is the first switching element is operating normally, the P-channel MOSFET (M7) that is the second switching element is in the on state and is the third switching element. The N-channel MOSFET (M5) is in the off state. For this reason, the output voltage of the drive circuit 10 is directly applied to the gate terminal (4) of the power MOSFET (M0), which is the first switching element, via an equivalently low gate resistance.
However, when the power MOSFET is overheated or overcurrent, the control circuit (11) causes the P-channel MOSFET (M7), which is the second switching element, to be off, and the N-channel, which is the third switching element. The MOSFET (M5) is turned on. At this time, the output terminal of the drive circuit 10 is cut off from the gate terminal of the power MOSFET (M0) that is the first switching element. For this reason, the low drain current during the protection operation is bypassed by the N-channel MOSFET (M5), and the power MOSFET (M0) can be shut off at high speed.
In another embodiment of the present invention, in order to measure the temperature of the power MOSFET as accurately as possible, or to detect the current of the power MOSFET in a current mirror configuration, the temperature detection circuit or current detection circuit is a power MOSFET (M0) of the main body. ) On the same first semiconductor chip (104), and the P-channel MOSFET (M7) as the second switching element cannot be formed in the drain region (1000 in FIG. 3) of the power MOSFET (M0). Since it was possible, it formed in the 2nd semiconductor chip (106), the insulating board (105) was provided under the said 2nd semiconductor chip (106), and was mounted in the same package for isolation | separation of both chips | tips. Therefore, there is an advantage that the power MOSFET incorporating the above-described high-performance overheat protection circuit or overcurrent protection circuit can be mounted in the same small package as the conventional one (see FIG. 5).
In another embodiment, the P-channel MOSFET can be separated from the drain region (1000) of the power MOSFET through the insulating layer (1006 or 1002) (see FIG. 3 or FIG. 4).
Other objects and features of the present invention will become apparent from the following examples.

本発明によれば、高周波パルス駆動時にもスイッチング損失が小さく、また、本体素子の遮断動作後のゲート電流が小さく、遮断動作が高速な過熱保護または過電流保護回路内蔵パワーＭＯＳＦＥＴが得られるという効果がある。   According to the present invention, the switching loss is small even during high-frequency pulse driving, the gate current after the shut-off operation of the main body element is small, and the overheat protection or power MOSFET with a built-in overcurrent protection circuit that has a fast shut-off operation can be obtained. There is.

本発明の第１の実施例の回路図である。1 is a circuit diagram of a first embodiment of the present invention. 本発明の第２の実施例の回路図である。It is a circuit diagram of the 2nd example of the present invention. 本発明の第３の実施例の半導体装置の断面図である。It is sectional drawing of the semiconductor device of the 3rd Example of this invention. 本発明の第４の実施例の半導体装置の断面図である。It is sectional drawing of the semiconductor device of the 4th Example of this invention. 本発明の第５の実施例の半導体装置の平面図である。It is a top view of the semiconductor device of the 5th example of the present invention. 本発明の第６の実施例の回路図である。It is a circuit diagram of the 6th example of the present invention. 本発明の第７の実施例の回路図である。It is a circuit diagram of the 7th example of the present invention. 本発明の第８の実施例の回路図である。It is a circuit diagram of the 8th example of the present invention. 本発明の第９の実施例の回路図である。It is a circuit diagram of the 9th example of the present invention.

添付の図面に沿って、この発明の好ましい実施の形態について詳細に説明する。   A preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

図１は本発明の第１の実施例の回路図である。本実施例は負荷短絡事故または放熱条件の悪化によりパワーＭＯＳＦＥＴが過熱状態または過電流状態になった場合でもドレイン電流を制限するか遮断することによりパワーＭＯＳＦＥＴの破壊を防止する保護回路である。本図で、Ｍ０はパワーＭＯＳＦＥＴ、１２はＭ０の温度検出回路または電流検出回路、１１はＭ５とＭ７の制御回路である。従来の過電流または過熱保護回路ではパワーＭＯＳＦＥＴ（Ｍ０）のゲート端子４と駆動回路１０との間にはゲート抵抗を用い、過熱遮断または過電流保護動作を行う場合にはＭ５をオンし、ゲート抵抗の電圧降下によりパワーＭＯＳＦＥＴ（Ｍ０）の電流制御または電流遮断を行っていた。これに対し本実施例ではゲート抵抗の代わりにＰチャネルＭＯＳＦＥＴ（Ｍ７）を用いていることが特徴である。本実施形態では、パワーＭＯＳＦＥＴ（Ｍ０）が正常動作している場合にはＰチャネルＭＯＳＦＥＴ（Ｍ７）がオン状態、ＮチャネルＭＯＳＦＥＴ（Ｍ５）がオフ状態である。このため、駆動回路１０の出力電圧はそのまま等価的に低いゲート抵抗を介して、パワーＭＯＳＦＥＴ（Ｍ０）のゲート端子（４）に印加される。一方、パワーＭＯＳＦＥＴが過熱状態または過電流状態になった場合には制御回路（１１）により、ＰチャネルＭＯＳＦＥＴ（Ｍ７）がオフ、ＮチャネルＭＯＳＦＥＴ（Ｍ５）がオンする。この時、駆動回路１０の出力端子は、パワーＭＯＳＦＥＴ（Ｍ０）のゲート端子（４）と遮断され、保護動作時の低いドレイン電流がＮチャネルＭＯＳＦＥＴ（Ｍ５）によりバイパスされるので、パワーＭＯＳＦＥＴ（Ｍ０）を高速に遮断できる。なお、外部ゲート端子（２）の電圧を下げた場合にはＰチャネルＭＯＳＦＥＴ（Ｍ７）のドレイン・ボディ間寄生ダイオ−ドに電流が流れて本体パワーＭＯＳＦＥＴ（Ｍ０）が遮断する。
従来の過熱遮断回路内蔵パワーＭＯＳＦＥＴの回路例では、ゲート抵抗を５ｋΩ程度と高くし、前記保護回路用ＭＯＳＦＥＴには遮断状態に１〜２ｍＡ程度の大電流を流すことにより、外部ゲート端子の電圧を５〜１０Ｖ程度降圧し、本体のパワーＭＯＳＦＥＴを遮断していた。このため、従来の過熱遮断回路用パワーＭＯＳＦＥＴは高周波のパルス駆動は不可能であり、また、ゲート遅延時間が大きくなるためスイッチング損失が大きくなるという問題があった。また、過熱遮断回路が働いた後のゲート電流が高いため、駆動回路の消費電力が高くなるという問題があった。
これに対し、図１の本発明の実施例では通常の駆動時には、等価的なゲート抵抗が小さいため高周波のパルス駆動が可能でスイッチング損失も小さいという利点がある。また、遮断動作時には等価的ゲート抵抗が高くなるため、過熱遮断回路が働いた後のゲート電流が小さく、過熱遮断のためのスイッチング時間が短くなるという利点がある。 FIG. 1 is a circuit diagram of a first embodiment of the present invention. This embodiment is a protection circuit that prevents destruction of the power MOSFET by limiting or blocking the drain current even when the power MOSFET becomes overheated or overcurrent due to a load short circuit accident or deterioration of heat dissipation conditions. In this figure, M0 is a power MOSFET, 12 is a temperature detection circuit or current detection circuit of M0, and 11 is a control circuit of M5 and M7. In the conventional overcurrent or overheat protection circuit, a gate resistor is used between the gate terminal 4 of the power MOSFET (M0) and the drive circuit 10, and M5 is turned on to perform overheat cutoff or overcurrent protection operation. The current of the power MOSFET (M0) is controlled or interrupted by a voltage drop across the resistor. On the other hand, this embodiment is characterized in that a P-channel MOSFET (M7) is used instead of the gate resistance. In the present embodiment, when the power MOSFET (M0) is operating normally, the P-channel MOSFET (M7) is on and the N-channel MOSFET (M5) is off. For this reason, the output voltage of the drive circuit 10 is applied as it is to the gate terminal (4) of the power MOSFET (M0) through an equivalently low gate resistance. On the other hand, when the power MOSFET is overheated or overcurrent, the control circuit (11) turns off the P-channel MOSFET (M7) and turns on the N-channel MOSFET (M5). At this time, the output terminal of the drive circuit 10 is disconnected from the gate terminal (4) of the power MOSFET (M0), and the low drain current during the protection operation is bypassed by the N-channel MOSFET (M5). ) Can be cut off at high speed. When the voltage at the external gate terminal (2) is lowered, a current flows through the drain-body parasitic diode of the P-channel MOSFET (M7) and the main power MOSFET (M0) is cut off.
In the circuit example of a conventional power MOSFET with a built-in overheat cutoff circuit, the gate resistance is increased to about 5 kΩ, and a large current of about 1 to 2 mA is applied to the protection circuit MOSFET in the cutoff state, whereby the voltage of the external gate terminal is increased. The voltage was lowered by about 5 to 10 V to shut off the power MOSFET of the main body. For this reason, the conventional power MOSFET for an overheat cutoff circuit cannot drive a high-frequency pulse, and has a problem that a switching loss is increased because a gate delay time is increased. Further, since the gate current after the overheat cutoff circuit is activated is high, there is a problem that the power consumption of the drive circuit becomes high.
On the other hand, the embodiment of the present invention shown in FIG. 1 has an advantage that high-frequency pulse driving is possible and switching loss is small because the equivalent gate resistance is small during normal driving. Further, since the equivalent gate resistance is increased during the shut-off operation, there is an advantage that the gate current after the overheat shut-off circuit is activated is small and the switching time for the overheat shut-off is shortened.

図２は本発明の第２の実施例の回路図である。本実施例は図１のブロック回路的な実施例を実際の回路で表したものである。本実施例ではパワーＭＯＳＦＥＴの温度検出回路として抵抗Ｒ４とダイオード列Ｄ１〜Ｄ４を使用している。通常の動作時には、ゲート電圧が外部ゲート端子２に印加された時、Ｍ１はオン状態になる。また、非対称型フリップフロップ構成のラッチ回路の出力は抵抗Ｒ１を抵抗Ｒ２より十分高く設定することにより低電圧状態になる。このため、Ｍ７はオン状態、Ｍ５はオフ状態となり、外部ゲート端子２に電圧が印加される時の等価的なゲート抵抗は低くなる。一方、負荷短絡事故等が発生しパワーＭＯＳＦＥＴの温度が上昇するとＭ１がオフし、ラッチ回路の状態が反転し、Ｍ７がオフする。このため、遮断動作時には等価的ゲート抵抗が高くなる。また、Ｍ５がオンするためパワーＭＯＳＦＥＴ（Ｍ０）を高速に遮断でき、遮断動作後のゲート電流が小さいという利点がある。   FIG. 2 is a circuit diagram of a second embodiment of the present invention. In this embodiment, the block circuit embodiment of FIG. 1 is represented by an actual circuit. In this embodiment, a resistor R4 and diode arrays D1 to D4 are used as a temperature detection circuit for the power MOSFET. During normal operation, when a gate voltage is applied to the external gate terminal 2, M1 is turned on. Further, the output of the latch circuit having the asymmetric flip-flop configuration becomes a low voltage state by setting the resistor R1 sufficiently higher than the resistor R2. For this reason, M7 is turned on, M5 is turned off, and the equivalent gate resistance when a voltage is applied to the external gate terminal 2 is lowered. On the other hand, when a load short circuit accident or the like occurs and the temperature of the power MOSFET rises, M1 is turned off, the state of the latch circuit is inverted, and M7 is turned off. For this reason, equivalent gate resistance becomes high at the time of interruption | blocking operation | movement. Further, since M5 is turned on, there is an advantage that the power MOSFET (M0) can be shut off at high speed and the gate current after the shutoff operation is small.

図３は本発明の第３の実施例の半導体装置の断面図である。本実施例は図２の回路で、１を外部ドレイン、２を外部ゲート、３を外部ソースとして、１チップ化するための半導体装置の断面構造である。１０１５は本体パワーＭＯＳＦＥＴ（図２のＭ０）のドレイン電極、１０００はＮ型エピタキシャル領域で本体パワーＭＯＳＦＥＴのドレイン領域、１００７ａはゲート用多結晶シリコン層、１０１２ａはＮ型拡散層で本体パワーＭＯＳＦＥＴのソース拡散層、１００８はボディ領域となるＰ型拡散層、１０１１ａはボディ領域のコンタクト抵抗低減のためのＰ型拡散層である。また、図の右側にはＭ５等に用いる保護回路用のＮチャネルＭＯＳＦＥＴを示す。１０１２ｂはドレインまたはソース用のＮ型拡散層、１００５はＰ型ウエル拡散層、１０１１ｂはボディ領域のコンタクト抵抗低減のためのＰ型拡散層、１００７ｂはゲート用多結晶シリコン層である。また、中央にはＭ７に用いる保護回路用ＰチャネルＭＯＳＦＥＴを示してある。１００７ｄと１００７ｅは１００７ａと同一工程で形成される多結晶シリコン層で、１００７ｅは低濃度のＮ型不純物をドープしたボディ領域、１００７ｄは１０１１ａの高濃度Ｐ型ドープと同一工程により高濃度Ｐ型領域にしてある。また、１０１０は多結晶シリコンゲート層である。
本実施例の特長は、Ｍ７に用いるＰチャネルＭＯＳＦＥＴを絶縁層１００６により本体パワーＭＯＳＦＥＴと分離された領域に形成してある点である。このため、本実施例では、従来のパワーＭＯＳＦＥＴ製造プロセスとほぼ同様な低コストプロセスで図２に示した高性能化した過熱遮断回路パワーＭＯＳＦＥＴを実現できるという利点がある。 FIG. 3 is a sectional view of a semiconductor device according to a third embodiment of the present invention. This embodiment is a cross-sectional structure of a semiconductor device for forming a single chip, with 1 being an external drain, 2 being an external gate, and 3 being an external source. 1015 is a drain electrode of the main power MOSFET (M0 in FIG. 2), 1000 is an N type epitaxial region and a drain region of the main power MOSFET, 1007a is a polycrystalline silicon layer for a gate, 1012a is an N type diffusion layer and a source of the main power MOSFET A diffusion layer, 1008 is a P-type diffusion layer serving as a body region, and 1011a is a P-type diffusion layer for reducing contact resistance of the body region. Further, an N-channel MOSFET for a protection circuit used for M5 and the like is shown on the right side of the figure. 1012b is an N-type diffusion layer for drain or source, 1005 is a P-type well diffusion layer, 1011b is a P-type diffusion layer for reducing contact resistance of the body region, and 1007b is a polycrystalline silicon layer for gate. In the center, a protection circuit P-channel MOSFET used for M7 is shown. 1007d and 1007e are polycrystalline silicon layers formed in the same process as 1007a, 1007e is a body region doped with low-concentration N-type impurities, and 1007d is a high-concentration P-type region in the same process as 1011a high-concentration P-type doping. It is. Reference numeral 1010 denotes a polycrystalline silicon gate layer.
The feature of this embodiment is that the P-channel MOSFET used for M7 is formed in a region separated from the main body power MOSFET by the insulating layer 1006. For this reason, the present embodiment has an advantage that the high-performance overheat cutoff circuit power MOSFET shown in FIG. 2 can be realized by a low-cost process substantially similar to the conventional power MOSFET manufacturing process.

図４は本発明の第４の実施例の半導体装置である。本実施例も図２の回路で、１を外部ドレイン、２を外部ゲート、３を外部ソースとして、１チップ化するための半導体装置の断面構造である。本実施例では誘電体分離構造で本発明の回路を実現している。本構造では最初にＮ型基板１０００の下側に溝を形成、高濃度Ｎ型埋込層１００１の形成、絶縁酸化膜１００２の形成を行った後、パワーＭＯＳＦＥＴ部直下の酸化膜１００２を除去し、シリコン層（１００３と１００４）の形成を行う。このとき、絶縁酸化膜１００２の下には多結晶シリコン層１００３、絶縁酸化膜１００２を除去した領域には単結晶シリコン層１００４が形成される。この後、Ｎ型シリコン層１０００の上側を削り平坦化し、通常のパワーＭＯＳＦＥＴと同様の工程を経ることにより本構造が得られる。本実施例の場合にはＭ７に用いるＰチャネルＭＯＳＦＥＴは絶縁層１００２により本体パワーＭＯＳＦＥＴと分離された領域に形成してある。このため、図３の実施例の場合と同様にＰチャネルＭＯＳＦＥＴのソースまたはドレインと本体パワーＭＯＳＦＥＴのドレインを分離できる。本実施例は図３に比べ製造方法が複雑になるが、ＰチャネルＭＯＳＦＥＴを単結晶シリコン層内に形成できるため、図３の場合に比べＰチャネルＭＯＳＦＥＴのオン抵抗を下げやすいという利点がある。また、Ｍ５等の保護回路用ＮチャネルＭＯＳＦＥＴも本体パワーＭＯＳＦＥＴと絶縁層１００２により分離して形成できるため、寄生バイポーラトランジスタの動作等による誤動作を防止できるという利点がある。   FIG. 4 shows a semiconductor device according to a fourth embodiment of the present invention. This embodiment also has a cross-sectional structure of a semiconductor device for forming a single chip in the circuit of FIG. 2, wherein 1 is an external drain, 2 is an external gate, and 3 is an external source. In this embodiment, the circuit of the present invention is realized by a dielectric separation structure. In this structure, first, after forming a trench under the N-type substrate 1000, forming a high-concentration N-type buried layer 1001, and forming an insulating oxide film 1002, the oxide film 1002 immediately below the power MOSFET portion is removed. The silicon layers (1003 and 1004) are formed. At this time, a polycrystalline silicon layer 1003 is formed under the insulating oxide film 1002, and a single crystal silicon layer 1004 is formed in a region where the insulating oxide film 1002 is removed. Thereafter, the upper side of the N-type silicon layer 1000 is shaved and flattened, and this structure is obtained through the same process as that of a normal power MOSFET. In this embodiment, the P-channel MOSFET used for M7 is formed in a region separated from the main power MOSFET by the insulating layer 1002. Therefore, the source or drain of the P-channel MOSFET and the drain of the main power MOSFET can be separated as in the embodiment of FIG. Although the manufacturing method of this embodiment is more complicated than that of FIG. 3, since the P-channel MOSFET can be formed in the single crystal silicon layer, there is an advantage that the on-resistance of the P-channel MOSFET can be easily lowered compared to the case of FIG. Further, since the N-channel MOSFET for the protection circuit such as M5 can be formed separately from the main body power MOSFET and the insulating layer 1002, there is an advantage that malfunction due to the operation of the parasitic bipolar transistor can be prevented.

図５は本発明の第５の実施例の半導体装置である。本実施例では本体パワーＭＯＳＦＥＴ（Ｍ０）と、保護回路用のＮチャネルＭＯＳＦＥＴ（Ｍ５）と前記温度検出回路または電流検出回路（１２）を第１の半導体チップ（１０４）に内蔵し、保護回路用のＰチャネルＭＯＳＦＥＴ（Ｍ７）を第２の半導体チップ（１０６）に形成し破線で示す同一の樹脂封止パッケージ中に実装したことを特徴とするものである。第１の半導体チップ（１０４）では裏面が本体パワーＭＯＳＦＥＴのドレインであるため、第２の半導体チップ（１０６）は絶縁板（１０５）の上に形成し、ＰチャネルＭＯＳＦＥＴ（Ｍ７）と本体パワーＭＯＳＦＥＴ（Ｍ０）を分離している。１１０は本体パワーＭＯＳＦＥＴのゲート端子用パッド（図２の４に対応）、１１１は本体パワーＭＯＳＦＥＴのソース端子用パッド、１１２はＭ７のゲート端子を制御するための端子用パッド、１１３は第１の半導体チップ上の外部ゲート端子用パッドで制御回路部の電源電圧を供給する。また、１０７はＭ７のドレイン端子用パッド、１０８はＭ７のゲート端子用パッド、１０９はＭ７のソース端子用パッドである。本実施例では実装方式を改良することにより、ＰチャネルＭＯＳＦＥＴであるＭ７を本体パワーＭＯＳＦＥＴと同一パッケージに実装し小型化した。本実施例によっても図３や図４で示した１チップで実現する保護回路内蔵パワーＭＯＳＦＥＴと同様の効果が得られる。   FIG. 5 shows a semiconductor device according to a fifth embodiment of the present invention. In this embodiment, the main body power MOSFET (M0), the N-channel MOSFET (M5) for the protection circuit, and the temperature detection circuit or current detection circuit (12) are built in the first semiconductor chip (104), and are used for the protection circuit. The P-channel MOSFET (M7) is formed on the second semiconductor chip (106) and mounted in the same resin-encapsulated package indicated by a broken line. Since the back surface of the first semiconductor chip (104) is the drain of the main body power MOSFET, the second semiconductor chip (106) is formed on the insulating plate (105), and the P channel MOSFET (M7) and the main body power MOSFET are formed. (M0) is separated. 110 is a gate terminal pad of the main power MOSFET (corresponding to 4 in FIG. 2), 111 is a source terminal pad of the main power MOSFET, 112 is a terminal pad for controlling the gate terminal of M7, and 113 is a first pad. The power supply voltage of the control circuit section is supplied by an external gate terminal pad on the semiconductor chip. Reference numeral 107 denotes an M7 drain terminal pad, 108 denotes an M7 gate terminal pad, and 109 denotes an M7 source terminal pad. In this embodiment, by improving the mounting system, the M7, which is a P-channel MOSFET, is mounted in the same package as the main body power MOSFET to reduce the size. Also in this embodiment, the same effect as that of the power MOSFET with a built-in protection circuit realized by one chip shown in FIGS. 3 and 4 can be obtained.

図６は本発明の第６の実施例の回路図である。本実施例では図２の抵抗Ｒ１、Ｒ２、Ｒ３、Ｒ４をＰチャネルＭＯＳＦＥＴ Ｍ９、Ｍ１０、Ｍ８、Ｍ６に置き換えた場合の実施例である。本実施例では図２の場合に比べ保護回路の占有面積を小さくすることができ、また、保護回路部のスイッチング速度が高速化できるという効果がある。ここで、ＰチャネルＭＯＳＦＥＴ Ｍ９、Ｍ１０、Ｍ８、Ｍ６は図３や図４の半導体素子構造を用いることによりＭ７と同様に本体素子と同一チップに共存可能である。また、ＰチャネルＭＯＳＦＥＴ Ｍ９、Ｍ１０、Ｍ８、Ｍ１１は図５の第２の半導体チップ１０６に共存させることにより、本体パワーＭＯＳＦＥＴと同一パッケージに形成することも可能である。   FIG. 6 is a circuit diagram of a sixth embodiment of the present invention. In this embodiment, the resistors R1, R2, R3, and R4 in FIG. 2 are replaced with P-channel MOSFETs M9, M10, M8, and M6. In this embodiment, the area occupied by the protection circuit can be reduced as compared with the case of FIG. 2, and the switching speed of the protection circuit section can be increased. Here, the P-channel MOSFETs M9, M10, M8, and M6 can coexist on the same chip as the main body element similarly to M7 by using the semiconductor element structure of FIGS. Further, the P-channel MOSFETs M9, M10, M8, and M11 can be formed in the same package as the main body power MOSFET by coexisting with the second semiconductor chip 106 of FIG.

図７は本発明の第７の実施例の回路図である。本実施例では図２のＰチャネルＭＯＳＦＥＴの代わりにデプレッション型ＮチャネルＭＯＳＦＥＴ（Ｍ１２）を用いた場合の実施例である。ここで、デプレッション型ＮチャネルＭＯＳＦＥＴ（Ｍ１２）はスイッチング素子または可変ゲート抵抗として振る舞う。すなわち、パワーＭＯＳＦＥＴ（Ｍ０）が正常動作している場合にはＭ１２のゲート電圧は高電位のためＭ１２はオン状態（低インピーダンス状態）、第３のスイッチング素子であるＮチャネルＭＯＳＦＥＴ（Ｍ５）はオフ状態である。このため、外部ゲート端子２の電圧はそのまま等価的に低いゲート抵抗を介して、パワーＭＯＳＦＥＴ（Ｍ０）のゲート端子（４）に印加される。このため、高周波パルス駆動回路にも低損失で使用可能である。一方、パワーＭＯＳＦＥＴが過熱状態になった場合にはＭ１２のゲート電位が下がるためＭ１２はほぼオフ状態または高インピーダンス状態になり、また、ＮチャネルＭＯＳＦＥＴ（Ｍ５）はオンする。このため、ＮチャネルＭＯＳＦＥＴ（Ｍ５）の電流駆動能力が低くても本体パワーＭＯＳＦＥＴ（Ｍ０）を高速に遮断できるという効果がある（図２の実施例と同様の効果がある）。本実施例のデプレッション型ＮチャネルＭＯＳＦＥＴ（Ｍ１２）は図３の制御用ＮチャネルＭＯＳＦＥＴと同様にＰ型ウエル構造の中に形成し、ゲート直下のＰ型ウエルの表面だけをイオン打ち込みによりＮ型化することにより実現できる。本実施例では、図３や図４に比べ半導体装置の製造方法が簡単であるという利点がある。なお、Ｍ１２はエンハンス型素子を使用することも可能である。また、多結晶シリコンダイオードＤ６を追加した場合には外部ゲート端子２によるパワーＭＯＳＦＥＴ（Ｍ０）の遮断を高速に行なえるという効果がある。   FIG. 7 is a circuit diagram of a seventh embodiment of the present invention. In this embodiment, a depletion type N channel MOSFET (M12) is used instead of the P channel MOSFET of FIG. Here, the depletion type N-channel MOSFET (M12) behaves as a switching element or a variable gate resistance. That is, when the power MOSFET (M0) is operating normally, the gate voltage of M12 is high, so that M12 is on (low impedance state), and the third switching element N-channel MOSFET (M5) is off. State. For this reason, the voltage of the external gate terminal 2 is applied as it is to the gate terminal (4) of the power MOSFET (M0) through an equivalently low gate resistance. For this reason, it can be used in a high-frequency pulse drive circuit with low loss. On the other hand, when the power MOSFET is overheated, the gate potential of M12 is lowered, so that M12 is almost turned off or in a high impedance state, and the N-channel MOSFET (M5) is turned on. For this reason, even if the current drive capability of the N-channel MOSFET (M5) is low, the main body power MOSFET (M0) can be shut off at high speed (the same effect as in the embodiment of FIG. 2). The depletion type N channel MOSFET (M12) of this embodiment is formed in a P type well structure like the control N channel MOSFET of FIG. 3, and only the surface of the P type well just under the gate is made N type by ion implantation. This can be achieved. In this embodiment, there is an advantage that the manufacturing method of the semiconductor device is simpler than those in FIGS. Note that M12 can use an enhanced element. Further, when the polycrystalline silicon diode D6 is added, there is an effect that the power MOSFET (M0) can be shut off by the external gate terminal 2 at high speed.

図８は本発明の第８の実施例の回路図である。本実施例では図７の抵抗Ｒ１、Ｒ２、Ｒ３、Ｒ４をデプレッション型ＮチャネルＭＯＳＦＥＴ Ｍ１４、Ｍ１５、Ｍ１３、Ｒ１１に置き換えた場合の実施例である。本実施例の場合には図７の場合に比べ、保護回路の占有面積を小さくすることができ、また、保護回路部のスイッチング速度が高速化できるという利点がある。   FIG. 8 is a circuit diagram of an eighth embodiment of the present invention. In this embodiment, the resistors R1, R2, R3 and R4 in FIG. 7 are replaced with depletion type N-channel MOSFETs M14, M15, M13 and R11. Compared with the case of FIG. 7, this embodiment has the advantage that the area occupied by the protection circuit can be reduced and the switching speed of the protection circuit section can be increased.

図９は本発明の第９の実施例の回路図である。これまでの実施例では、過熱遮断回路内蔵パワーＭＯＳＦＥＴを例にとり説明してきたが、本実施例では過電流遮断回路内蔵パワーＭＯＳＦＥＴを用いた場合を示してある。本実施例では大きなサイズ（大きなチャネル幅）の本体パワーＭＯＳＦＥＴ（Ｍ０）と同一チップに小さなサイズ（小さなチャネル幅）のセンス用ＭＯＳＦＥＴ（Ｍ１５）を所謂カレントミラー接続して内蔵し、本体パワーＭＯＳＦＥＴ（ＭＯ）に過電流が流れた場合にセンス用ＭＯＳＦＥＴ（Ｍ１５）にもセンス電流が流れる電流検出回路を実現している。通常、外部ゲート端子に電圧が印加されるとセンス用ＭＯＳＦＥＴ（Ｍ１５）のソース電位（５）が低電位のためＭ５はオフ、Ｍ１７はオフ、Ｍ１６はオン、Ｍ７はオン状態である。このため、外部ゲート端子（２）の印加電圧はそのまま等価的に低いゲート抵抗を介して、パワーＭＯＳＦＥＴ（Ｍ０）のゲート端子（４）に印加される。一方、パワーＭＯＳＦＥＴが過電流状態になった場合にはＭ１５のソース電圧が増加するため、上記と逆にＰチャネルＭＯＳＦＥＴ（Ｍ７）がオフ、ＮチャネルＭＯＳＦＥＴ（Ｍ５）がオンする。このため、低電流駆動能力を有するＮチャネルＭＯＳＦＥＴ（Ｍ５）を用いてもパワーＭＯＳＦＥＴ（Ｍ０）を高速に遮断できる。本実施例では抵抗Ｒ５〜Ｒ８の値、Ｍ７のオン抵抗、Ｍ５、Ｍ１６、Ｍ１７の電流駆動能力の設計値により、過電流時に本体パワーＭＯＳＦＥＴが遮断する過電流遮断回路内蔵パワーＭＯＳＦＥＴにも、電流を制御するだけの過電流制限回路内蔵パワーＭＯＳＦＥＴにもなる。本実施例の過電流保護回路を有する半導体装置も図３、図４、図５の実施例で述べた過熱保護回路内蔵パワーＭＯＳＦＥＴと同じ構造にて実現できる。   FIG. 9 is a circuit diagram of the ninth embodiment of the present invention. In the embodiments described so far, the power MOSFET with built-in overheat cutoff circuit has been described as an example. However, in this embodiment, the case where the power MOSFET with built-in overcurrent cutoff circuit is used is shown. In this embodiment, a large size (large channel width) main body power MOSFET (M0) and a small size (small channel width) sense MOSFET (M15) are incorporated in a so-called current mirror in the same chip, and the main body power MOSFET ( A current detection circuit is realized in which a sense current flows in the sense MOSFET (M15) when an overcurrent flows in (MO). Normally, when a voltage is applied to the external gate terminal, the source potential (5) of the sense MOSFET (M15) is low, so M5 is off, M17 is off, M16 is on, and M7 is on. Therefore, the voltage applied to the external gate terminal (2) is applied as it is to the gate terminal (4) of the power MOSFET (M0) through an equivalently low gate resistance. On the other hand, when the power MOSFET enters an overcurrent state, the source voltage of M15 increases, so that the P-channel MOSFET (M7) is turned off and the N-channel MOSFET (M5) is turned on contrary to the above. For this reason, even if it uses N channel MOSFET (M5) which has a low current drive capability, power MOSFET (M0) can be interrupted | blocked at high speed. In the present embodiment, the power MOSFET with a built-in overcurrent cutoff circuit that shuts off the main body power MOSFET in the event of an overcurrent also depends on the values of the resistors R5 to R8, the on-resistance of M7, and the design values of the current drive capability of M5, M16, and M17. It also becomes a power MOSFET with a built-in overcurrent limiting circuit that only controls. The semiconductor device having the overcurrent protection circuit of this embodiment can also be realized with the same structure as the power MOSFET with built-in overheat protection circuit described in the embodiments of FIGS.

以上、本発明の実施例を詳細に説明したが、本発明は上記の実施例に限定されるものではなく、その技術思想の範囲内で種々の変形が可能である。
例えば、以上の実施例では本体素子がパワーＭＯＳＦＥＴの場合に関して述べたが、本発明の回路技術は本体素子として、バイポーラトランジスタや絶縁ゲート型バイポーラトランジスタ（ＩＧＢＴ）を用いた場合にも適用可能であることは言うまでもない。 As mentioned above, although the Example of this invention was described in detail, this invention is not limited to said Example, A various deformation | transformation is possible within the range of the technical thought.
For example, in the above embodiments, the case where the main body element is a power MOSFET has been described. However, the circuit technology of the present invention can also be applied to a case where a bipolar transistor or an insulated gate bipolar transistor (IGBT) is used as the main body element. Needless to say.

１、１０１…外部ドレイン端子、２、１００…外部ゲート端子、３、１０２…外部ソース端子、４…本体パワーＭＯＳＦＥＴの内部ゲート端子、５…センスＭＯＳＦＥＴのソース端子、１０…駆動回路、１１…制御回路、１２…パワーＭＯＳＦＥＴの温度検出回路または電流検出回路、
１０４…Ｍ０と温度検出回路または電流検出回路を内蔵する第１の半導体チップ、１０５…絶縁板、１０６…Ｍ７を内蔵する第２の半導体チップ、１０７…第２の半導体チップ上の本体パワーＭＯＳＦＥＴの内部ゲート用パッド、１０８…第２の半導体チップ上の本体パワーＭＯＳＦＥＴの内部ゲート用パッド、１０９…第２の半導体チップ上の外部ゲート端子用パッド、１１０…第１の半導体チップ上の本体パワーＭＯＳＦＥＴの内部ゲート用パッド１１１…第１の半導体チップ上の外部ソース用パッド、１１２…Ｍ７またはＭ１２のゲート制御用端子パッド、１１３…第１の半導体チップ上の外部ゲート用パッド、１０４…Ｍ０と温度検出回路または電流検出回路を内蔵する第１の半導体チップ、
１０００…Ｎ型基板またはＮ型エピタキシャル層、１００１…高濃度Ｎ型埋込層、１００２、１００６、１００９、１０１３…絶縁層、１００３…高濃度Ｎ型多結晶シリコン層、１００４…高濃度Ｎ型単結晶シリコン層、１００５…Ｐ型ウエル拡散層、１００７ａ、１００７ｂ、１００７ｃ…多結晶シリコン層、１００８…Ｐ型チャネル拡散層、１０１０…多結晶シリコン層（制御回路用Ｐ型ＭＯＳＦＥＴ部ゲート用）、１０１１ａ、１０１１ｂ…高濃度Ｐ型拡散層、１０１２ａ、１０１２ｂ…高濃度Ｎ型拡散層、１０１４、１０１５…電極層、
Ｒ１〜Ｒ８…抵抗、Ｄ１〜Ｄ６…ダイオ−ド、Ｍ０…パワーＭＯＳＦＥＴ、Ｍ１〜Ｍ５、Ｍ１６、Ｍ１７…制御用ＮチャネルＭＯＳＦＥＴ、Ｍ６、Ｍ７、Ｍ８〜Ｍ１０…制御用ＰチャネルＭＯＳＦＥＴ、Ｍ１１〜Ｍ１５…制御用デプレッション型ＮチャネルＭＯＳＦＥＴ。 DESCRIPTION OF SYMBOLS 1,101 ... External drain terminal 2,100 ... External gate terminal 3,102 ... External source terminal, 4 ... Internal gate terminal of main body power MOSFET, 5 ... Source terminal of sense MOSFET, 10 ... Drive circuit, 11 ... Control Circuit, 12 ... power MOSFET temperature detection circuit or current detection circuit,
104... M0 and a first semiconductor chip incorporating a temperature detection circuit or current detection circuit, 105... An insulating plate, 106... A second semiconductor chip incorporating M7, and 107 ... a main power MOSFET on the second semiconductor chip. Internal gate pad 108... Internal power pad of main power MOSFET on second semiconductor chip 109. External gate terminal pad on second semiconductor chip 110. Main power MOSFET on first semiconductor chip , Internal gate pad 111... External source pad on the first semiconductor chip, 112... M7 or M12 gate control terminal pad, 113... External gate pad on the first semiconductor chip, 104. A first semiconductor chip incorporating a detection circuit or a current detection circuit;
DESCRIPTION OF SYMBOLS 1000 ... N type substrate or N type epitaxial layer, 1001 ... High concentration N type buried layer, 1002, 1006, 1009, 1013 ... Insulating layer, 1003 ... High concentration N type polycrystalline silicon layer, 1004 ... High concentration N type single Crystal silicon layer, 1005... P-type well diffusion layer, 1007a, 1007b, 1007c .. Polycrystalline silicon layer, 1008... P-type channel diffusion layer, 1010... Polycrystalline silicon layer (for P-type MOSFET for control circuit gate), 1011a 1011b ... High-concentration P-type diffusion layer, 1012a, 1012b ... High-concentration N-type diffusion layer, 1014, 1015 ... Electrode layer,
R1 to R8, resistors, D1 to D6, diodes, M0, power MOSFETs, M1 to M5, M16, M17, control N-channel MOSFETs, M6, M7, M8 to M10, control P-channel MOSFETs, M11 to M15 ... Depletion type N-channel MOSFET for control.

Claims (4)

第１、第２、第３外部端子を備え、第１半導体チップと第２半導体チップを同一パッケージ内に実装した半導体装置であって、
前記第１半導体チップは第１ソース端子用パッドと第１ゲート端子用パッドと、制御回路出力端子パッドと、制御回路電源端子パッドを備え、
前記第２半導体チップは第２ドレイン端子用パッドと第２ゲート端子用パッドと第２ソース端子用パッドを備え、
前記第１半導体チップの裏面は前記第１外部端子に接続され、
前記第１ソース端子用パッドは前記第３外部端子に接続され、
前記制御回路電源端子パッドと第２ソース端子用パッドは前記第２外部端子に接続され、
前記第１ゲート端子用パッドと前記第２ドレイン端子用パッド、及び前記制御回路出力端子パッドと第２ゲート端子用パッドはそれぞれ前記パッケージ内部で接続され、
前記第１外部端子は前記第１半導体チップと前記第２半導体チップが搭載される導電板と接続され、
前記第２半導体チップは絶縁板を介して前記導電板上に搭載され、
前記第１半導体チップはパワーＭＯＳＦＥＴと温度検出回路とラッチ回路を含み、
前記パワーＭＯＳＦＥＴのソース端子は前記第１ソース端子用パッドに、ゲート端子は第１ゲート端子用パッドにそれぞれ接続され、
前記パワーＭＯＳＦＥＴのドレイン端子は前記第１半導体チップの裏面であり、
前記制御回路電源端子パッドと、前記温度検出回路と前記ラッチ回路の電源が接続され、
前記制御回路出力端子パッドには前記ラッチ回路の出力端子が接続され、
前記第２の半導体チップはＰチャネルＭＯＳＦＥＴを含み、
前記第２ドレイン端子用パッドと前記ＰチャネルＭＯＳＦＥＴのドレイン端子、前記第２ゲート端子用パッドと前記ＰチャネルＭＯＳＦＥＴのゲート端子、前記第２ソース端子用パッドと前記ＰチャネルＭＯＳＦＥＴのソース端子がそれぞれ接続されていることを特徴とする半導体装置。 A semiconductor device comprising first, second and third external terminals, wherein the first semiconductor chip and the second semiconductor chip are mounted in the same package,
The first semiconductor chip includes a first source terminal pad, a first gate terminal pad, a control circuit output terminal pad, and a control circuit power terminal pad.
The second semiconductor chip includes a second drain terminal pad, a second gate terminal pad, and a second source terminal pad,
A back surface of the first semiconductor chip is connected to the first external terminal;
The first source terminal pad is connected to the third external terminal;
The control circuit power supply terminal pad and the second source terminal pad are connected to the second external terminal,
The first gate terminal pad and the second drain terminal pad, and the control circuit output terminal pad and the second gate terminal pad are connected inside the package, respectively.
The first external terminal is connected to a conductive plate on which the first semiconductor chip and the second semiconductor chip are mounted,
The second semiconductor chip is mounted on the conductive plate via an insulating plate,
The first semiconductor chip includes a power MOSFET, a temperature detection circuit, and a latch circuit,
The power MOSFET has a source terminal connected to the first source terminal pad and a gate terminal connected to the first gate terminal pad,
The drain terminal of the power MOSFET is the back surface of the first semiconductor chip,
The control circuit power supply terminal pad, the temperature detection circuit and the power supply of the latch circuit are connected,
An output terminal of the latch circuit is connected to the control circuit output terminal pad,
The second semiconductor chip includes a P-channel MOSFET;
The second drain terminal pad and the drain terminal of the P channel MOSFET, the second gate terminal pad and the gate terminal of the P channel MOSFET, and the second source terminal pad and the source terminal of the P channel MOSFET are connected to each other. A semiconductor device which is characterized by being made . 前記第１半導体チップは前記導電板上で前記第３外部端子に近い側に配置されていることを特徴とする請求項１記載の半導体装置。 The semiconductor device according to claim 1, wherein said first semiconductor chip, characterized in that it is arranged closer to the third external terminal on the conductive plate. 前記第２半導体チップは前記導電板上で前記第２外部端子に近い側に配置されていることを特徴とする請求項１記載の半導体装置。 The semiconductor device according to claim 1, wherein said second semiconductor chip, characterized in that it is arranged closer to the second external terminal on the conductive plate. 前記導電板は一部が前記パッケージを形成する樹脂より一部が露出していることを特徴とする請求項１記載の半導体装置。 The semiconductor device according to claim 1, wherein said conductive plate is of a part and a part of a resin forming the package is exposed.
JP2009247256A 1993-02-22 2009-10-28 Semiconductor device Expired - Lifetime JP4605613B2 (en)

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JP5031579A JP3018816B2 (en) 1993-02-22 1993-02-22 Semiconductor element protection circuit and semiconductor device having the same
JP17505599A JP3446665B2 (en) 1993-02-22 1999-06-22 Semiconductor element protection circuit and semiconductor device having the same
JP2003093135A JP4007450B2 (en) 1993-02-22 2003-03-31 Semiconductor device
JP2007025328A JP4437823B2 (en) 1993-02-22 2007-02-05 Semiconductor device
JP2009247256A JP4605613B2 (en) 1993-02-22 2009-10-28 Semiconductor device

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JP17505599A JP3446665B2 (en) 1993-02-22 1999-06-22 Semiconductor element protection circuit and semiconductor device having the same
JP2003093135A JP4007450B2 (en) 1993-02-22 2003-03-31 Semiconductor device
JP2007025328A JP4437823B2 (en) 1993-02-22 2007-02-05 Semiconductor device
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JP3018816B2 (en) 2000-03-13
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JP2003309264A (en) 2003-10-31
JP2010022069A (en) 2010-01-28
JPH06244414A (en) 1994-09-02
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JP4007450B2 (en) 2007-11-14
JP4437823B2 (en) 2010-03-24

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