JP4437823B2 - Semiconductor device - Google Patents
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- JP4437823B2 JP4437823B2 JP2007025328A JP2007025328A JP4437823B2 JP 4437823 B2 JP4437823 B2 JP 4437823B2 JP 2007025328 A JP2007025328 A JP 2007025328A JP 2007025328 A JP2007025328 A JP 2007025328A JP 4437823 B2 JP4437823 B2 JP 4437823B2
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- 239000004065 semiconductor Substances 0.000 title claims description 53
- 238000001514 detection method Methods 0.000 claims abstract description 26
- 239000011347 resin Substances 0.000 claims 1
- 229920005989 resin Polymers 0.000 claims 1
- 238000007789 sealing Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 12
- 238000009792 diffusion process Methods 0.000 description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 108091006146 Channels Proteins 0.000 description 7
- 210000000746 body region Anatomy 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 230000000903 blocking effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000013021 overheating Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
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- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
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- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- H01L2924/3025—Electromagnetic shielding
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Electronic Switches (AREA)
- Protection Of Static Devices (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
本発明は大電力を扱う半導体素子に係り、特に、大電力用半導体素子の過熱並びに過電流保護回路並びにこれを有する半導体装置に関する。 The present invention relates to a semiconductor element that handles high power, and more particularly, to an overheat and overcurrent protection circuit for a semiconductor element for high power and a semiconductor device having the same.
過熱遮断回路を内蔵するパワーMOSFETの例としては、特開昭63−229758号公報がある。この従来例では本体のパワーMOSFETのゲート端子と外部ゲート端子の間にゲート抵抗を、ゲート端子に保護回路用MOSFETを設け、本体パワーMOSFETが過熱状態になったとき保護回路用MOSFETをオンし、ゲート抵抗に電流を流すことにより、本体パワーMOSFETのゲート端子電圧を下げて本体パワーMOSFETを遮断し、過熱による素子破壊を防止していた。
この従来の過熱遮断回路内蔵パワーMOSFETの回路例では、外部ゲート端子の電圧を5〜10V程度降圧して、本体のパワーMOSFETを遮断する必要からゲート抵抗が大きく、遮断用電流も大きくなるという問題があった。例えばこの場合、ゲート抵抗を5kΩ程度にする必要があり、保護回路用MOSFETには過熱遮断動作時に1〜2mA程度の大電流を流す必要があった。このため、従来の過熱遮断回路用パワーMOSFETは高周波パルス駆動ではゲート遅延時間が大きくなりスイッチング損失が大きくなるという問題があった。また、過熱遮断動作時には保護回路用MOSFETがオンとなるので、外部ゲート端子のゲート電流が大きくなり、駆動回路の消費電力が大きくなるという問題があった。 In this conventional circuit example of a power MOSFET with a built-in overheat cutoff circuit, the voltage of the external gate terminal is lowered by about 5 to 10 V to cut off the power MOSFET of the main body, so that the gate resistance is large and the cutoff current is also large. was there. For example, in this case, the gate resistance needs to be about 5 kΩ, and a large current of about 1 to 2 mA needs to flow through the protection circuit MOSFET during the overheat cutoff operation. For this reason, the conventional power MOSFET for the overheat cutoff circuit has a problem in that the gate delay time is increased and the switching loss is increased in the high-frequency pulse drive. Further, since the protection circuit MOSFET is turned on during the overheat shut-off operation, there is a problem that the gate current of the external gate terminal increases and the power consumption of the drive circuit increases.
従って本発明の目的とするところは、高周波パルス駆動が可能でスイッチング損失が小さく、過熱遮断動作後のゲート電流も小さい、パワーMOSFETの保護回路ならびに保護回路を有する保護回路内蔵パワーMOSFETを提供することにある。 Accordingly, an object of the present invention is to provide a power MOSFET protection circuit and a power MOSFET with a built-in protection circuit, which can be driven by high frequency pulses, have low switching loss, and have a small gate current after an overheat cutoff operation. It is in.
上記目的を達成するために、本発明の一実施形態によれば、
第1のスイッチング素子(M0)の入力端子(4)とこの駆動回路(10)の間に第2のスイッチング素子(M7)または可変抵抗素子を設け、
前記第1のスイッチング素子(M0)の入力端子(4)に第3のスイッチング素子(M5)を設け、
さらに、前記第1のスイッチング素子(M0)の温度検出回路または電流検出回路(12)を設け、
この温度検出回路または電流検出回路(12)により、前記第3のスイッチング素子(M5)をオン、前記第2のスイッチング素子(M7)をオフまたは高インピーダンスとせしめることを特徴とするものである(図1参照)。
In order to achieve the above object, according to one embodiment of the present invention,
A second switching element (M7) or a variable resistance element is provided between the input terminal (4) of the first switching element (M0) and the drive circuit (10),
A third switching element (M5) is provided at the input terminal (4) of the first switching element (M0);
Furthermore, a temperature detection circuit or a current detection circuit (12) of the first switching element (M0) is provided,
By this temperature detection circuit or current detection circuit (12), the third switching element (M5) is turned on and the second switching element (M7) is turned off or has a high impedance. (See FIG. 1).
さらに、本発明の他の一実施形態によれば、前記第1のスイッチング素子(M0)と、前記第3のスイッチング素子(M5)と前記温度検出回路または電流検出回路(12)を第1の半導体チップ(104)に内蔵し、前記第2のスイッチング素子(M7)または前記可変抵抗素子を有する第2の半導体チップ(106)と同一パッケージに内蔵したことを特徴とするものである(図5参照)。 Furthermore, according to another embodiment of the present invention, the first switching element (M0), the third switching element (M5), and the temperature detection circuit or current detection circuit (12) are connected to the first switching element (M0). Built in a semiconductor chip (104) and built in the same package as the second semiconductor chip (106) having the second switching element (M7) or the variable resistance element (FIG. 5). reference).
さらに、本発明の好適な他の実施形態によれば、前記第2のスイッチング素子(M7)または前記可変抵抗素子が前記第1のスイッチング素子(M0)と絶縁層(1006または1002)を介して、同一チップ上に設けたことを特徴とするものである(図3と図4を参照)。 Furthermore, according to another preferred embodiment of the present invention, the second switching element (M7) or the variable resistance element is interposed between the first switching element (M0) and the insulating layer (1006 or 1002). Are provided on the same chip (see FIGS. 3 and 4).
本発明の代表的な実施形態では、負荷短絡事故または放熱条件の悪化によりパワーMOSFETが過熱状態または過電流状態になった場合でもドレイン電流を制限するか遮断することにより素子破壊を防止するパワーMOSFETの保護回路として、従来のゲート抵抗の代わりにPチャネルMOSFET(M7)を用いていることが特徴である(図1参照)。
本実施形態では、第1のスイッチング素子であるパワーMOSFET(M0)が正常動作している場合には第2のスイッチング素子であるPチャネルMOSFET(M7)がオン状態、第3のスイッチング素子であるNチャネルMOSFET(M5)がオフ状態である。このため、駆動回路10の出力電圧はそのまま等価的に低いゲート抵抗を介して、第1のスイッチング素子であるパワーMOSFET(M0)のゲート端子(4)に印加される。
ところが、パワーMOSFETが過熱状態または過電流状態になった場合には制御回路(11)により、第2のスイッチング素子であるPチャネルMOSFET(M7)がオフ状態、第3のスイッチング素子であるNチャネルMOSFET(M5)がオン状態になる。この時、駆動回路10の出力端子は、第1のスイッチング素子であるパワーMOSFET(M0)のゲート端子と遮断される。このため、保護動作時の低いドレイン電流がNチャネルMOSFET(M5)によりバイパスされパワーMOSFET(M0)を高速に遮断できる。
本発明の他の実施形態では、パワーMOSFETの温度をできるだけ正確に測定するため、またはパワーMOSFETの電流をカレントミラー構成で検出するために、温度検出回路または電流検出回路は本体のパワーMOSFET(M0)と同一の第1の半導体チップ(104)に形成し、第2のスイッチング素子であるPチャネルMOSFET(M7)はパワーMOSFET(M0)のドレイン領域(図3の1000)に形成することが不可能なため、第2の半導体チップ(106)に形成し、両チップの分離のため絶縁板(105)を前記第2の半導体チップ(106)の下に設けて同一パッケージに実装した。このため、前述の高性能な過熱保護回路または過電流保護回路を内蔵したパワーMOSFETを従来と同じ小型のパッケージに実装できるという利点がある(図5参照)。
また、他の実施形態として、PチャネルMOSFETを絶縁層(1006または1002)を介してパワーMOSFETのドレイン領域(1000)と分離することも可能である(図3または図4参照)。
本発明のその他の目的と特徴は、以下の実施例から明らかとなろう。
In a typical embodiment of the present invention, a power MOSFET that prevents element breakdown by limiting or blocking drain current even when the power MOSFET is overheated or overcurrent due to a load short circuit accident or deterioration of heat dissipation conditions. As a protection circuit, a P-channel MOSFET (M7) is used instead of the conventional gate resistance (see FIG. 1).
In this embodiment, when the power MOSFET (M0) that is the first switching element is operating normally, the P-channel MOSFET (M7) that is the second switching element is in the on state and is the third switching element. The N-channel MOSFET (M5) is in the off state. For this reason, the output voltage of the drive circuit 10 is directly applied to the gate terminal (4) of the power MOSFET (M0), which is the first switching element, via an equivalently low gate resistance.
However, when the power MOSFET is overheated or overcurrent, the control circuit (11) causes the P-channel MOSFET (M7), which is the second switching element, to be off, and the N-channel, which is the third switching element. The MOSFET (M5) is turned on. At this time, the output terminal of the drive circuit 10 is cut off from the gate terminal of the power MOSFET (M0) that is the first switching element. For this reason, the low drain current during the protection operation is bypassed by the N-channel MOSFET (M5), and the power MOSFET (M0) can be shut off at high speed.
In another embodiment of the present invention, in order to measure the temperature of the power MOSFET as accurately as possible, or to detect the current of the power MOSFET in a current mirror configuration, the temperature detection circuit or current detection circuit is a power MOSFET (M0) of the main body. ) On the same first semiconductor chip (104), and the P-channel MOSFET (M7) as the second switching element cannot be formed in the drain region (1000 in FIG. 3) of the power MOSFET (M0). Since it was possible, it formed in the 2nd semiconductor chip (106), the insulating board (105) was provided under the said 2nd semiconductor chip (106), and was mounted in the same package for isolation | separation of both chips | tips. Therefore, there is an advantage that the power MOSFET incorporating the above-described high-performance overheat protection circuit or overcurrent protection circuit can be mounted in the same small package as the conventional one (see FIG. 5).
In another embodiment, the P-channel MOSFET can be separated from the drain region (1000) of the power MOSFET through the insulating layer (1006 or 1002) (see FIG. 3 or FIG. 4).
Other objects and features of the present invention will become apparent from the following examples.
本発明によれば、高周波パルス駆動時にもスイッチング損失が小さく、また、本体素子の遮断動作後のゲート電流が小さく、遮断動作が高速な過熱保護または過電流保護回路内蔵パワーMOSFETが得られるという効果がある。 According to the present invention, the switching loss is small even during high-frequency pulse driving, the gate current after the shut-off operation of the main body element is small, and the overheat protection or power MOSFET with a built-in overcurrent protection circuit that has a fast shut-off operation can be obtained. There is.
図1は本発明の第1の実施例の回路図である。本実施例は負荷短絡事故または放熱条件の悪化によりパワーMOSFETが過熱状態または過電流状態になった場合でもドレイン電流を制限するか遮断することによりパワーMOSFETの破壊を防止する保護回路である。本図で、M0はパワーMOSFET、12はM0の温度検出回路または電流検出回路、11はM5とM7の制御回路である。従来の過電流または過熱保護回路ではパワーMOSFET(M0)のゲート端子4と駆動回路10との間にはゲート抵抗を用い、過熱遮断または過電流保護動作を行う場合にはM5をオンし、ゲート抵抗の電圧降下によりパワーMOSFET(M0)の電流制御または電流遮断を行っていた。これに対し本実施例ではゲート抵抗の代わりにPチャネルMOSFET(M7)を用いていることが特徴である。本実施形態では、パワーMOSFET(M0)が正常動作している場合にはPチャネルMOSFET(M7)がオン状態、NチャネルMOSFET(M5)がオフ状態である。このため、駆動回路10の出力電圧はそのまま等価的に低いゲート抵抗を介して、パワーMOSFET(M0)のゲート端子(4)に印加される。一方、パワーMOSFETが過熱状態または過電流状態になった場合には制御回路(11)により、PチャネルMOSFET(M7)がオフ、NチャネルMOSFET(M5)がオンする。この時、駆動回路10の出力端子は、パワーMOSFET(M0)のゲート端子(4)と遮断され、保護動作時の低いドレイン電流がNチャネルMOSFET(M5)によりバイパスされるので、パワーMOSFET(M0)を高速に遮断できる。なお、外部ゲート端子(2)の電圧を下げた場合にはPチャネルMOSFET(M7)のドレイン・ボディ間寄生ダイオ−ドに電流が流れて本体パワーMOSFET(M0)が遮断する。
従来の過熱遮断回路内蔵パワーMOSFETの回路例では、ゲート抵抗を5kΩ程度と高くし、前記保護回路用MOSFETには遮断状態に1〜2mA程度の大電流を流すことにより、外部ゲート端子の電圧を5〜10V程度降圧し、本体のパワーMOSFETを遮断していた。このため、従来の過熱遮断回路用パワーMOSFETは高周波のパルス駆動は不可能であり、また、ゲート遅延時間が大きくなるためスイッチング損失が大きくなるという問題があった。また、過熱遮断回路が働いた後のゲート電流が高いため、駆動回路の消費電力が高くなるという問題があった。
これに対し、図1の本発明の実施例では通常の駆動時には、等価的なゲート抵抗が小さいため高周波のパルス駆動が可能でスイッチング損失も小さいという利点がある。また、遮断動作時には等価的ゲート抵抗が高くなるため、過熱遮断回路が働いた後のゲート電流が小さく、過熱遮断のためのスイッチング時間が短くなるという利点がある。
FIG. 1 is a circuit diagram of a first embodiment of the present invention. This embodiment is a protection circuit that prevents destruction of the power MOSFET by limiting or blocking the drain current even when the power MOSFET becomes overheated or overcurrent due to a load short circuit accident or deterioration of heat dissipation conditions. In this figure, M0 is a power MOSFET, 12 is a temperature detection circuit or current detection circuit of M0, and 11 is a control circuit of M5 and M7. In a conventional overcurrent or overheat protection circuit, a gate resistor is used between the gate terminal 4 of the power MOSFET (M0) and the drive circuit 10, and M5 is turned on to perform overheat cutoff or overcurrent protection operation. Current control or current interruption of the power MOSFET (M0) is performed by a voltage drop of the resistor. On the other hand, this embodiment is characterized in that a P-channel MOSFET (M7) is used instead of the gate resistance. In the present embodiment, when the power MOSFET (M0) is operating normally, the P-channel MOSFET (M7) is on and the N-channel MOSFET (M5) is off. For this reason, the output voltage of the drive circuit 10 is applied as it is to the gate terminal (4) of the power MOSFET (M0) through an equivalently low gate resistance. On the other hand, when the power MOSFET is overheated or overcurrent, the control circuit (11) turns off the P-channel MOSFET (M7) and turns on the N-channel MOSFET (M5). At this time, the output terminal of the drive circuit 10 is disconnected from the gate terminal (4) of the power MOSFET (M0), and the low drain current during the protection operation is bypassed by the N-channel MOSFET (M5). ) Can be cut off at high speed. When the voltage at the external gate terminal (2) is lowered, a current flows through the drain-body parasitic diode of the P-channel MOSFET (M7) and the main power MOSFET (M0) is cut off.
In the circuit example of a conventional power MOSFET with a built-in overheat cutoff circuit, the gate resistance is increased to about 5 kΩ, and a large current of about 1 to 2 mA is applied to the protection circuit MOSFET in the cutoff state, whereby the voltage of the external gate terminal is increased. The voltage was lowered by about 5 to 10 V to shut off the power MOSFET of the main body. For this reason, the conventional power MOSFET for an overheat cutoff circuit cannot drive a high-frequency pulse, and has a problem that a switching loss is increased because a gate delay time is increased. Further, since the gate current after the overheat cutoff circuit is activated is high, there is a problem that the power consumption of the drive circuit becomes high.
On the other hand, the embodiment of the present invention shown in FIG. 1 has an advantage that high-frequency pulse driving is possible and switching loss is small because the equivalent gate resistance is small during normal driving. Further, since the equivalent gate resistance is increased during the shut-off operation, there is an advantage that the gate current after the overheat shut-off circuit is activated is small and the switching time for the overheat shut-off is shortened.
図2は本発明の第2の実施例の回路図である。本実施例は図1のブロック回路的な実施例を実際の回路で表したものである。本実施例ではパワーMOSFETの温度検出回路として抵抗R4とダイオード列D1〜D4を使用している。通常の動作時には、ゲート電圧が外部ゲート端子2に印加された時、M1はオン状態になる。また、非対称型フリップフロップ構成のラッチ回路の出力は抵抗R1を抵抗R2より十分高く設定することにより低電圧状態になる。このため、M7はオン状態、M5はオフ状態となり、外部ゲート端子2に電圧が印加される時の等価的なゲート抵抗は低くなる。一方、負荷短絡事故等が発生しパワーMOSFETの温度が上昇するとM1がオフし、ラッチ回路の状態が反転し、M7がオフする。このため、遮断動作時には等価的ゲート抵抗が高くなる。また、M5がオンするためパワーMOSFET(M0)を高速に遮断でき、遮断動作後のゲート電流が小さいという利点がある。 FIG. 2 is a circuit diagram of a second embodiment of the present invention. In this embodiment, the block circuit embodiment of FIG. 1 is represented by an actual circuit. In this embodiment, a resistor R4 and diode arrays D1 to D4 are used as a temperature detection circuit for the power MOSFET. During normal operation, when a gate voltage is applied to the external gate terminal 2, M1 is turned on. Further, the output of the latch circuit having the asymmetric flip-flop configuration becomes a low voltage state by setting the resistor R1 sufficiently higher than the resistor R2. For this reason, M7 is turned on, M5 is turned off, and the equivalent gate resistance when a voltage is applied to the external gate terminal 2 is lowered. On the other hand, when a load short circuit accident or the like occurs and the temperature of the power MOSFET rises, M1 is turned off, the state of the latch circuit is inverted, and M7 is turned off. For this reason, equivalent gate resistance becomes high at the time of interruption | blocking operation | movement. Further, since M5 is turned on, there is an advantage that the power MOSFET (M0) can be shut off at high speed and the gate current after the shutoff operation is small.
図3は本発明の第3の実施例の半導体装置の断面図である。本実施例は図2の回路で、1を外部ドレイン、2を外部ゲート、3を外部ソースとして、1チップ化するための半導体装置の断面構造である。1015は本体パワーMOSFET(図2のM0)のドレイン電極、1000はN型エピタキシャル領域で本体パワーMOSFETのドレイン領域、1007aはゲート用多結晶シリコン層、1012aはN型拡散層で本体パワーMOSFETのソース拡散層、1008はボディ領域となるP型拡散層、1011aはボディ領域のコンタクト抵抗低減のためのP型拡散層である。また、図の右側にはM5等に用いる保護回路用のNチャネルMOSFETを示す。1012bはドレインまたはソース用のN型拡散層、1005はP型ウエル拡散層、1011bはボディ領域のコンタクト抵抗低減のためのP型拡散層、1007bはゲート用多結晶シリコン層である。また、中央にはM7に用いる保護回路用PチャネルMOSFETを示してある。1007dと1007eは1007aと同一工程で形成される多結晶シリコン層で、1007eは低濃度のN型不純物をドープしたボディ領域、1007dは1011aの高濃度P型ドープと同一工程により高濃度P型領域にしてある。また、1010は多結晶シリコンゲート層である。
本実施例の特長は、M7に用いるPチャネルMOSFETを絶縁層1006により本体パワーMOSFETと分離された領域に形成してある点である。このため、本実施例では、従来のパワーMOSFET製造プロセスとほぼ同様な低コストプロセスで図2に示した高性能化した過熱遮断回路パワーMOSFETを実現できるという利点がある。
FIG. 3 is a sectional view of a semiconductor device according to a third embodiment of the present invention. This embodiment is a cross-sectional structure of a semiconductor device for forming a single chip, with 1 being an external drain, 2 being an external gate, and 3 being an external source. 1015 is a drain electrode of the main power MOSFET (M0 in FIG. 2), 1000 is an N type epitaxial region and a drain region of the main power MOSFET, 1007a is a polycrystalline silicon layer for a gate, 1012a is an N type diffusion layer and a source of the main power MOSFET A diffusion layer, 1008 is a P-type diffusion layer serving as a body region, and 1011a is a P-type diffusion layer for reducing contact resistance of the body region. Further, an N-channel MOSFET for a protection circuit used for M5 and the like is shown on the right side of the figure. 1012b is an N-type diffusion layer for drain or source, 1005 is a P-type well diffusion layer, 1011b is a P-type diffusion layer for reducing contact resistance of the body region, and 1007b is a polycrystalline silicon layer for gate. In the center, a protection circuit P-channel MOSFET used for M7 is shown. 1007d and 1007e are polycrystalline silicon layers formed in the same process as 1007a, 1007e is a body region doped with low-concentration N-type impurities, 1007d is a high-concentration P-type region in the same process as 1011a high-concentration P-type doping It is. Reference numeral 1010 denotes a polycrystalline silicon gate layer.
The feature of this embodiment is that the P-channel MOSFET used for M7 is formed in a region separated from the main body power MOSFET by the insulating layer 1006. For this reason, the present embodiment has an advantage that the high-performance overheat cutoff circuit power MOSFET shown in FIG. 2 can be realized by a low-cost process substantially similar to the conventional power MOSFET manufacturing process.
図4は本発明の第4の実施例の半導体装置である。本実施例も図2の回路で、1を外部ドレイン、2を外部ゲート、3を外部ソースとして、1チップ化するための半導体装置の断面構造である。本実施例では誘電体分離構造で本発明の回路を実現している。本構造では最初にN型基板1000の下側に溝を形成、高濃度N型埋込層1001の形成、絶縁酸化膜1002の形成を行った後、パワーMOSFET部直下の酸化膜1002を除去し、シリコン層(1003と1004)の形成を行う。このとき、絶縁酸化膜1002の下には多結晶シリコン層1003、絶縁酸化膜1002を除去した領域には単結晶シリコン層1004が形成される。この後、N型シリコン層1000の上側を削り平坦化し、通常のパワーMOSFETと同様の工程を経ることにより本構造が得られる。本実施例の場合にはM7に用いるPチャネルMOSFETは絶縁層1002により本体パワーMOSFETと分離された領域に形成してある。このため、図3の実施例の場合と同様にPチャネルMOSFETのソースまたはドレインと本体パワーMOSFETのドレインを分離できる。本実施例は図3に比べ製造方法が複雑になるが、PチャネルMOSFETを単結晶シリコン層内に形成できるため、図3の場合に比べPチャネルMOSFETのオン抵抗を下げやすいという利点がある。また、M5等の保護回路用NチャネルMOSFETも本体パワーMOSFETと絶縁層1002により分離して形成できるため、寄生バイポーラトランジスタの動作等による誤動作を防止できるという利点がある。 FIG. 4 shows a semiconductor device according to a fourth embodiment of the present invention. This embodiment also has a cross-sectional structure of a semiconductor device for forming a single chip in the circuit of FIG. 2, wherein 1 is an external drain, 2 is an external gate, and 3 is an external source. In this embodiment, the circuit of the present invention is realized by a dielectric separation structure. In this structure, first, after forming a trench under the N-type substrate 1000, forming a high-concentration N-type buried layer 1001, and forming an insulating oxide film 1002, the oxide film 1002 immediately below the power MOSFET portion is removed. The silicon layers (1003 and 1004) are formed. At this time, a polycrystalline silicon layer 1003 is formed under the insulating oxide film 1002, and a single crystal silicon layer 1004 is formed in a region where the insulating oxide film 1002 is removed. Thereafter, the upper side of the N-type silicon layer 1000 is shaved and flattened, and this structure is obtained through the same process as that of a normal power MOSFET. In this embodiment, the P-channel MOSFET used for M7 is formed in a region separated from the main power MOSFET by the insulating layer 1002. Therefore, the source or drain of the P-channel MOSFET and the drain of the main power MOSFET can be separated as in the embodiment of FIG. Although the manufacturing method of this embodiment is more complicated than that of FIG. 3, since the P-channel MOSFET can be formed in the single crystal silicon layer, there is an advantage that the on-resistance of the P-channel MOSFET can be easily lowered compared to the case of FIG. Further, since the N-channel MOSFET for the protection circuit such as M5 can be formed separately from the main body power MOSFET and the insulating layer 1002, there is an advantage that malfunction due to the operation of the parasitic bipolar transistor can be prevented.
図5は本発明の第5の実施例の半導体装置である。本実施例では本体パワーMOSFET(M0)と、保護回路用のNチャネルMOSFET(M5)と前記温度検出回路または電流検出回路(12)を第1の半導体チップ(104)に内蔵し、保護回路用のPチャネルMOSFET(M7)を第2の半導体チップ(106)に形成し破線で示す同一の樹脂封止パッケージ中に実装したことを特徴とするものである。第1の半導体チップ(104)では裏面が本体パワーMOSFETのドレインであるため、第2の半導体チップ(106)は絶縁板(105)の上に形成し、PチャネルMOSFET(M7)と本体パワーMOSFET(M0)を分離している。110は本体パワーMOSFETのゲート端子用パッド(図2の4に対応)、111は本体パワーMOSFETのソース端子用パッド、112はM7のゲート端子を制御するための端子用パッド、113は第1の半導体チップ上の外部ゲート端子用パッドで制御回路部の電源電圧を供給する。また、107はM7のドレイン端子用パッド、108はM7のゲート端子用パッド、109はM7のソース端子用パッドである。本実施例では実装方式を改良することにより、PチャネルMOSFETであるM7を本体パワーMOSFETと同一パッケージに実装し小型化した。本実施例によっても図3や図4で示した1チップで実現する保護回路内蔵パワーMOSFETと同様の効果が得られる。 FIG. 5 shows a semiconductor device according to a fifth embodiment of the present invention. In this embodiment, the main body power MOSFET (M0), the N-channel MOSFET (M5) for the protection circuit, and the temperature detection circuit or current detection circuit (12) are built in the first semiconductor chip (104), and are used for the protection circuit. The P-channel MOSFET (M7) is formed on the second semiconductor chip (106) and mounted in the same resin-encapsulated package indicated by a broken line. Since the back surface of the first semiconductor chip (104) is the drain of the main body power MOSFET, the second semiconductor chip (106) is formed on the insulating plate (105), and the P channel MOSFET (M7) and the main body power MOSFET are formed. (M0) is separated. 110 is a gate terminal pad of the main power MOSFET (corresponding to 4 in FIG. 2), 111 is a source terminal pad of the main power MOSFET, 112 is a terminal pad for controlling the gate terminal of M7, and 113 is a first pad. The power supply voltage of the control circuit section is supplied by an external gate terminal pad on the semiconductor chip. Reference numeral 107 denotes an M7 drain terminal pad, 108 denotes an M7 gate terminal pad, and 109 denotes an M7 source terminal pad. In this embodiment, by improving the mounting system, the M7, which is a P-channel MOSFET, is mounted in the same package as the main body power MOSFET to reduce the size. Also in this embodiment, the same effect as that of the power MOSFET with a built-in protection circuit realized by one chip shown in FIGS. 3 and 4 can be obtained.
図6は本発明の第6の実施例の回路図である。本実施例では図2の抵抗R1、R2、R3、R4をPチャネルMOSFET M9、M10、M8、M6に置き換えた場合の実施例である。本実施例では図2の場合に比べ保護回路の占有面積を小さくすることができ、また、保護回路部のスイッチング速度が高速化できるという効果がある。ここで、PチャネルMOSFET M9、M10、M8、M6は図3や図4の半導体素子構造を用いることによりM7と同様に本体素子と同一チップに共存可能である。また、PチャネルMOSFET M9、M10、M8、M11は図5の第2の半導体チップ106に共存させることにより、本体パワーMOSFETと同一パッケージに形成することも可能である。 FIG. 6 is a circuit diagram of a sixth embodiment of the present invention. In this embodiment, the resistors R1, R2, R3, and R4 in FIG. 2 are replaced with P-channel MOSFETs M9, M10, M8, and M6. In this embodiment, the area occupied by the protection circuit can be reduced as compared with the case of FIG. 2, and the switching speed of the protection circuit section can be increased. Here, the P-channel MOSFETs M9, M10, M8, and M6 can coexist on the same chip as the main body element similarly to M7 by using the semiconductor element structure of FIGS. Further, the P-channel MOSFETs M9, M10, M8, and M11 can be formed in the same package as the main body power MOSFET by coexisting with the second semiconductor chip 106 of FIG.
図7は本発明の第7の実施例の回路図である。本実施例では図2のPチャネルMOSFETの代わりにデプレッション型NチャネルMOSFET(M12)を用いた場合の実施例である。ここで、デプレッション型NチャネルMOSFET(M12)はスイッチング素子または可変ゲート抵抗として振る舞う。すなわち、パワーMOSFET(M0)が正常動作している場合にはM12のゲート電圧は高電位のためM12はオン状態(低インピーダンス状態)、第3のスイッチング素子であるNチャネルMOSFET(M5)はオフ状態である。このため、外部ゲート端子2の電圧はそのまま等価的に低いゲート抵抗を介して、パワーMOSFET(M0)のゲート端子(4)に印加される。このため、高周波パルス駆動回路にも低損失で使用可能である。一方、パワーMOSFETが過熱状態になった場合にはM12のゲート電位が下がるためM12はほぼオフ状態または高インピーダンス状態になり、また、NチャネルMOSFET(M5)はオンする。このため、NチャネルMOSFET(M5)の電流駆動能力が低くても本体パワーMOSFET(M0)を高速に遮断できるという効果がある(図2の実施例と同様の効果がある)。本実施例のデプレッション型NチャネルMOSFET(M12)は図3の制御用NチャネルMOSFETと同様にP型ウエル構造の中に形成し、ゲート直下のP型ウエルの表面だけをイオン打ち込みによりN型化することにより実現できる。本実施例では、図3や図4に比べ半導体装置の製造方法が簡単であるという利点がある。なお、M12はエンハンス型素子を使用することも可能である。また、多結晶シリコンダイオードD6を追加した場合には外部ゲート端子2によるパワーMOSFET(M0)の遮断を高速に行なえるという効果がある。 FIG. 7 is a circuit diagram of a seventh embodiment of the present invention. In this embodiment, a depletion type N channel MOSFET (M12) is used instead of the P channel MOSFET of FIG. Here, the depletion type N-channel MOSFET (M12) behaves as a switching element or a variable gate resistance. That is, when the power MOSFET (M0) is operating normally, the gate voltage of M12 is high, so that M12 is on (low impedance state), and the third switching element N-channel MOSFET (M5) is off. State. For this reason, the voltage of the external gate terminal 2 is applied as it is to the gate terminal (4) of the power MOSFET (M0) through an equivalently low gate resistance. For this reason, it can be used in a high-frequency pulse drive circuit with low loss. On the other hand, when the power MOSFET is overheated, the gate potential of M12 is lowered, so that M12 is almost turned off or in a high impedance state, and the N-channel MOSFET (M5) is turned on. For this reason, even if the current drive capability of the N-channel MOSFET (M5) is low, the main body power MOSFET (M0) can be shut off at high speed (the same effect as in the embodiment of FIG. 2). The depletion type N channel MOSFET (M12) of this embodiment is formed in a P type well structure like the control N channel MOSFET of FIG. 3, and only the surface of the P type well just under the gate is made N type by ion implantation. This can be achieved. In this embodiment, there is an advantage that the manufacturing method of the semiconductor device is simpler than those in FIGS. Note that M12 can use an enhanced element. Further, when the polycrystalline silicon diode D6 is added, there is an effect that the power MOSFET (M0) can be shut off by the external gate terminal 2 at high speed.
図8は本発明の第8の実施例の回路図である。本実施例では図7の抵抗R1、R2、R3、R4をデプレッション型NチャネルMOSFET M14、M15、M13、R11に置き換えた場合の実施例である。本実施例の場合には図7の場合に比べ、保護回路の占有面積を小さくすることができ、また、保護回路部のスイッチング速度が高速化できるという利点がある。 FIG. 8 is a circuit diagram of an eighth embodiment of the present invention. In this embodiment, the resistors R1, R2, R3 and R4 in FIG. 7 are replaced with depletion type N-channel MOSFETs M14, M15, M13 and R11. Compared with the case of FIG. 7, this embodiment has the advantage that the area occupied by the protection circuit can be reduced and the switching speed of the protection circuit section can be increased.
図9は本発明の第9の実施例の回路図である。これまでの実施例では、過熱遮断回路内蔵パワーMOSFETを例にとり説明してきたが、本実施例では過電流遮断回路内蔵パワーMOSFETを用いた場合を示してある。本実施例では大きなサイズ(大きなチャネル幅)の本体パワーMOSFET(M0)と同一チップに小さなサイズ(小さなチャネル幅)のセンス用MOSFET(M15)を所謂カレントミラー接続して内蔵し、本体パワーMOSFET(MO)に過電流が流れた場合にセンス用MOSFET(M15)にもセンス電流が流れる電流検出回路を実現している。通常、外部ゲート端子に電圧が印加されるとセンス用MOSFET(M15)のソース電位(5)が低電位のためM5はオフ、M17はオフ、M16はオン、M7はオン状態である。このため、外部ゲート端子(2)の印加電圧はそのまま等価的に低いゲート抵抗を介して、パワーMOSFET(M0)のゲート端子(4)に印加される。一方、パワーMOSFETが過電流状態になった場合にはM15のソース電圧が増加するため、上記と逆にPチャネルMOSFET(M7)がオフ、NチャネルMOSFET(M5)がオンする。このため、低電流駆動能力を有するNチャネルMOSFET(M5)を用いてもパワーMOSFET(M0)を高速に遮断できる。本実施例では抵抗R5〜R8の値、M7のオン抵抗、M5、M16、M17の電流駆動能力の設計値により、過電流時に本体パワーMOSFETが遮断する過電流遮断回路内蔵パワーMOSFETにも、電流を制御するだけの過電流制限回路内蔵パワーMOSFETにもなる。本実施例の過電流保護回路を有する半導体装置も図3、図4、図5の実施例で述べた過熱保護回路内蔵パワーMOSFETと同じ構造にて実現できる。 FIG. 9 is a circuit diagram of the ninth embodiment of the present invention. In the embodiments described so far, the power MOSFET with built-in overheat cutoff circuit has been described as an example. However, in this embodiment, the case where the power MOSFET with built-in overcurrent cutoff circuit is used is shown. In this embodiment, a large size (large channel width) main body power MOSFET (M0) and a small size (small channel width) sense MOSFET (M15) are incorporated in a so-called current mirror in the same chip, and the main body power MOSFET ( A current detection circuit is realized in which a sense current flows in the sense MOSFET (M15) when an overcurrent flows in (MO). Normally, when a voltage is applied to the external gate terminal, the source potential (5) of the sense MOSFET (M15) is low, so M5 is off, M17 is off, M16 is on, and M7 is on. Therefore, the voltage applied to the external gate terminal (2) is applied as it is to the gate terminal (4) of the power MOSFET (M0) through an equivalently low gate resistance. On the other hand, when the power MOSFET enters an overcurrent state, the source voltage of M15 increases, so that the P-channel MOSFET (M7) is turned off and the N-channel MOSFET (M5) is turned on contrary to the above. For this reason, the power MOSFET (M0) can be cut off at high speed even when an N-channel MOSFET (M5) having a low current driving capability is used. In the present embodiment, the power MOSFET with a built-in overcurrent cutoff circuit that shuts off the main body power MOSFET in the event of an overcurrent also depends on the values of the resistors R5 to R8, the on-resistance of M7, and the design values of the current drive capability of M5, M16, and M17. It also becomes a power MOSFET with a built-in overcurrent limiting circuit that only controls the current. The semiconductor device having the overcurrent protection circuit of this embodiment can also be realized with the same structure as the power MOSFET with built-in overheat protection circuit described in the embodiments of FIGS.
以上、本発明の実施例を詳細に説明したが、本発明は上記の実施例に限定されるものではなく、その技術思想の範囲内で種々の変形が可能である。
例えば、以上の実施例では本体素子がパワーMOSFETの場合に関して述べたが、本発明の回路技術は本体素子として、バイポーラトランジスタや絶縁ゲート型バイポーラトランジスタ(IGBT)を用いた場合にも適用可能であることは言うまでもない。
As mentioned above, although the Example of this invention was described in detail, this invention is not limited to said Example, A various deformation | transformation is possible within the range of the technical thought.
For example, in the above embodiments, the case where the main body element is a power MOSFET has been described. However, the circuit technology of the present invention can also be applied to a case where a bipolar transistor or an insulated gate bipolar transistor (IGBT) is used as the main body element. Needless to say.
1、101…外部ドレイン端子、2、100…外部ゲート端子、3、102…外部ソース端子、4…本体パワーMOSFETの内部ゲート端子、5…センスMOSFETのソース端子、10…駆動回路、11…制御回路、12…パワーMOSFETの温度検出回路または電流検出回路、
104…M0と温度検出回路または電流検出回路を内蔵する第1の半導体チップ、105…絶縁板、106…M7を内蔵する第2の半導体チップ、107…第2の半導体チップ上の本体パワーMOSFETの内部ゲート用パッド、108…第2の半導体チップ上の本体パワーMOSFETの内部ゲート用パッド、109…第2の半導体チップ上の外部ゲート端子用パッド、110…第1の半導体チップ上の本体パワーMOSFETの内部ゲート用パッド111…第1の半導体チップ上の外部ソース用パッド、112…M7またはM12のゲート制御用端子パッド、113…第1の半導体チップ上の外部ゲート用パッド、104…M0と温度検出回路または電流検出回路を内蔵する第1の半導体チップ、
1000…N型基板またはN型エピタキシャル層、1001…高濃度N型埋込層、1002、1006、1009、1013…絶縁層、1003…高濃度N型多結晶シリコン層、1004…高濃度N型単結晶シリコン層、1005…P型ウエル拡散層、1007a、1007b、1007c…多結晶シリコン層、1008…P型チャネル拡散層、1010…多結晶シリコン層(制御回路用P型MOSFET部ゲート用)、1011a、1011b…高濃度P型拡散層、1012a、1012b…高濃度N型拡散層、1014、1015…電極層、
R1〜R8…抵抗、D1〜D6…ダイオ−ド、M0…パワーMOSFET、M1〜M5、M16、M17…制御用NチャネルMOSFET、M6、M7、M8〜M10…制御用PチャネルMOSFET、M11〜M15…制御用デプレッション型NチャネルMOSFET。
DESCRIPTION OF SYMBOLS 1,101 ... External drain terminal 2,100 ... External gate terminal 3,102 ... External source terminal, 4 ... Internal gate terminal of main body power MOSFET, 5 ... Source terminal of sense MOSFET, 10 ... Drive circuit, 11 ... Control Circuit, 12 ... power MOSFET temperature detection circuit or current detection circuit,
104... M0 and a first semiconductor chip incorporating a temperature detection circuit or current detection circuit, 105... An insulating plate, 106... A second semiconductor chip incorporating M7, and 107 ... a main power MOSFET on the second semiconductor chip. Internal gate pad 108... Internal power pad of main power MOSFET on second semiconductor chip 109. External gate terminal pad on second semiconductor chip 110. Main power MOSFET on first semiconductor chip , Internal gate pad 111... External source pad on the first semiconductor chip, 112... M7 or M12 gate control terminal pad, 113... External gate pad on the first semiconductor chip, 104. A first semiconductor chip incorporating a detection circuit or a current detection circuit;
DESCRIPTION OF SYMBOLS 1000 ... N type substrate or N type epitaxial layer, 1001 ... High concentration N type buried layer, 1002, 1006, 1009, 1013 ... Insulating layer, 1003 ... High concentration N type polycrystalline silicon layer, 1004 ... High concentration N type single Crystal silicon layer, 1005... P-type well diffusion layer, 1007a, 1007b, 1007c .. Polycrystalline silicon layer, 1008... P-type channel diffusion layer, 1010... Polycrystalline silicon layer (for P-type MOSFET for control circuit gate), 1011a 1011b ... High-concentration P-type diffusion layer, 1012a, 1012b ... High-concentration N-type diffusion layer, 1014, 1015 ... Electrode layer,
R1 to R8, resistors, D1 to D6, diodes, M0, power MOSFETs, M1 to M5, M16, M17, control N-channel MOSFETs, M6, M7, M8 to M10, control P-channel MOSFETs, M11 to M15 ... Depletion type N-channel MOSFET for control.
Claims (5)
第1の半導体チップは、パワーMOSFETと、第1のMOSFETと、上記パワーMOSFETの一定以上の温度を検出する検出回路と、上記検出結果を保持し出力するラッチ回路を含み、上記第1のMOSFETのソース、及びドレインが上記パワーMOSFETのソース、及びゲートにそれぞれ接続されており、
第2の半導体チップは、第2のMOSFETを含み、
上記半導体装置は上記パッケージ外に導出された第1端子、第2端子、第3端子とを具備し、
上記第1端子は上記第1の半導体チップの裏面に形成された上記パワーMOSFETのドレイン電極と接続され、
上記第2端子は上記第2の半導体チップの表面に形成され上記第2のMOSFETのソースまたはドレイン電極と接続された第1パッドと接続され、
上記第3端子は上記第1の半導体チップの表面に形成され上記パワーMOSFETのソース電極と接続される第2パッドと接続され、
上記第2MOSFETの上記第1パッドと接続されたソースまたはドレイン電極と異なるソースまたはドレイン電極は上記第2の半導体チップの表面に形成された第3パッドと接続され、
上記第1の半導体チップの表面に形成され、上記パワーMOSFETのゲート電極と接続される第4パッドと上記第3パッドが接続され、
上記第1のMOSFETと上記第2のMOSFETのゲート電極に印加される電圧は上記ラッチ回路の出力により制御され、その制御によって、上記パワーMOSFETが上記一定の温度より高い場合には、上記第1のMOSFETをオンにし、上記第2のMOSFETをオフにすることを特徴とする半導体装置。 In a semiconductor device in which a first semiconductor chip and a second semiconductor chip are mounted in the same package by resin sealing,
The first semiconductor chip includes a power MOSFET, a first MOSFET , a detection circuit that detects a temperature above a certain level of the power MOSFET, and a latch circuit that holds and outputs the detection result. Are connected to the source and gate of the power MOSFET, respectively.
The second semiconductor chip includes a second MOSFET,
The semiconductor device includes a first terminal, a second terminal, and a third terminal led out of the package,
The first terminal is connected to a drain electrode of the power MOSFET formed on the back surface of the first semiconductor chip ,
The second terminal is connected to a first pad formed on the surface of the second semiconductor chip and connected to the source or drain electrode of the second MOSFET ,
The third terminal is connected to a second pad connected to the source electrode of the upper Symbol power MOSFET is formed on the surface of the first semiconductor chip,
A source or drain electrode different from the source or drain electrode connected to the first pad of the second MOSFET is connected to a third pad formed on the surface of the second semiconductor chip ,
A fourth pad formed on the surface of the first semiconductor chip and connected to the gate electrode of the power MOSFET is connected to the third pad,
The voltage applied to the gate electrodes of the first MOSFET and the second MOSFET is controlled by the output of the latch circuit, and when the power MOSFET is higher than the certain temperature by the control, the first MOSFET A semiconductor device, wherein the MOSFET is turned on and the second MOSFET is turned off .
上記ラッチ回路は、上記検出回路の上記信号が第2状態となった場合にその出力を変化させ保持することを特徴とする請求項1記載の半導体装置。 The detection circuit outputs a signal that is in a first state when the temperature is lower than the constant temperature, and in a second state when the temperature is higher than the constant temperature,
2. The semiconductor device according to claim 1, wherein the latch circuit changes and holds the output when the signal of the detection circuit is in a second state .
上記第1の半導体チップは上記導電板上に配置され、
上記第2の半導体チップは上記絶縁板上に配置されていることを特徴とする請求項1記載の半導体装置。 A conductive plate connected to the first terminal; and an insulating plate formed on the conductive plate;
The first semiconductor chip is disposed on the conductive plate;
The semiconductor device according to claim 1, wherein the second semiconductor chip is disposed on the insulating plate .
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JP6503202B2 (en) * | 2015-03-12 | 2019-04-17 | エイブリック株式会社 | Semiconductor device |
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JP2017163741A (en) | 2016-03-10 | 2017-09-14 | エスアイアイ・セミコンダクタ株式会社 | Switching regulator |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61194755A (en) * | 1985-02-25 | 1986-08-29 | Hitachi Ltd | Semiconductor device |
JPH0666472B2 (en) * | 1987-06-22 | 1994-08-24 | 日産自動車株式会社 | MOSFET with overcurrent protection function |
JPH01109755A (en) * | 1987-10-22 | 1989-04-26 | Nec Corp | Lead frame |
JPH02285932A (en) * | 1989-04-25 | 1990-11-26 | Nec Corp | Overcurrent protective circuit |
US5023692A (en) * | 1989-12-07 | 1991-06-11 | Harris Semiconductor Patents, Inc. | Power MOSFET transistor circuit |
-
1993
- 1993-02-22 JP JP5031579A patent/JP3018816B2/en not_active Expired - Lifetime
-
1999
- 1999-06-22 JP JP17505599A patent/JP3446665B2/en not_active Expired - Lifetime
-
2003
- 2003-03-31 JP JP2003093135A patent/JP4007450B2/en not_active Expired - Lifetime
-
2007
- 2007-02-05 JP JP2007025328A patent/JP4437823B2/en not_active Expired - Lifetime
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2009
- 2009-10-28 JP JP2009247256A patent/JP4605613B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JP3446665B2 (en) | 2003-09-16 |
JP3018816B2 (en) | 2000-03-13 |
JPH06244414A (en) | 1994-09-02 |
JP2000101080A (en) | 2000-04-07 |
JP2010022069A (en) | 2010-01-28 |
JP2003309264A (en) | 2003-10-31 |
JP2007215181A (en) | 2007-08-23 |
JP4605613B2 (en) | 2011-01-05 |
JP4007450B2 (en) | 2007-11-14 |
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