JP4568039B2 - 半導体装置およびそれを用いた半導体モジュール - Google Patents
半導体装置およびそれを用いた半導体モジュール Download PDFInfo
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- JP4568039B2 JP4568039B2 JP2004194673A JP2004194673A JP4568039B2 JP 4568039 B2 JP4568039 B2 JP 4568039B2 JP 2004194673 A JP2004194673 A JP 2004194673A JP 2004194673 A JP2004194673 A JP 2004194673A JP 4568039 B2 JP4568039 B2 JP 4568039B2
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- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
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- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
本実施形態は、貫通電極を備えた半導体装置に関する。半導体基板に一または二以上のストライプ状の貫通電極が近接配置され、そのストライプ状の貫通電極の外側を、所定の幅の筒状貫通電極が囲んでいる。
図3は、本実施形態に係る半導体装置の構成を模式的に示す断面図である。また、図4は、図3のB−B’断面図である。図3および図4に示したように、半導体装置110は、シリコン基板101およびシリコン基板101中を貫通する構造体130を備える。構造体130は、貫通電極131、シリコン119、第一の絶縁膜109および第二の絶縁膜133を備える。
以上の実施形態に記載の半導体装置は、マルチチップモジュール等に好適に用いることができる。マルチチップモジュールは、たとえば以上の実施形態に係る半導体装置と他の半導体装置とが積層されており、シリコン基板101を貫通する貫通電極と他の半導体装置の導電部材とが電気的に接続された構成とすることができる。
101 シリコン基板
103 筒状貫通電極
105 シリコン
105 絶縁膜
107 ストライプ状貫通電極
109 第一の絶縁膜
110 半導体装置
111 第二の絶縁膜
113 第三の絶縁膜
115 筒状貫通電極
117 ストライプ状貫通電極
119 シリコン
120 構造体
121 開口部
123 開口部
125 絶縁膜
127 導電膜
129 絶縁膜
130 構造体
131 貫通電極
133 第二の絶縁膜
135 バンプ
137 プリント配線基板
Claims (4)
- 半導体基板と、
前記半導体基板を貫通する筒状の第一導電体と、
前記半導体基板を貫通し、前記第一導電体の内側に前記第一導電体から離間して設けられた複数のストライプ状の第二導電体と、
前記半導体基板と前記第一導電体との間に設けられ、前記第一導電体の外側面を被覆する絶縁膜と、
を備えることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、複数の前記第二導電体は、互いに平行に設けられていることを特徴とする半導体装置。
- 半導体基板と、
前記半導体基板を貫通する筒状の第一導電体と、
前記半導体基板を貫通し、前記第一導電体の内面の一の領域と他の領域とを接続する複数のストライプ状の第二導電体と、
を備えることを特徴とする半導体装置。 - 請求項1乃至3いずれかに記載の半導体装置と、他の半導体装置とが積層されてなる半導体モジュールであって、
前記第一導電体または前記第二導電体と、前記他の半導体装置とが、電気的に接続されていることを特徴とする半導体モジュール。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004194673A JP4568039B2 (ja) | 2004-06-30 | 2004-06-30 | 半導体装置およびそれを用いた半導体モジュール |
US11/167,162 US7768133B2 (en) | 2004-06-30 | 2005-06-28 | Semiconductor device and semiconductor module employing thereof |
US12/820,478 US7898073B2 (en) | 2004-06-30 | 2010-06-22 | Semiconductor device and semiconductor module employing thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004194673A JP4568039B2 (ja) | 2004-06-30 | 2004-06-30 | 半導体装置およびそれを用いた半導体モジュール |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006019431A JP2006019431A (ja) | 2006-01-19 |
JP4568039B2 true JP4568039B2 (ja) | 2010-10-27 |
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Application Number | Title | Priority Date | Filing Date |
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JP2004194673A Expired - Fee Related JP4568039B2 (ja) | 2004-06-30 | 2004-06-30 | 半導体装置およびそれを用いた半導体モジュール |
Country Status (2)
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US (2) | US7768133B2 (ja) |
JP (1) | JP4568039B2 (ja) |
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JP4577687B2 (ja) * | 2005-03-17 | 2010-11-10 | エルピーダメモリ株式会社 | 半導体装置 |
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JP2010074106A (ja) * | 2008-09-22 | 2010-04-02 | Nec Electronics Corp | 半導体チップ、半導体ウェーハおよびそのダイシング方法 |
JP2010219425A (ja) * | 2009-03-18 | 2010-09-30 | Toshiba Corp | 半導体装置 |
JP5537197B2 (ja) | 2010-03-12 | 2014-07-02 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
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US8505628B2 (en) | 2010-06-30 | 2013-08-13 | Schlumberger Technology Corporation | High solids content slurries, systems and methods |
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US7898073B2 (en) | 2011-03-01 |
JP2006019431A (ja) | 2006-01-19 |
US7768133B2 (en) | 2010-08-03 |
US20100258918A1 (en) | 2010-10-14 |
US20060006539A1 (en) | 2006-01-12 |
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