JP4540223B2 - Electronic component mounting board - Google Patents

Electronic component mounting board Download PDF

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Publication number
JP4540223B2
JP4540223B2 JP2000396301A JP2000396301A JP4540223B2 JP 4540223 B2 JP4540223 B2 JP 4540223B2 JP 2000396301 A JP2000396301 A JP 2000396301A JP 2000396301 A JP2000396301 A JP 2000396301A JP 4540223 B2 JP4540223 B2 JP 4540223B2
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Prior art keywords
electronic component
component mounting
insulating substrate
resistor
wiring layer
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Expired - Fee Related
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JP2000396301A
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Japanese (ja)
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JP2002198630A (en
Inventor
慎也 寺尾
辰郎 西村
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Kyocera Corp
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Kyocera Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体素子やコンデンサ等の複数個の電子部品および抵抗体が搭載される電子部品搭載基板に関するものである。
【０００２】
【従来技術】
従来より、半導体素子や複数の各種電子部品を絶縁基板の両面に搭載した電子部品搭載基板が知られており、その一般的な構造として、図３に示すように、半導体素子やコンデンサ等の各種電子部品から発生する熱を外部に効率良く放熱するために、絶縁基板の一方の表面に半導体素子やコンデンサ等の電子部品を複数個搭載し、これら表面に実装した電子部品に隣接して電気特性確認用のテストパッドを数個形成するとともに、前記絶縁基板の他方の表面（裏面）に前記表面実装部品に供給する電圧等を制御するための抵抗体を所定の個数形成し、該抵抗体をガラスおよび樹脂からなる保護層にて保護したものが知られている。
【０００３】
そして、該電子部品搭載基板の裏面（抵抗体形成面）にシリコン接着剤等を介してヒートシンクを取着し、各電子部品から発生した熱は、各部品からの自然放熱、部品に接合したヒートシンクからの放熱、および絶縁基板を通し基板端部の筐体取り付け部を介した筐体への熱放散によって外部へ放熱される。
【０００４】
かかる電子部品搭載基板においては、ますます表面に搭載される表面実装部品（電子部品）の点数が増加し、特に、車載用に用いられる電子部品搭載基板ではエンジンルーム内のスペースがほとんど無く、基板のさらなる小型化、低コスト化が望まれていることから、電子部品搭載基板のより一層の高密度化を図る必要がある。
【０００５】
そこで、小型高密度化を目的として、例えば、特開平１０−７０３５１号や特開平１１−２０４９１４号では、絶縁基板表面に各種電子部品を搭載するとともに、該絶縁基板表面にカバーを設け、該カバーの表面にも電子部品を搭載することによって基板を小型化できることが記載されている。
【０００６】
【発明が解決しようとする課題】
しかしながら、特開平１０−７０３５１号や特開平１１−２０４９１４号に記載されたカバーを設ける構造の電子部品搭載基板では、カバー等を別途形成する必要があり、かつ該カバー表面にも電子部品を実装しなければならないために実装が難しく、コスト増となるとともに、電子部品の作動に伴って発生する発熱を効率よく放熱することができないという問題があった。
【０００７】
かかる理由から、電子部品は基板表面に実装することが望ましいが、従来の電子部品搭載基板の（ａ）電子部品実装面および（ｂ）抵抗体形成面を示す平面図に示すように電子部品の部品点数が多く電子部品実装面（ａ）のデッドスペースがほとんどないとともに、電子部品実装面（ａ）と抵抗体形成面（ｂ）とのデッドスペースの差が大きいものであった。
【０００８】
本発明は上記課題を解決するためになされたものであり、その目的は、単純な構造で、かつ低コストで小型高密度化が可能な電子部品搭載基板を提供することにある。
【０００９】
【課題を解決するための手段】
本発明者等は、上記課題に対して検討した結果、絶縁基板の表面に半導体素子やコンデンサ等の表面実装部品（電子部品）を複数個実装し、前記絶縁基板の裏面に前記電子部品に接続される抵抗体を形成するとともに、前記絶縁基板の前記抵抗体形成面（裏面）に半導体素子の約２倍の実装面積を必要とするテストパッドを形成することによって、絶縁基板の電子部品実装面に必要な実装面積を小さくでき、絶縁基板の面積を小さくすることができる結果、電子部品搭載基板全体を小型化ができることを知見した。
【００１０】
すなわち、本発明の電子部品搭載基板は、搭載される複数の電子部品の全てが絶縁基板の一方の主面に搭載されているとともに、所定のパターンに形成された抵抗体材料からなり、前記電子部品に電気的に接続されて該電子部品に供給される電圧を調整する抵抗体と、前記電子部品の電気特性確認用のテストパッドとが前記絶縁基板の他方の主面のみに配置されていることを特徴とするものである。
【００１１】
ここで、前記テストパッドが、前記絶縁基板の前記他方の主面に形成されたタングステンおよび／またはモリブデンを主成分とする第１の表面配線層と、該第１の表面配線層の表面に形成された第１のメッキ膜とを備えることが望ましく、さらに、前記第１のメッキ膜が、前記第１の表面配線層の表面に形成された厚み５〜１５μｍのＮｉまたはＣｕからなる第２のメッキ膜と、該第２のメッキ膜の表面に形成された厚み０．０３〜０．５μｍのＡｕメッキ膜とからなることが望ましい。
【００１２】
また、前記抵抗体が、前記絶縁基板の前記他方の主面に形成された第２の表面配線層と、該第２の表面配線層の表面に形成されたＮｉまたはＣｕからなる第３のメッキ膜および該第３のメッキ膜の表面に形成されたＣｕを主成分としたメタライズ層を介して接続されていることが望ましい。
【００１３】
さらに、前記絶縁基板の前記他方の主面の前記テストパッド以外の領域が保護層によって被覆されていることが望ましい。
【００１４】
【発明の実施の形態】
本発明の電子部品搭載基板の一例について、その概略断面図を示す図１およびその平面図（（ａ）電子部品搭載面、（ｂ）抵抗体形成面）である図２を基に説明する。
図１によれば、電子部品搭載基板１は、絶縁層２ａ〜２ｅの積層体からなる絶縁基板２の一方の表面に表面配線層３が形成されている。また、半導体素子、コンデンサ、ダイオード、トランジスタ等の複数個の電子部品４ａ、４ｂ（４ａは半導体素子、４ｂはその他の電子部品）は、表面配線層３と半田等の接続端子５を介して電気的に接続され、絶縁基板２表面に実装されている。なお、電子部品４のサイズは様々であるが、例えば、１０ｍｍ×１０ｍｍ以上の大きさの半導体素子４ａ等が搭載され、また、電子部品搭載面に搭載される電子部品４の数は、例えば５個以上、特に１０個以上、さらに３０個以上、さらには５０個以上となる。
【００１５】
また、表面配線層３の表面にはＮｉまたはＣｕメッキ膜６ａおよびＡｕメッキ膜６ｂが被着形成され、表面配線層３の酸化を防止する働きをなす。
【００１６】
また、表面配線層３は、絶縁基板２の内部に形成されるビアホール導体７や内部配線層８と電気的に接続されて配線回路を形成し、絶縁基板２の他方の表面（裏面）の抵抗体１０と接続される表面配線層１１や、電子部品４の電気特性を確認するためのテストパッド１３と接続されている。
【００１７】
なお、本発明によれば、テストパッド１３は必ずしも電子部品４の直下に形成される必要はなく、回路設計の都合に応じて回路を引き回し、絶縁基板２の裏面のデッドスペースに設ければよい。
【００１８】
また、抵抗体１０およびテストパッド１３はそれぞれの電子部品４に対してそれぞれ個別に形成する必要はなく、回路設計に合わせて各階路ブロックごとに形成すればよい。すなわち、抵抗体１０の数は電子部品４の数より少ないことが望ましい。
【００１９】
本発明によれば、図１および図２に示すように、絶縁基板２の両面に形成される電子部品４の実装に必要な面積と、抵抗体１０およびテストパッド１３の実装に必要な面積とのバランスを合わせることができ、絶縁基板２の一方の表面に必要な面積を小さくできることから絶縁基板２自体を小型化できる。
【００２０】
また、絶縁基板２の裏面には抵抗体１０と接続される表面配線層１１やテストパッド１３を形成する表面配線層１５が形成され、さらに表面配線層１５の酸化等を防止する上で、表面配線層１５の表面に少なくとも１層のメッキ膜１６を形成することが望ましい。なお、表面配線層１５はメッキ膜１６を形成する際のメッキ液に対する耐食性の観点で、磁器表面にメタライズペーストを焼き付ける厚膜法にて形成した配線層ではなく、タングステンおよび／またはモリブデンを主成分とする導体層からなることが望ましい。また、テストパッド１３のサイズは、例えば、一辺が０．５〜１．５ｍｍ×０．５〜１．５ｍｍの概略四角形状で、その厚みが５〜３０μｍからなる。
【００２１】
また、メッキ膜１６は、メッキ膜１６表面に接続されるワイヤとのボンディング性、およびメッキ膜１６の残留応力により半田実装時等に生じる剥がれ等の不具合を防止するために、特に、厚み５〜１５μｍ、さらに７〜１３μｍのＮｉまたはＣｕメッキ膜１６ａと、厚み０．０３〜０．５μｍ、さらに０．０５〜０．１５μｍのＡｕメッキ膜１６ｂとを形成した構成からなることが望ましい。なお、Ｃｕメッキ膜１６ａを形成する場合には必ずしもＡｕメッキ膜１６ｂを形成しない場合もある。
【００２２】
一方、絶縁基板１表面に形成された表面配線層１１の表面には抵抗体１０が形成されるが、抵抗体１０との反応性を抑制して所望の抵抗値を得るために、抵抗体１０と表面配線層１１との間にＣｕを主成分としたメタライズ層（以下、Ｃｕメタライズ層と略す。）１８が形成され、また、表面配線層１１とＣｕメタライズ層１８との接着性を高めるために、両者間にＮｉまたはＣｕメッキ膜１６ａが形成されている。
【００２３】
すなわち、抵抗体１０は、絶縁基板１表面に形成された表面配線層１１と、該表面配線層１１表面に形成されるＮｉまたはＣｕメッキ膜１６ａ、および該ＮｉまたはＣｕメッキ膜１６ａ表面に形成されるＣｕメタライズ層１８を介して接続されている。
【００２４】
ここで、抵抗体１０は、酸化錫系、ランタンボライド系、Ｃｕ−ニッケル（Ｎｉ）系の群から選ばれる少なくとも１種の抵抗体材料によって形成され、必要な抵抗値によってその形状が決定されるが、例えば、抵抗体１０のサイズは、例えば、幅０．５〜８ｍｍ×長さ１〜１５ｍｍで、厚みが１０〜３０μｍからなる。
【００２５】
また、Ｃｕメタライズ層１８は、Ｃｕペーストを印刷して焼き付けることによって形成される、いわゆる銅厚膜導体からなることが製造の容易性、良好なメタライズ層の形成性の点で望ましい。さらに、その厚みは１０〜２５μｍであることが望ましい。
【００２６】
また、図１によれば、メッキ膜１６形成時のメッキ液による浸食を防止し、かつ外部との電気絶縁性を確保するために、テストパッド１３形成部以外の抵抗体１０形成面、すなわち絶縁基板２の裏面を保護層２０によって被覆している。
【００２７】
なお、図１によれば、保護層２０は、抵抗体１０表面を被覆し、抵抗体１０の抵抗値の調整のために行うレーザートリミング処理時に抵抗体１０にかかる熱的なダメージや抵抗体１０の飛散を防止するために形成されるオーバーガラス層２０ａと、耐湿性、耐食性および絶縁性を高めるための樹脂層２０ｂにて形成されている。
【００２８】
ここで、オーバーガラス層２０ａを形成するガラスとしては、ＳｉＯ2系ガラス、Ｂ2Ｏ3系ガラス、ＳｉＯ2−Ｂ2Ｏ3系ガラス、ＰｂＯ系ガラス、ＰｂＯ−ＺｎＯ系ガラスおよびＢｉ2Ｏ3系ガラスの群から選ばれる少なくとも１種のガラスが採用でき、また、所望によってＡｌ2Ｏ3、ＳｉＯ2、ＺｎＯ、ＺｒＯ2およびＴｉＯ2等のフィラー成分を含有するものであってもよい。
【００２９】
また、樹脂層２０ｂとしては、紫外線硬化型樹脂も適応可能であるが、メッキ液に対する耐薬品性が高い熱硬化型樹脂が望ましく、中でもエポキシ樹脂、ウレタン樹脂、テフロン樹脂、ポリイミド樹脂等が、さらにはコストの点でエポキシ樹脂が望ましい。
【００３０】
一方、絶縁層２ａ〜２ｅは、アルミナ、窒化アルミニウム、窒化ケイ素、炭化ケイ素等のセラミックスからなることが望ましく、特に、アルミナを主成分とし、焼結助剤として酸化珪素、酸化マグネシウム、酸化カルシウム、酸化マンガン等を添加した組成物からなることが望ましい。また、セラミックス以外にプラスチックも適応可能である。
【００３１】
（モジュール）
また、上述した本発明の電子部品搭載基板は、絶縁基板２の抵抗体１０形成面（裏面）を金属ケース内に収納され、金属ケースのコネクタと電子部品搭載基板の接続端子とを電気的に接続した後、金属ケース内に樹脂を充填することにより電子制御ユニットを形成することができる。
【００３２】
（製造方法）
また、上記電子部品搭載基板を作製するには、例えば、まず、絶縁基板を形成するためのセラミック粉末に焼結助剤成分を添加し、さらに、適当な有機バインダー、有機溶剤、可塑剤、分散剤等を添加混合してスラリーを調整する。そして、このスラリーを従来周知のドクターブレード法やカレンダーロール法等のシート成形法を採用してシート状となし、カットしてセラミックグリーンシートを作製し、しかる後、前記グリーンシートの所定の位置にビアホールを形成する。
【００３３】
また、タングステン、モリブデンなどの高融点金属に、所望によりセラミック粉末やガラス粉末を添加し、かつ、これに、有機バインダー、有機溶剤、可塑剤等を添加混合して得た導体ペーストを用いて、スクリーン印刷法などによって導体ペーストをビアホール内に充填したり、表面配線層および内部配線層を形成するための回路パターンを形成する。
【００３４】
なお、導体ペースト中には、低抵抗化のためにタングステンおよびモリブデン１００重量部に対して、Ｃｕ、銀、白金、パラジウムの群から選ばれる金属を総量で６０重量部以下、特に５０重量部以下、さらに５〜５０重量部添加することもできる。
【００３５】
その後、ビアホール導体および配線層を形成した複数のグリーンシートを積層圧着した後、例えば１２００〜２０００℃、特に１５００〜１７００℃の還元雰囲気中で焼成することによって配線層およびビアホール導体を具備する絶縁基板を作製する。
【００３６】
次に、得られた絶縁基板の表面配線層に対して、メッキを施す。本発明によれば、電子部品搭載面側の表面配線層およびテストパッドをなす表面配線層にはＮｉまたはＣｕメッキ（一次メッキ）およびＡｕメッキ（二次メッキ）を施し、かつ抵抗体と接続される表面配線層にはＮｉまたはＣｕメッキ（一次メッキ）のみが施される。
【００３７】
そして、Ｃｕペーストを用いてスクリーン印刷法等の印刷法により、ＮｉまたはＣｕメッキ膜のみを形成した抵抗体と接続される表面配線層の表面をＣｕ導体にて被覆した後、例えば、非酸化性雰囲気中、６００〜９００℃で焼き付け処理することによりＣｕメタライズ層を形成する。
【００３８】
その後、Ｃｕメタライズ表面を含む絶縁基板裏面の所定位置に、抵抗体形成用のペーストを用いてスクリーン印刷法等の印刷法により抵抗体パターンを作製し、例えば、６００〜９００℃の非酸化性雰囲気中にて焼き付け処理を施すことにより抵抗体を形成する。
【００３９】
また、抵抗体表面に所定の組成からなるオーバーガラス形成用のガラスペーストを印刷した後、例えば、５００〜６５０℃の非酸化性雰囲気中にて焼き付けてオーバーガラス層を形成した後、抵抗体に対してオーバーガラス層ごとレーザー等の照射を行い、抵抗体に所定の切りこみ溝を形成することによって、抵抗体を最終的に必要な抵抗値にトリミングする。なお、オーバーガラス層は抵抗体形成部の表面のみに形成してもよく、または絶縁基板裏面のテストパッド部を除く全面に形成してもよい。
【００４０】
そして、抵抗体の吸湿、酸化を防止するために、抵抗体の表面または絶縁基板裏面のテストパッド部を除く全面に印刷法により樹脂層を形成する。また、樹脂層が紫外線硬化型樹脂の場合には紫外線照射によって、熱硬化型樹脂の場合には、例えば１００〜２００℃に加熱することによって樹脂を硬化させて樹脂層を形成する。
【００４１】
こうして作製された電子部品搭載基板の電子部品搭載面に半田等の接続端子を介して半導体素子やコンデンサ等の電子部品を実装する。そして、ボードテスター等を用いて電子部品を介して接続した２つのテストパッドにプローブピンを接触させることにより実装した電子部品の電気特性を確認する。本発明によれば、電子部品とテストパッドとは絶縁基板の別面に形成されるが、複数のプローブピンを備えた基板からなる冶具を裏面に接触させることで、検査は何ら支障なく行える。
【００４２】
電子部品の良好な電気特性が確認された電子部品搭載基板は、抵抗体形成面側を接着面として、シリコン等の接着剤を所定位置の塗布したアルミニウムケース内に収納、固定される。また、該アルミニウムケースにはコネクタが形成され、該コネクタと電子部品搭載基板の回路とをＡｌ線等のワイヤ等にて電気的に接続する。
【００４３】
その後、前記アルミニウムケース内に電気絶縁性、放熱性および衝撃吸収性に優れたシリコンゲル等の保護材を注入し、ポリブチレンテレフタレート（ＰＢＴ）等の樹脂性の蓋体で覆うことにより電子制御ユニットを形成することができる。
【００４４】
【発明の効果】
以上詳述した通り、本発明の電子部品搭載基板によれば、該基板の一方の表面に複数個の電子部品を搭載し、他方の表面（裏面）に抵抗体および前記電子部品の電気特性確認用のテストパッドを形成することによって、単純な構造で電子部品の放熱性を低下させることなく、かつ低コストで小型高密度化が可能な電子部品搭載基板となる。
【００４５】
また、前記テストパッドを、前記絶縁基板表面に形成されたタングステンおよび／またはモリブデンを主成分とする表面配線層と、該表面配線層表面に少なくとも１層形成されたメッキ膜とを備えたものにて形成することによって、耐湿性や耐酸化性およびメッキ液に対する耐薬品性に優れたテストパッドとなる。
【図面の簡単な説明】
【図１】本発明の電子部品搭載基板の一例を示す概略断面図である。
【図２】図１の電子部品搭載基板の（ａ）電子部品搭載面、（ｂ）抵抗体形成面を示す平面図である。
【図３】従来の電子部品搭載基板の一例について（ａ）電子部品搭載面、（ｂ）抵抗体形成面を示す平面図である。
【符号の説明】
１ 電子部品搭載基板
２ 絶縁基板
２ａ〜２ｅ 絶縁層
３、１１、１５ 表面配線層
４ 電子部品
５ 接続端子
６、１６ メッキ膜
６ａ、１６ａ Ｎｉメッキ膜
６ｂ、１６ｂ Ａｕメッキ膜
７ ビアホール導体
８ 内部配線層
１０ 抵抗体
１３ テストパッド
２０ 保護層
２０ａ オーバーガラス層
２０ｂ 樹脂層
１８ Ｃｕメタライズ層[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an electronic component mounting board on which a plurality of electronic components such as semiconductor elements and capacitors and resistors are mounted.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, an electronic component mounting board in which a semiconductor element and a plurality of various electronic components are mounted on both sides of an insulating substrate is known, and as a general structure, as shown in FIG. In order to efficiently dissipate heat generated from electronic components to the outside, multiple electronic components such as semiconductor elements and capacitors are mounted on one surface of the insulating substrate, and electrical characteristics are adjacent to the electronic components mounted on these surfaces. A number of test pads for confirmation are formed, and a predetermined number of resistors for controlling the voltage supplied to the surface-mounted component are formed on the other surface (back surface) of the insulating substrate. Those protected by a protective layer made of glass and resin are known.
[0003]
Then, a heat sink is attached to the back surface (resistor forming surface) of the electronic component mounting substrate via a silicon adhesive or the like, and the heat generated from each electronic component is naturally radiated from each component, and the heat sink joined to the component. The heat is radiated to the outside by heat dissipation from the substrate and heat dissipation to the housing through the housing mounting portion at the end of the substrate through the insulating substrate.
[0004]
In such electronic component mounting boards, the number of surface mount components (electronic components) mounted on the surface is increasing, and in particular, there is almost no space in the engine room for electronic component mounting boards used for in-vehicle use. Therefore, it is necessary to further increase the density of the electronic component mounting substrate.
[0005]
Therefore, for the purpose of miniaturization and high density, for example, in JP-A-10-70351 and JP-A-11-204914, various electronic components are mounted on the surface of the insulating substrate, and a cover is provided on the surface of the insulating substrate. It is described that the substrate can be reduced in size by mounting electronic components on the surface of the substrate.
[0006]
[Problems to be solved by the invention]
However, in the electronic component mounting substrate having the structure provided with the cover described in JP-A-10-70351 and JP-A-11-204914, it is necessary to separately form a cover or the like, and the electronic component is mounted on the cover surface. As a result, mounting is difficult and the cost is increased, and heat generated by the operation of the electronic component cannot be efficiently radiated.
[0007]
For this reason, it is desirable to mount the electronic component on the surface of the substrate. However, as shown in the plan view showing the (a) electronic component mounting surface and (b) resistor forming surface of the conventional electronic component mounting substrate, as shown in FIG. The number of parts was large and there was almost no dead space on the electronic component mounting surface (a), and the difference in dead space between the electronic component mounting surface (a) and the resistor forming surface (b) was large.
[0008]
The present invention has been made to solve the above-described problems, and an object of the present invention is to provide an electronic component mounting substrate that has a simple structure and can be reduced in size and increased in density at a low cost.
[0009]
[Means for Solving the Problems]
As a result of studying the above problems, the present inventors have mounted a plurality of surface mount components (electronic components) such as semiconductor elements and capacitors on the surface of the insulating substrate, and connected to the electronic components on the back surface of the insulating substrate. And forming a test pad that requires about twice the mounting area of the semiconductor element on the resistor forming surface (back surface) of the insulating substrate, thereby forming the electronic component mounting surface of the insulating substrate. As a result of reducing the mounting area required for reducing the area of the insulating substrate, it has been found that the entire electronic component mounting board can be reduced in size.
[0010]
That is, the electronic component mounting board of the present invention, together with all of the plurality of electronic components to be mounted is the mounting tower on one main surface of the insulating substrate, a resistor body material formed in a predetermined pattern, the a resistor for adjusting the voltage supplied to the electronic component is electrically connected to the electronic component, is a pre-Symbol test pad for electrical characterization of electronic components disposed only on the other main surface of the insulating substrate It is characterized by that.
[0011]
Here, the test pad, a first surface wiring layer mainly composed of the other tungsten and / or molybdenum formed on a main surface of the insulating substrate, form a surface of said first surface wiring layer it is desirable and a first plating film was made, further, the first plating film is first made of Ni or Cu of the first thickness formed on the surface of the surface wiring layer 5 to 15 [mu] m 2 and the plating film, it is preferably made of a Au-plated film of said second thickness formed on the surface of the plated film 0.03 to 0.5 microns.
[0012]
Furthermore, the resistor is, the second surface wiring layer formed on the other main surface of the insulating substrate, a third plating made of the second surface wiring layer formed on the surface of Ni or Cu film Contact Yobi該third Rukoto mainly made of Cu formed on the surface of the plated film were connected via the metallization layer is desirable.
[0013]
Furthermore, it is desirable that a region other than the test pad on the other main surface of the insulating substrate is covered with a protective layer.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
An example of the electronic component mounting substrate of the present invention will be described with reference to FIG. 1 showing a schematic sectional view thereof and FIG. 2 which is a plan view thereof ((a) electronic component mounting surface, (b) resistor forming surface).
According to FIG. 1, the electronic component mounting substrate 1 has a surface wiring layer 3 formed on one surface of an insulating substrate 2 made of a laminate of insulating layers 2a to 2e. A plurality of electronic components 4a and 4b (4a is a semiconductor device, 4b is another electronic component) such as a semiconductor element, a capacitor, a diode, and a transistor are electrically connected via a surface wiring layer 3 and a connection terminal 5 such as solder. Connected to each other and mounted on the surface of the insulating substrate 2. Although the size of the electronic component 4 is various, for example, a semiconductor element 4a having a size of 10 mm × 10 mm or more is mounted, and the number of the electronic components 4 mounted on the electronic component mounting surface is, for example, 5 Or more, especially 10 or more, further 30 or more, and further 50 or more.
[0015]
Further, a Ni or Cu plating film 6a and an Au plating film 6b are formed on the surface of the surface wiring layer 3 so as to prevent the surface wiring layer 3 from being oxidized.
[0016]
The surface wiring layer 3 is electrically connected to the via-hole conductor 7 and the internal wiring layer 8 formed inside the insulating substrate 2 to form a wiring circuit, and the resistance of the other surface (back surface) of the insulating substrate 2. A surface wiring layer 11 connected to the body 10 and a test pad 13 for confirming electrical characteristics of the electronic component 4 are connected.
[0017]
According to the present invention, the test pad 13 does not necessarily have to be formed directly under the electronic component 4, and the circuit may be routed according to the convenience of circuit design and provided in the dead space on the back surface of the insulating substrate 2. .
[0018]
Further, the resistor 10 and the test pad 13 do not need to be individually formed for each electronic component 4, and may be formed for each block according to the circuit design. That is, it is desirable that the number of resistors 10 is smaller than the number of electronic components 4.
[0019]
According to the present invention, as shown in FIGS. 1 and 2, the area necessary for mounting the electronic component 4 formed on both surfaces of the insulating substrate 2 and the area required for mounting the resistor 10 and the test pad 13 are as follows. Since the area required for one surface of the insulating substrate 2 can be reduced, the insulating substrate 2 itself can be downsized.
[0020]
Further, a surface wiring layer 11 for forming a surface wiring layer 11 connected to the resistor 10 and a test pad 13 is formed on the back surface of the insulating substrate 2, and the surface wiring layer 15 is prevented from being oxidized and the like. It is desirable to form at least one plating film 16 on the surface of the wiring layer 15. The surface wiring layer 15 is not a wiring layer formed by a thick film method in which a metallized paste is baked on the surface of the porcelain, but is mainly composed of tungsten and / or molybdenum from the viewpoint of corrosion resistance to the plating solution when forming the plating film 16. It is desirable that it is made of a conductor layer. The size of the test pad 13 is, for example, a substantially square shape with one side of 0.5 to 1.5 mm × 0.5 to 1.5 mm and a thickness of 5 to 30 μm.
[0021]
In addition, the plating film 16 has a thickness of 5 to 5 in particular in order to prevent problems such as bondability with wires connected to the surface of the plating film 16 and peeling due to residual stress of the plating film 16 during solder mounting. It is desirable to have a structure in which a 15 μm, 7 to 13 μm Ni or Cu plated film 16 a and a 0.03 to 0.5 μm thick, 0.05 to 0.15 μm Au plated film 16 b are formed. Note that when the Cu plating film 16a is formed, the Au plating film 16b is not necessarily formed.
[0022]
On the other hand, the resistor 10 is formed on the surface of the surface wiring layer 11 formed on the surface of the insulating substrate 1. In order to suppress the reactivity with the resistor 10 and obtain a desired resistance value, the resistor 10 In order to enhance adhesion between the surface wiring layer 11 and the Cu metallized layer 18, a metallized layer (hereinafter abbreviated as Cu metallized layer) 18 containing Cu as a main component is formed between the surface wiring layer 11 and the surface metallized layer 11. In addition, a Ni or Cu plating film 16a is formed between them.
[0023]
That is, the resistor 10 is formed on the surface wiring layer 11 formed on the surface of the insulating substrate 1, the Ni or Cu plating film 16a formed on the surface wiring layer 11, and the surface of the Ni or Cu plating film 16a. Are connected via a Cu metallization layer 18.
[0024]
Here, the resistor 10 is formed of at least one resistor material selected from the group consisting of tin oxide, lanthanum boride, and Cu-nickel (Ni), and its shape is determined by a required resistance value. For example, the size of the resistor 10 is, for example, a width of 0.5 to 8 mm × a length of 1 to 15 mm and a thickness of 10 to 30 μm.
[0025]
The Cu metallized layer 18 is preferably made of a so-called copper thick film conductor formed by printing and baking a Cu paste from the viewpoint of ease of manufacture and good metallized layer formability. Further, the thickness is desirably 10 to 25 μm.
[0026]
Further, according to FIG. 1, in order to prevent erosion by the plating solution when forming the plating film 16 and to ensure electrical insulation from the outside, the resistor 10 forming surface other than the test pad 13 forming portion, that is, the insulating surface. The back surface of the substrate 2 is covered with a protective layer 20.
[0027]
According to FIG. 1, the protective layer 20 covers the surface of the resistor 10, and the thermal damage or the resistor 10 is applied to the resistor 10 during the laser trimming process for adjusting the resistance value of the resistor 10. The over glass layer 20a is formed to prevent the scattering of the resin, and the resin layer 20b is used to improve moisture resistance, corrosion resistance, and insulation.
[0028]
Here, as the glass forming the over glass layer 20a, SiO 2 glass, B 2 O 3 glass, SiO 2 —B 2 O 3 glass, PbO glass, PbO—ZnO glass, and Bi 2 O 3 are used. At least one glass selected from the group of system glasses can be used, and it may contain a filler component such as Al 2 O 3 , SiO 2 , ZnO, ZrO 2 and TiO 2 if desired.
[0029]
Further, as the resin layer 20b, an ultraviolet curable resin can be applied, but a thermosetting resin having high chemical resistance to the plating solution is desirable, and among them, an epoxy resin, a urethane resin, a Teflon resin, a polyimide resin, etc. In view of cost, epoxy resin is desirable.
[0030]
On the other hand, the insulating layers 2a to 2e are preferably made of ceramics such as alumina, aluminum nitride, silicon nitride, and silicon carbide. In particular, alumina is the main component, and silicon oxide, magnesium oxide, calcium oxide, It is desirable to consist of the composition which added manganese oxide etc. In addition to ceramics, plastic is also applicable.
[0031]
(module)
In the electronic component mounting board of the present invention described above, the resistor 10 forming surface (back surface) of the insulating substrate 2 is housed in a metal case, and the connector of the metal case and the connection terminal of the electronic component mounting board are electrically connected. After the connection, the electronic control unit can be formed by filling the resin in the metal case.
[0032]
(Production method)
In order to produce the electronic component mounting substrate, for example, first, a sintering aid component is added to ceramic powder for forming an insulating substrate, and further, an appropriate organic binder, organic solvent, plasticizer, dispersion A slurry is prepared by adding and mixing agents. Then, this slurry is formed into a sheet shape by adopting a conventionally known sheet forming method such as a doctor blade method or a calender roll method, and cut to produce a ceramic green sheet, and then to a predetermined position of the green sheet. A via hole is formed.
[0033]
Also, using a conductive paste obtained by adding ceramic powder or glass powder to a high melting point metal such as tungsten or molybdenum as desired, and adding and mixing an organic binder, organic solvent, plasticizer, etc. to this, A conductor paste is filled into the via hole by a screen printing method or the like, or a circuit pattern for forming a surface wiring layer and an internal wiring layer is formed.
[0034]
In the conductive paste, the total amount of metal selected from the group of Cu, silver, platinum, and palladium is 60 parts by weight or less, particularly 50 parts by weight or less, with respect to 100 parts by weight of tungsten and molybdenum in order to reduce resistance. Further, 5 to 50 parts by weight can be added.
[0035]
After that, a plurality of green sheets on which via-hole conductors and wiring layers are formed are laminated and pressure-bonded, and then fired in a reducing atmosphere of, for example, 1200 to 2000 ° C., particularly 1500 to 1700 ° C., thereby providing the insulating substrate having the wiring layers and via-hole conductors Is made.
[0036]
Next, plating is performed on the surface wiring layer of the obtained insulating substrate. According to the present invention, the surface wiring layer on the electronic component mounting surface side and the surface wiring layer forming the test pad are subjected to Ni or Cu plating (primary plating) and Au plating (secondary plating) and connected to the resistor. Only the Ni or Cu plating (primary plating) is applied to the surface wiring layer.
[0037]
Then, the surface of the surface wiring layer connected to the resistor formed only with Ni or Cu plating film is coated with a Cu conductor by a printing method such as a screen printing method using Cu paste, and then, for example, non-oxidizing A Cu metallized layer is formed by baking at 600 to 900 ° C. in an atmosphere.
[0038]
Thereafter, a resistor pattern is formed by a printing method such as a screen printing method using a resistor forming paste at a predetermined position on the back surface of the insulating substrate including the Cu metallized surface. For example, a non-oxidizing atmosphere at 600 to 900 ° C. A resistor is formed by baking inside.
[0039]
Moreover, after printing the glass paste for over-glass formation which consists of predetermined composition on the resistor surface, for example, after baking in 500-650 degreeC non-oxidizing atmosphere and forming an over-glass layer, on a resistor On the other hand, the entire glass substrate is irradiated with a laser or the like to form a predetermined cut groove in the resistor, so that the resistor is finally trimmed to a required resistance value. The over glass layer may be formed only on the surface of the resistor forming portion, or may be formed on the entire surface except the test pad portion on the back surface of the insulating substrate.
[0040]
In order to prevent moisture absorption and oxidation of the resistor, a resin layer is formed by a printing method on the entire surface of the resistor or on the entire surface except the test pad portion on the back surface of the insulating substrate. Further, when the resin layer is an ultraviolet curable resin, the resin layer is formed by curing with ultraviolet irradiation, and when the resin layer is a thermosetting resin, for example, by heating to 100 to 200 ° C.
[0041]
An electronic component such as a semiconductor element or a capacitor is mounted on the electronic component mounting surface of the electronic component mounting substrate thus manufactured via a connection terminal such as solder. Then, the electrical characteristics of the mounted electronic component are confirmed by bringing the probe pin into contact with two test pads connected via the electronic component using a board tester or the like. According to the present invention, the electronic component and the test pad are formed on different surfaces of the insulating substrate, but the inspection can be performed without any trouble by bringing a jig made of a substrate having a plurality of probe pins into contact with the back surface.
[0042]
An electronic component mounting board on which good electrical characteristics of the electronic component have been confirmed is housed and fixed in an aluminum case coated with an adhesive such as silicon with a resistor forming surface as an adhesive surface. In addition, a connector is formed on the aluminum case, and the connector and the circuit of the electronic component mounting substrate are electrically connected by a wire such as an Al wire.
[0043]
Thereafter, a protective material such as silicon gel excellent in electrical insulation, heat dissipation and shock absorption is injected into the aluminum case, and the electronic control unit is covered with a resin lid such as polybutylene terephthalate (PBT). Can be formed.
[0044]
【The invention's effect】
As described above in detail, according to the electronic component mounting substrate of the present invention, a plurality of electronic components are mounted on one surface of the substrate, and the electrical characteristics of the resistor and the electronic component are confirmed on the other surface (back surface). By forming the test pad for the electronic component, the electronic component mounting substrate can be reduced in size and density at low cost without reducing the heat dissipation of the electronic component with a simple structure.
[0045]
Further, the test pad is provided with a surface wiring layer mainly composed of tungsten and / or molybdenum formed on the surface of the insulating substrate, and a plating film formed on at least one layer on the surface wiring layer surface. The test pad is excellent in moisture resistance, oxidation resistance, and chemical resistance to the plating solution.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view showing an example of an electronic component mounting board according to the present invention.
2 is a plan view showing (a) an electronic component mounting surface and (b) a resistor forming surface of the electronic component mounting substrate of FIG. 1;
FIG. 3 is a plan view showing (a) an electronic component mounting surface and (b) a resistor forming surface of an example of a conventional electronic component mounting substrate.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Electronic component mounting board 2 Insulating board 2a-2e Insulating layer 3, 11, 15 Surface wiring layer 4 Electronic component 5 Connection terminal 6, 16 Plating film 6a, 16a Ni plating film 6b, 16b Au plating film 7 Via-hole conductor 8 Internal wiring Layer 10 Resistor 13 Test pad 20 Protective layer 20a Over glass layer 20b Resin layer 18 Cu metallized layer

Claims (5)

搭載される複数の電子部品の全てが絶縁基板の一方の主面に搭載されているとともに、所定のパターンに形成された抵抗体材料からなり、前記電子部品に電気的に接続されて該電子部品に供給される電圧を調整する抵抗体と、前記電子部品の電気特性確認用のテストパッドとが前記絶縁基板の他方の主面のみに配置されていることを特徴とする電子部品搭載基板。 With all of the plurality of electronic components to be mounted is the mounting tower on one main surface of the insulating substrate, a resistor body material formed into a predetermined pattern, electrically connected to the electronic component electronic electronic component mounting board, characterized in that a resistor for adjusting the voltage supplied to the component, and the pre-Symbol test pad for electrical characterization of electronic components are disposed only on the other main surface of the insulating substrate . 前記テストパッドが、前記絶縁基板の前記他方の主面に形成されたタングステンおよび／またはモリブデンを主成分とする第１の表面配線層と、該第１の表面配線層の表面に形成された第１のメッキ膜とを備えることを特徴とする請求項１記載の電子部品搭載基板。The test pad, a first surface wiring layer mainly composed of the other tungsten and / or molybdenum formed on a main surface of the insulating substrate was made form the surface of the first surface wiring layer The electronic component mounting board according to claim 1, further comprising a first plating film. 前記第１のメッキ膜が、前記第１の表面配線層の表面に形成された厚み５〜１５μｍのＮｉまたはＣｕからなる第２のメッキ膜と、該第２のメッキ膜の表面に形成された厚み０．０３〜０．５μｍのＡｕメッキ膜とからなることを特徴とする請求項２記載の電子部品搭載基板。The first plating film, and a second plating film consisting of Ni or Cu of the first thickness formed on the surface of the surface wiring layer 5 to 15 [mu] m, formed on the surface of the second plating film 3. The electronic component mounting substrate according to claim 2, comprising an Au plating film having a thickness of 0.03 to 0.5 [mu] m. 前記抵抗体が、前記絶縁基板の前記他方の主面に形成された第２の表面配線層と、該第２の表面配線層の表面に形成されたＮｉまたはＣｕからなる第３のメッキ膜および該第３のメッキ膜の表面に形成されたＣｕを主成分としたメタライズ層を介して接続されていることを特徴とする請求項１乃至３のいずれか記載の電子部品搭載基板。Said resistor, said second surface wiring layer formed on the other main surface of the insulating substrate, the third plating layer up for made of the second surface wiring layer formed on a surface with Ni or Cu of Yobi該third electronic component mounting board according to any one of claims 1 to 3, wherein Rukoto the Cu formed on the surface of the plating film are connected through a metallization layer mainly composed of. 前記絶縁基板の前記他方の主面の前記テストパッド以外の領域が保護層によって被覆されていることを特徴とする請求項１乃至４のいずれか記載の電子部品搭載基板。 5. The electronic component mounting substrate according to claim 1 , wherein a region other than the test pad on the other main surface of the insulating substrate is covered with a protective layer.
JP2000396301A 2000-12-26 2000-12-26 Electronic component mounting board Expired - Fee Related JP4540223B2 (en)

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KR101085752B1 (en) 2010-05-10 2011-11-21 삼성전기주식회사 Circuit board and method for testing component built in the circuit board
JP6155545B2 (en) * 2012-03-15 2017-07-05 株式会社デンソー Circuit board with external connection conductor and manufacturing method thereof
JP6235423B2 (en) 2014-06-30 2017-11-22 東芝メモリ株式会社 Semiconductor device
JP2020102513A (en) * 2018-12-21 2020-07-02 株式会社ノーリツ Electronic device and hot water device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01119557A (en) * 1987-10-30 1989-05-11 Kyocera Corp Colored alumina-based sintered compact
JPH05183259A (en) * 1991-12-27 1993-07-23 Ibiden Co Ltd Manufacture of high density printed wiring board
JPH08167630A (en) * 1994-12-15 1996-06-25 Hitachi Ltd Chip connection structure
JPH08274435A (en) * 1995-03-29 1996-10-18 Sumitomo Kinzoku Electro Device:Kk Ceramic circuit board
JPH098482A (en) * 1995-06-19 1997-01-10 Oki Electric Ind Co Ltd Heat dissipating method of switching element

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01119557A (en) * 1987-10-30 1989-05-11 Kyocera Corp Colored alumina-based sintered compact
JPH05183259A (en) * 1991-12-27 1993-07-23 Ibiden Co Ltd Manufacture of high density printed wiring board
JPH08167630A (en) * 1994-12-15 1996-06-25 Hitachi Ltd Chip connection structure
JPH08274435A (en) * 1995-03-29 1996-10-18 Sumitomo Kinzoku Electro Device:Kk Ceramic circuit board
JPH098482A (en) * 1995-06-19 1997-01-10 Oki Electric Ind Co Ltd Heat dissipating method of switching element

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