JP4524310B2 - ハブベースのメモリシステムにおける書込みコマンドを終了させる方法とシステム - Google Patents
ハブベースのメモリシステムにおける書込みコマンドを終了させる方法とシステム Download PDFInfo
- Publication number
- JP4524310B2 JP4524310B2 JP2007515399A JP2007515399A JP4524310B2 JP 4524310 B2 JP4524310 B2 JP 4524310B2 JP 2007515399 A JP2007515399 A JP 2007515399A JP 2007515399 A JP2007515399 A JP 2007515399A JP 4524310 B2 JP4524310 B2 JP 4524310B2
- Authority
- JP
- Japan
- Prior art keywords
- memory
- command
- hub
- write command
- write
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims description 17
- 238000011144 upstream manufacturing Methods 0.000 claims description 5
- 230000006870 function Effects 0.000 claims description 3
- 230000003287 optical effect Effects 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 238000004891 communication Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000004044 response Effects 0.000 description 4
- 230000001360 synchronised effect Effects 0.000 description 3
- 241000723353 Chrysanthemum Species 0.000 description 1
- 235000005633 Chrysanthemum balsamita Nutrition 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 239000013307 optical fiber Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
- G06F13/423—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1684—Details of memory controller using multiple buses
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4247—Bus transfer protocol, e.g. handshake; Synchronisation on a daisy chain bus
- G06F13/4256—Bus transfer protocol, e.g. handshake; Synchronisation on a daisy chain bus using a clocked protocol
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- Read Only Memory (AREA)
- Memory System (AREA)
- Information Transfer Systems (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Description
102 システムメモリ
104 プロセッサ
106 プロセッサバス
108 キャッシュメモリ
110 システムコントローラ
112 グラフィックスコントローラ
114 ビデオ端末
118 入力デバイス
120 出力デバイス
124 データストレージデバイス
130 メモリモジュール
134 高速リンク
140 メモリハブ
148 メモリデバイス
150 バスシステム
Claims (5)
- メモリハブアーキテクチャを有するシステムメモリにおいて書込みコマンドを処理する方法であって、前記システムメモリは複数のメモリモジュールを含み、各メモリモジュールはメモリハブを含む、前記方法は、
前記書込みコマンドを前記メモリハブに適用するステップであって、前記書込みコマンドはコマンド部分と書込みデータ部分からなる、ステップと、
前記メモリハブにおいて、前記書込みコマンドが、対応するメモリモジュールに向けられているかどうかを判定するステップと、
前記書込みコマンドが、対応するメモリモジュールに向けられていないと前記メモリハブで判定された場合、前記書込みコマンドを次のメモリハブにダウンストリーム転送するステップと、
前記書込みコマンドが、対応するメモリモジュールに向けられていると前記メモリハブで判定されるまで、前記判定するステップ及び前記転送するステップを繰り返すステップと、
前記書込みコマンドが、対応するメモリモジュールに向けられていると前記メモリハブで判定された場合、前記書込みデータ部分のダウンストリーム転送を終了するステップと、
を含むことを特徴とする方法。 - 前記終了するステップは、さらに前記コマンド部分のダウンストリーム転送を終了することを特徴とする請求項1に記載の方法。
- 前記メモリハブに前記書込みコマンドを適用することに先立って、前記メモリハブに読取りコマンドを適用するステップをさらに含み、前記読取りコマンドは、前記書込みコマンドが向けられているメモリハブのダウンストリームメモリハブへ向けられることを特徴とする請求項1に記載の方法。
- 前記読取りおよび書込みコマンドが適用されるときの両者の間の時間間隔が定義され、前記時間間隔は、前記書込みコマンドが向けられているアップストリームメモリハブに対する、前記読取りコマンドが向けられているダウンストリームメモリハブの位置の関数であることを特徴とする請求項3に記載の方法。
- 前記判定するステップは、前記書込みコマンドのアドレスコンポーネントを、前記メモリモジュールに関連付けられたアドレスと比較することである、ことを特徴とする請求項1に記載の方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/857,467 US7363419B2 (en) | 2004-05-28 | 2004-05-28 | Method and system for terminating write commands in a hub-based memory system |
PCT/US2005/018783 WO2005119457A2 (en) | 2004-05-28 | 2005-05-27 | Method and system for terminating write commands in a hub-based memory system |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010092895A Division JP5238747B2 (ja) | 2004-05-28 | 2010-04-14 | ハブベースのシステムメモリにおける書込みコマンドを終了させる方法とシステム |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008501194A JP2008501194A (ja) | 2008-01-17 |
JP4524310B2 true JP4524310B2 (ja) | 2010-08-18 |
Family
ID=35426752
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007515399A Active JP4524310B2 (ja) | 2004-05-28 | 2005-05-27 | ハブベースのメモリシステムにおける書込みコマンドを終了させる方法とシステム |
JP2010092895A Active JP5238747B2 (ja) | 2004-05-28 | 2010-04-14 | ハブベースのシステムメモリにおける書込みコマンドを終了させる方法とシステム |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010092895A Active JP5238747B2 (ja) | 2004-05-28 | 2010-04-14 | ハブベースのシステムメモリにおける書込みコマンドを終了させる方法とシステム |
Country Status (6)
Country | Link |
---|---|
US (2) | US7363419B2 (ja) |
EP (2) | EP2562653B1 (ja) |
JP (2) | JP4524310B2 (ja) |
KR (1) | KR100947755B1 (ja) |
TW (1) | TWI341973B (ja) |
WO (1) | WO2005119457A2 (ja) |
Families Citing this family (48)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7836252B2 (en) | 2002-08-29 | 2010-11-16 | Micron Technology, Inc. | System and method for optimizing interconnections of memory devices in a multichip module |
US7133991B2 (en) * | 2003-08-20 | 2006-11-07 | Micron Technology, Inc. | Method and system for capturing and bypassing memory transactions in a hub-based memory system |
US7136958B2 (en) | 2003-08-28 | 2006-11-14 | Micron Technology, Inc. | Multiple processor system and method including multiple memory hub modules |
US7120743B2 (en) | 2003-10-20 | 2006-10-10 | Micron Technology, Inc. | Arbitration system and method for memory responses in a hub-based memory system |
US7788451B2 (en) | 2004-02-05 | 2010-08-31 | Micron Technology, Inc. | Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system |
US7366864B2 (en) | 2004-03-08 | 2008-04-29 | Micron Technology, Inc. | Memory hub architecture having programmable lane widths |
US7257683B2 (en) | 2004-03-24 | 2007-08-14 | Micron Technology, Inc. | Memory arbitration system and method having an arbitration packet protocol |
US7120723B2 (en) | 2004-03-25 | 2006-10-10 | Micron Technology, Inc. | System and method for memory hub-based expansion bus |
US6980042B2 (en) * | 2004-04-05 | 2005-12-27 | Micron Technology, Inc. | Delay line synchronizer apparatus and method |
US7590797B2 (en) | 2004-04-08 | 2009-09-15 | Micron Technology, Inc. | System and method for optimizing interconnections of components in a multichip memory module |
US7296129B2 (en) | 2004-07-30 | 2007-11-13 | International Business Machines Corporation | System, method and storage medium for providing a serialized memory interface with a bus repeater |
US7392331B2 (en) | 2004-08-31 | 2008-06-24 | Micron Technology, Inc. | System and method for transmitting data packets in a computer system having a memory hub architecture |
US7331010B2 (en) | 2004-10-29 | 2008-02-12 | International Business Machines Corporation | System, method and storage medium for providing fault detection and correction in a memory subsystem |
US7299313B2 (en) * | 2004-10-29 | 2007-11-20 | International Business Machines Corporation | System, method and storage medium for a memory subsystem command interface |
US7512762B2 (en) | 2004-10-29 | 2009-03-31 | International Business Machines Corporation | System, method and storage medium for a memory subsystem with positional read data latency |
US7478259B2 (en) | 2005-10-31 | 2009-01-13 | International Business Machines Corporation | System, method and storage medium for deriving clocks in a memory system |
US7685392B2 (en) | 2005-11-28 | 2010-03-23 | International Business Machines Corporation | Providing indeterminate read data latency in a memory system |
JP5065618B2 (ja) * | 2006-05-16 | 2012-11-07 | 株式会社日立製作所 | メモリモジュール |
US7669086B2 (en) * | 2006-08-02 | 2010-02-23 | International Business Machines Corporation | Systems and methods for providing collision detection in a memory system |
US7870459B2 (en) | 2006-10-23 | 2011-01-11 | International Business Machines Corporation | High density high reliability memory module with power gating and a fault tolerant address and command bus |
US7721140B2 (en) | 2007-01-02 | 2010-05-18 | International Business Machines Corporation | Systems and methods for improving serviceability of a memory system |
WO2008098342A1 (en) * | 2007-02-16 | 2008-08-21 | Mosaid Technologies Incorporated | Semiconductor device and method for reducing power consumption in a system having interconnected devices |
US8060869B1 (en) * | 2007-06-08 | 2011-11-15 | Oracle America, Inc. | Method and system for detecting memory problems in user programs |
US8082482B2 (en) | 2007-08-31 | 2011-12-20 | International Business Machines Corporation | System for performing error correction operations in a memory hub device of a memory module |
US8086936B2 (en) | 2007-08-31 | 2011-12-27 | International Business Machines Corporation | Performing error correction at a memory device level that is transparent to a memory channel |
US7865674B2 (en) * | 2007-08-31 | 2011-01-04 | International Business Machines Corporation | System for enhancing the memory bandwidth available through a memory module |
US20100269021A1 (en) * | 2007-09-05 | 2010-10-21 | Gower Kevin C | Method for Performing Error Correction Operations in a Memory Hub Device of a Memory Module |
US8019919B2 (en) * | 2007-09-05 | 2011-09-13 | International Business Machines Corporation | Method for enhancing the memory bandwidth available through a memory module |
US7925825B2 (en) | 2008-01-24 | 2011-04-12 | International Business Machines Corporation | System to support a full asynchronous interface within a memory hub device |
US7930470B2 (en) | 2008-01-24 | 2011-04-19 | International Business Machines Corporation | System to enable a memory hub device to manage thermal conditions at a memory device level transparent to a memory controller |
US7925824B2 (en) | 2008-01-24 | 2011-04-12 | International Business Machines Corporation | System to reduce latency by running a memory channel frequency fully asynchronous from a memory device frequency |
US8140936B2 (en) | 2008-01-24 | 2012-03-20 | International Business Machines Corporation | System for a combined error correction code and cyclic redundancy check code for a memory channel |
US7925826B2 (en) | 2008-01-24 | 2011-04-12 | International Business Machines Corporation | System to increase the overall bandwidth of a memory channel by allowing the memory channel to operate at a frequency independent from a memory device frequency |
US7930469B2 (en) * | 2008-01-24 | 2011-04-19 | International Business Machines Corporation | System to provide memory system power reduction without reducing overall memory system performance |
US20100005214A1 (en) * | 2008-07-01 | 2010-01-07 | International Business Machines Corporation | Enhancing bus efficiency in a memory system |
US20100005219A1 (en) * | 2008-07-01 | 2010-01-07 | International Business Machines Corporation | 276-pin buffered memory module with enhanced memory system interconnect and features |
US20100005212A1 (en) * | 2008-07-01 | 2010-01-07 | International Business Machines Corporation | Providing a variable frame format protocol in a cascade interconnected memory system |
US20100005220A1 (en) * | 2008-07-01 | 2010-01-07 | International Business Machines Corporation | 276-pin buffered memory module with enhanced memory system interconnect and features |
US7717752B2 (en) * | 2008-07-01 | 2010-05-18 | International Business Machines Corporation | 276-pin buffered memory module with enhanced memory system interconnect and features |
US20100005206A1 (en) * | 2008-07-01 | 2010-01-07 | International Business Machines Corporation | Automatic read data flow control in a cascade interconnect memory system |
US20100005218A1 (en) * | 2008-07-01 | 2010-01-07 | International Business Machines Corporation | Enhanced cascade interconnected memory system |
JP2010251319A (ja) | 2009-04-15 | 2010-11-04 | Chou Hsien Tsai | 双方向電気的連接が可能なソケット構造 |
US8521980B2 (en) * | 2009-07-16 | 2013-08-27 | Mosaid Technologies Incorporated | Simultaneous read and write data transfer |
US8756273B2 (en) * | 2011-11-28 | 2014-06-17 | Sap Ag | Handling of cross-system metadata in a system landscape with a hub and backend-systems |
US8825967B2 (en) | 2011-12-08 | 2014-09-02 | Conversant Intellectual Property Management Inc. | Independent write and read control in serially-connected devices |
US9357649B2 (en) | 2012-05-08 | 2016-05-31 | Inernational Business Machines Corporation | 276-pin buffered memory card with enhanced memory system interconnect |
US9519315B2 (en) | 2013-03-12 | 2016-12-13 | International Business Machines Corporation | 276-pin buffered memory card with enhanced memory system interconnect |
US11404136B2 (en) * | 2020-12-16 | 2022-08-02 | Micron Technology, Inc. | Memory device protection using interleaved multibit symbols |
Family Cites Families (271)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US227798A (en) * | 1880-05-18 | Buckle | ||
US665329A (en) * | 1900-02-20 | 1901-01-01 | John J Koetzner | Temporary cover or top for counters, saloon-bars, &c. |
US697926A (en) * | 1902-02-25 | 1902-04-15 | Kempshall Mfg Co | Golf-ball. |
US729709A (en) * | 1902-03-19 | 1903-06-02 | American Telephone & Telegraph | Loaded electric circuit. |
US3742253A (en) | 1971-03-15 | 1973-06-26 | Burroughs Corp | Three state logic device with applications |
US4078228A (en) | 1975-03-24 | 1978-03-07 | Ohkura Electric Co., Ltd. | Loop data highway communication system |
US4045781A (en) | 1976-02-13 | 1977-08-30 | Digital Equipment Corporation | Memory module with selectable byte addressing for digital data processing system |
US4253146A (en) | 1978-12-21 | 1981-02-24 | Burroughs Corporation | Module for coupling computer-processors |
US4253144A (en) | 1978-12-21 | 1981-02-24 | Burroughs Corporation | Multi-processor communication network |
US4245306A (en) | 1978-12-21 | 1981-01-13 | Burroughs Corporation | Selection of addressed processor in a multi-processor network |
US4240143A (en) | 1978-12-22 | 1980-12-16 | Burroughs Corporation | Hierarchical multi-processor network for memory sharing |
US4608702A (en) | 1984-12-21 | 1986-08-26 | Advanced Micro Devices, Inc. | Method for digital clock recovery from Manchester-encoded signals |
US4724520A (en) | 1985-07-01 | 1988-02-09 | United Technologies Corporation | Modular multiport data hub |
JPS6240565A (ja) * | 1985-08-15 | 1987-02-21 | Hitachi Ltd | メモリ制御方式 |
US4843263A (en) * | 1986-01-10 | 1989-06-27 | Nec Corporation | Clock timing controller for a plurality of LSI chips |
US4707823A (en) | 1986-07-21 | 1987-11-17 | Chrysler Motors Corporation | Fiber optic multiplexed data acquisition system |
US4831520A (en) | 1987-02-24 | 1989-05-16 | Digital Equipment Corporation | Bus interface circuit for digital data processor |
JPH07117863B2 (ja) | 1987-06-26 | 1995-12-18 | 株式会社日立製作所 | オンラインシステムの再立上げ方式 |
US4891808A (en) | 1987-12-24 | 1990-01-02 | Coherent Communication Systems Corp. | Self-synchronizing multiplexer |
US5251303A (en) | 1989-01-13 | 1993-10-05 | International Business Machines Corporation | System for DMA block data transfer based on linked control blocks |
US5442770A (en) | 1989-01-24 | 1995-08-15 | Nec Electronics, Inc. | Triple port cache memory |
US4953930A (en) | 1989-03-15 | 1990-09-04 | Ramtech, Inc. | CPU socket supporting socket-to-socket optical communications |
US4982185A (en) | 1989-05-17 | 1991-01-01 | Blh Electronics, Inc. | System for synchronous measurement in a digital computer network |
JPH03156795A (ja) | 1989-11-15 | 1991-07-04 | Toshiba Micro Electron Kk | 半導体メモリ回路装置 |
US5317752A (en) | 1989-12-22 | 1994-05-31 | Tandem Computers Incorporated | Fault-tolerant computer system with auto-restart after power-fall |
US5327553A (en) | 1989-12-22 | 1994-07-05 | Tandem Computers Incorporated | Fault-tolerant computer system with /CONFIG filesystem |
US5313590A (en) | 1990-01-05 | 1994-05-17 | Maspar Computer Corporation | System having fixedly priorized and grouped by positions I/O lines for interconnecting router elements in plurality of stages within parrallel computer |
JP2772103B2 (ja) | 1990-03-28 | 1998-07-02 | 株式会社東芝 | 計算機システム立上げ方式 |
US5243703A (en) | 1990-04-18 | 1993-09-07 | Rambus, Inc. | Apparatus for synchronously generating clock signals in a data processing system |
IL96808A (en) | 1990-04-18 | 1996-03-31 | Rambus Inc | Introductory / Origin Circuit Agreed Using High-Performance Brokerage |
BE1004668A3 (nl) | 1991-04-02 | 1993-01-05 | Bell Telephone Mfg | Beschermingsinrichting voor een optische zender/ontvangerinrichting. |
US5461627A (en) | 1991-12-24 | 1995-10-24 | Rypinski; Chandos A. | Access protocol for a common channel wireless network |
JP2554816B2 (ja) | 1992-02-20 | 1996-11-20 | 株式会社東芝 | 半導体記憶装置 |
DE4390991T1 (de) | 1992-03-06 | 1995-02-23 | Rambus Inc | Verfahren und Schaltungsanordnung zum Minimieren der Takt-Daten-Schieflage in einem Bussystem |
US5355391A (en) | 1992-03-06 | 1994-10-11 | Rambus, Inc. | High speed bus system |
EP0632913B1 (en) | 1992-03-25 | 2001-10-31 | Sun Microsystems, Inc. | Fiber optic memory coupling system |
US5432907A (en) | 1992-05-12 | 1995-07-11 | Network Resources Corporation | Network hub with integrated bridge |
US5270964A (en) | 1992-05-19 | 1993-12-14 | Sun Microsystems, Inc. | Single in-line memory module |
GB2270780A (en) | 1992-09-21 | 1994-03-23 | Ibm | Scatter-gather in data processing systems. |
JPH0713945A (ja) | 1993-06-16 | 1995-01-17 | Nippon Sheet Glass Co Ltd | 演算処理部および制御・記憶部分離型マルチプロセッサ ・システムのバス構造 |
US5768629A (en) | 1993-06-24 | 1998-06-16 | Discovision Associates | Token-based adaptive video processing arrangement |
US5497494A (en) | 1993-07-23 | 1996-03-05 | International Business Machines Corporation | Method for saving and restoring the state of a CPU executing code in protected mode |
US5729709A (en) | 1993-11-12 | 1998-03-17 | Intel Corporation | Memory controller with burst addressing circuit |
US5502621A (en) | 1994-03-31 | 1996-03-26 | Hewlett-Packard Company | Mirrored pin assignment for two sided multi-chip layout |
US5566325A (en) | 1994-06-30 | 1996-10-15 | Digital Equipment Corporation | Method and apparatus for adaptive memory access |
US6175571B1 (en) | 1994-07-22 | 2001-01-16 | Network Peripherals, Inc. | Distributed memory switching hub |
US5978567A (en) | 1994-07-27 | 1999-11-02 | Instant Video Technologies Inc. | System for distribution of interactive multimedia and linear programs by enabling program webs which include control scripts to define presentation by client transceiver |
US5553070A (en) | 1994-09-13 | 1996-09-03 | Riley; Robert E. | Data link module for time division multiplexing control systems |
JPH08123717A (ja) | 1994-10-25 | 1996-05-17 | Oki Electric Ind Co Ltd | 半導体記憶装置 |
US6804760B2 (en) | 1994-12-23 | 2004-10-12 | Micron Technology, Inc. | Method for determining a type of memory present in a system |
US5715456A (en) | 1995-02-13 | 1998-02-03 | International Business Machines Corporation | Method and apparatus for booting a computer system without pre-installing an operating system |
US5875352A (en) | 1995-11-03 | 1999-02-23 | Sun Microsystems, Inc. | Method and apparatus for multiple channel direct memory access control |
US5834956A (en) | 1995-12-29 | 1998-11-10 | Intel Corporation | Core clock correction in a 2/N mode clocking scheme |
US7681005B1 (en) | 1996-01-11 | 2010-03-16 | Micron Technology, Inc. | Asynchronously-accessible memory device with mode selection circuitry for burst or pipelined operation |
US5966724A (en) | 1996-01-11 | 1999-10-12 | Micron Technology, Inc. | Synchronous memory device with dual page and burst mode operations |
US5832250A (en) | 1996-01-26 | 1998-11-03 | Unisys Corporation | Multi set cache structure having parity RAMs holding parity bits for tag data and for status data utilizing prediction circuitry that predicts and generates the needed parity bits |
US5819304A (en) | 1996-01-29 | 1998-10-06 | Iowa State University Research Foundation, Inc. | Random access memory assembly |
US5659798A (en) | 1996-02-02 | 1997-08-19 | Blumrich; Matthias Augustin | Method and system for initiating and loading DMA controller registers by using user-level programs |
US5687325A (en) | 1996-04-19 | 1997-11-11 | Chang; Web | Application specific field programmable gate array |
US6064706A (en) | 1996-05-01 | 2000-05-16 | Alcatel Usa, Inc. | Apparatus and method of desynchronizing synchronously mapped asynchronous data |
US5818844A (en) | 1996-06-06 | 1998-10-06 | Advanced Micro Devices, Inc. | Address generation and data path arbitration to and from SRAM to accommodate multiple transmitted packets |
US5900020A (en) * | 1996-06-27 | 1999-05-04 | Sequent Computer Systems, Inc. | Method and apparatus for maintaining an order of write operations by processors in a multiprocessor computer to maintain memory consistency |
US5875454A (en) | 1996-07-24 | 1999-02-23 | International Business Machiness Corporation | Compressed data cache storage system |
JPH1049511A (ja) | 1996-08-02 | 1998-02-20 | Oki Electric Ind Co Ltd | 1チップマイクロコンピュータ |
JP4070255B2 (ja) | 1996-08-13 | 2008-04-02 | 富士通株式会社 | 半導体集積回路 |
TW304288B (en) | 1996-08-16 | 1997-05-01 | United Microelectronics Corp | Manufacturing method of semiconductor memory device with capacitor |
US5706224A (en) | 1996-10-10 | 1998-01-06 | Quality Semiconductor, Inc. | Content addressable memory and random access memory partition circuit |
US6272600B1 (en) * | 1996-11-15 | 2001-08-07 | Hyundai Electronics America | Memory request reordering in a data processing system |
US6167486A (en) | 1996-11-18 | 2000-12-26 | Nec Electronics, Inc. | Parallel access virtual channel memory system with cacheable channels |
EP0849685A3 (en) | 1996-12-19 | 2000-09-06 | Texas Instruments Incorporated | Communication bus system between processors and memory modules |
US6308248B1 (en) | 1996-12-31 | 2001-10-23 | Compaq Computer Corporation | Method and system for allocating memory space using mapping controller, page table and frame numbers |
US6031241A (en) | 1997-03-11 | 2000-02-29 | University Of Central Florida | Capillary discharge extreme ultraviolet lamp source for EUV microlithography and other related applications |
US6271582B1 (en) | 1997-04-07 | 2001-08-07 | Micron Technology, Inc. | Interdigitated leads-over-chip lead frame, device, and method for supporting an integrated circuit die |
KR100202385B1 (ko) | 1997-06-04 | 1999-06-15 | 윤종용 | Hdlc를 이용한 반이중 통신용 송신 장치 |
US5946712A (en) | 1997-06-04 | 1999-08-31 | Oak Technology, Inc. | Apparatus and method for reading data from synchronous memory |
US6044429A (en) * | 1997-07-10 | 2000-03-28 | Micron Technology, Inc. | Method and apparatus for collision-free data transfers in a memory device with selectable data or address paths |
US6243769B1 (en) | 1997-07-18 | 2001-06-05 | Micron Technology, Inc. | Dynamic buffer allocation for a computer system |
US6073190A (en) | 1997-07-18 | 2000-06-06 | Micron Electronics, Inc. | System for dynamic buffer allocation comprising control logic for controlling a first address buffer and a first data buffer as a matched pair |
US6760833B1 (en) | 1997-08-01 | 2004-07-06 | Micron Technology, Inc. | Split embedded DRAM processor |
US6105075A (en) | 1997-08-05 | 2000-08-15 | Adaptec, Inc. | Scatter gather memory system for a hardware accelerated command interpreter engine |
US6137780A (en) * | 1997-08-07 | 2000-10-24 | At&T Corp | Apparatus and method to monitor communication system status |
JP4014708B2 (ja) | 1997-08-21 | 2007-11-28 | 株式会社ルネサステクノロジ | 半導体集積回路装置の設計方法 |
US6249802B1 (en) | 1997-09-19 | 2001-06-19 | Silicon Graphics, Inc. | Method, system, and computer program product for allocating physical memory in a distributed shared memory network |
US6223301B1 (en) | 1997-09-30 | 2001-04-24 | Compaq Computer Corporation | Fault tolerant memory |
KR100603687B1 (ko) | 1997-10-10 | 2006-07-20 | 람버스 인코포레이티드 | 최소의 대기시간으로 페일-세이프 재동기화를 위한 방법및 장치 |
JPH11120120A (ja) | 1997-10-13 | 1999-04-30 | Fujitsu Ltd | カードバス用インターフェース回路及びそれを有するカードバス用pcカード |
FR2770008B1 (fr) * | 1997-10-16 | 2001-10-12 | Alsthom Cge Alkatel | Dispositif de communication entre plusieurs processeurs |
US5987196A (en) | 1997-11-06 | 1999-11-16 | Micron Technology, Inc. | Semiconductor structure having an optical signal path in a substrate and method for forming the same |
US6098158A (en) | 1997-12-18 | 2000-08-01 | International Business Machines Corporation | Software-enabled fast boot |
US6014721A (en) * | 1998-01-07 | 2000-01-11 | International Business Machines Corporation | Method and system for transferring data between buses having differing ordering policies |
US6023726A (en) | 1998-01-20 | 2000-02-08 | Netscape Communications Corporation | User configurable prefetch control system for enabling client to prefetch documents from a network server |
US6721860B2 (en) * | 1998-01-29 | 2004-04-13 | Micron Technology, Inc. | Method for bus capacitance reduction |
GB2333896B (en) * | 1998-01-31 | 2003-04-09 | Mitel Semiconductor Ab | Vertical cavity surface emitting laser |
US6742098B1 (en) * | 2000-10-03 | 2004-05-25 | Intel Corporation | Dual-port buffer-to-memory interface |
US7024518B2 (en) | 1998-02-13 | 2006-04-04 | Intel Corporation | Dual-port buffer-to-memory interface |
US6186400B1 (en) | 1998-03-20 | 2001-02-13 | Symbol Technologies, Inc. | Bar code reader with an integrated scanning component module mountable on printed circuit board |
US6038630A (en) | 1998-03-24 | 2000-03-14 | International Business Machines Corporation | Shared access control device for integrated system with multiple functional units accessing external structures over multiple data buses |
US6079008A (en) | 1998-04-03 | 2000-06-20 | Patton Electronics Co. | Multiple thread multiple data predictive coded parallel processing system and method |
US6247107B1 (en) | 1998-04-06 | 2001-06-12 | Advanced Micro Devices, Inc. | Chipset configured to perform data-directed prefetching |
JPH11316617A (ja) | 1998-05-01 | 1999-11-16 | Mitsubishi Electric Corp | 半導体回路装置 |
KR100283243B1 (ko) | 1998-05-11 | 2001-03-02 | 구자홍 | 운영체제의 부팅방법 |
US6167465A (en) | 1998-05-20 | 2000-12-26 | Aureal Semiconductor, Inc. | System for managing multiple DMA connections between a peripheral device and a memory and performing real-time operations on data carried by a selected DMA connection |
SG75958A1 (en) | 1998-06-01 | 2000-10-24 | Hitachi Ulsi Sys Co Ltd | Semiconductor device and a method of producing semiconductor device |
US6405280B1 (en) * | 1998-06-05 | 2002-06-11 | Micron Technology, Inc. | Packet-oriented synchronous DRAM interface supporting a plurality of orderings for data block transfers within a burst sequence |
US6301637B1 (en) | 1998-06-08 | 2001-10-09 | Storage Technology Corporation | High performance data paths |
US6134624A (en) | 1998-06-08 | 2000-10-17 | Storage Technology Corporation | High bandwidth cache system |
US6067649A (en) | 1998-06-10 | 2000-05-23 | Compaq Computer Corporation | Method and apparatus for a low power self test of a memory subsystem |
US6453377B1 (en) * | 1998-06-16 | 2002-09-17 | Micron Technology, Inc. | Computer including optical interconnect, memory unit, and method of assembling a computer |
US6289068B1 (en) | 1998-06-22 | 2001-09-11 | Xilinx, Inc. | Delay lock loop with clock phase shifter |
JP2000011640A (ja) | 1998-06-23 | 2000-01-14 | Nec Corp | 半導体記憶装置 |
FR2780535B1 (fr) * | 1998-06-25 | 2000-08-25 | Inst Nat Rech Inf Automat | Dispositif de traitement de donnees d'acquisition, notamment de donnees d'image |
JP3178423B2 (ja) | 1998-07-03 | 2001-06-18 | 日本電気株式会社 | バーチャルチャネルsdram |
US6286083B1 (en) | 1998-07-08 | 2001-09-04 | Compaq Computer Corporation | Computer system with adaptive memory arbitration scheme |
US7002982B1 (en) * | 1998-07-08 | 2006-02-21 | Broadcom Corporation | Apparatus and method for storing data |
JP3248617B2 (ja) * | 1998-07-14 | 2002-01-21 | 日本電気株式会社 | 半導体記憶装置 |
US6272609B1 (en) | 1998-07-31 | 2001-08-07 | Micron Electronics, Inc. | Pipelined memory controller |
US6061296A (en) | 1998-08-17 | 2000-05-09 | Vanguard International Semiconductor Corporation | Multiple data clock activation with programmable delay for use in multiple CAS latency memory devices |
US6219725B1 (en) | 1998-08-28 | 2001-04-17 | Hewlett-Packard Company | Method and apparatus for performing direct memory access transfers involving non-sequentially-addressable memory locations |
US6029250A (en) | 1998-09-09 | 2000-02-22 | Micron Technology, Inc. | Method and apparatus for adaptively adjusting the timing offset between a clock signal and digital signals transmitted coincident with that clock signal, and memory device and system using same |
US6622188B1 (en) | 1998-09-30 | 2003-09-16 | International Business Machines Corporation | 12C bus expansion apparatus and method therefor |
US6910109B2 (en) | 1998-09-30 | 2005-06-21 | Intel Corporation | Tracking memory page state |
US6587912B2 (en) | 1998-09-30 | 2003-07-01 | Intel Corporation | Method and apparatus for implementing multiple memory buses on a memory module |
TW498215B (en) | 1998-10-30 | 2002-08-11 | Ind Tech Res Inst | Ring topology network switch using dual-port memory |
US6243831B1 (en) | 1998-10-31 | 2001-06-05 | Compaq Computer Corporation | Computer system with power loss protection mechanism |
JP3248500B2 (ja) | 1998-11-12 | 2002-01-21 | 日本電気株式会社 | 半導体記憶装置およびそのデータ読み出し方法 |
US6434639B1 (en) | 1998-11-13 | 2002-08-13 | Intel Corporation | System for combining requests associated with one or more memory locations that are collectively associated with a single cache line to furnish a single memory operation |
US6453370B1 (en) | 1998-11-16 | 2002-09-17 | Infineion Technologies Ag | Using of bank tag registers to avoid a background operation collision in memory systems |
US6438622B1 (en) | 1998-11-17 | 2002-08-20 | Intel Corporation | Multiprocessor system including a docking system |
US6100735A (en) | 1998-11-19 | 2000-08-08 | Centillium Communications, Inc. | Segmented dual delay-locked loop for precise variable-phase clock generation |
US6430696B1 (en) | 1998-11-30 | 2002-08-06 | Micron Technology, Inc. | Method and apparatus for high speed data capture utilizing bit-to-bit timing correction, and memory device using same |
US6463059B1 (en) | 1998-12-04 | 2002-10-08 | Koninklijke Philips Electronics N.V. | Direct memory access execution engine with indirect addressing of circular queues in addition to direct memory addressing |
US6349363B2 (en) * | 1998-12-08 | 2002-02-19 | Intel Corporation | Multi-section cache with different attributes for each section |
US6374360B1 (en) | 1998-12-11 | 2002-04-16 | Micron Technology, Inc. | Method and apparatus for bit-to-bit timing correction of a high speed memory bus |
US6067262A (en) | 1998-12-11 | 2000-05-23 | Lsi Logic Corporation | Redundancy analysis for embedded memories with built-in self test and built-in self repair |
FR2787600B1 (fr) * | 1998-12-17 | 2001-11-16 | St Microelectronics Sa | Memoire tampon associee a plusieurs canaux de communication de donnees |
US6487556B1 (en) | 1998-12-18 | 2002-11-26 | International Business Machines Corporation | Method and system for providing an associative datastore within a data processing system |
US6191663B1 (en) | 1998-12-22 | 2001-02-20 | Intel Corporation | Echo reduction on bit-serial, multi-drop bus |
US6367074B1 (en) * | 1998-12-28 | 2002-04-02 | Intel Corporation | Operation of a system |
US6598154B1 (en) | 1998-12-29 | 2003-07-22 | Intel Corporation | Precoding branch instructions to reduce branch-penalty in pipelined processors |
US6061263A (en) | 1998-12-29 | 2000-05-09 | Intel Corporation | Small outline rambus in-line memory module |
US6324485B1 (en) | 1999-01-26 | 2001-11-27 | Newmillennia Solutions, Inc. | Application specific automated test equipment system for testing integrated circuit devices in a native environment |
EP1703520B1 (en) | 1999-02-01 | 2011-07-27 | Renesas Electronics Corporation | Semiconductor integrated circuit and nonvolatile memory element |
US6327650B1 (en) * | 1999-02-12 | 2001-12-04 | Vsli Technology, Inc. | Pipelined multiprocessing with upstream processor concurrently writing to local register and to register of downstream processor |
US6285349B1 (en) | 1999-02-26 | 2001-09-04 | Intel Corporation | Correcting non-uniformity in displays |
US6564329B1 (en) * | 1999-03-16 | 2003-05-13 | Linkup Systems Corporation | System and method for dynamic clock generation |
JP3633354B2 (ja) * | 1999-03-29 | 2005-03-30 | 株式会社日立製作所 | 半導体装置 |
US6496909B1 (en) | 1999-04-06 | 2002-12-17 | Silicon Graphics, Inc. | Method for managing concurrent access to virtual memory data structures |
US6381190B1 (en) * | 1999-05-13 | 2002-04-30 | Nec Corporation | Semiconductor memory device in which use of cache can be selected |
US6233376B1 (en) | 1999-05-18 | 2001-05-15 | The United States Of America As Represented By The Secretary Of The Navy | Embedded fiber optic circuit boards and integrated circuits |
JP3376315B2 (ja) | 1999-05-18 | 2003-02-10 | 日本電気株式会社 | ビット同期回路 |
US6449308B1 (en) | 1999-05-25 | 2002-09-10 | Intel Corporation | High-speed digital distribution system |
US6294937B1 (en) | 1999-05-25 | 2001-09-25 | Lsi Logic Corporation | Method and apparatus for self correcting parallel I/O circuitry |
JP3721283B2 (ja) | 1999-06-03 | 2005-11-30 | 株式会社日立製作所 | 主記憶共有型マルチプロセッサシステム |
JP2001014840A (ja) * | 1999-06-24 | 2001-01-19 | Nec Corp | 複数ラインバッファ型メモリlsi |
US6434736B1 (en) | 1999-07-08 | 2002-08-13 | Intel Corporation | Location based timing scheme in memory design |
US6401213B1 (en) * | 1999-07-09 | 2002-06-04 | Micron Technology, Inc. | Timing circuit for high speed memory |
US6477592B1 (en) | 1999-08-06 | 2002-11-05 | Integrated Memory Logic, Inc. | System for I/O interfacing for semiconductor chip utilizing addition of reference element to each data element in first data stream and interpret to recover data elements of second data stream |
US6629220B1 (en) | 1999-08-20 | 2003-09-30 | Intel Corporation | Method and apparatus for dynamic arbitration between a first queue and a second queue based on a high priority transaction type |
US6493803B1 (en) | 1999-08-23 | 2002-12-10 | Advanced Micro Devices, Inc. | Direct memory access controller with channel width configurability support |
US6552564B1 (en) * | 1999-08-30 | 2003-04-22 | Micron Technology, Inc. | Technique to reduce reflections and ringing on CMOS interconnections |
US6539490B1 (en) * | 1999-08-30 | 2003-03-25 | Micron Technology, Inc. | Clock distribution without clock delay or skew |
US6307769B1 (en) | 1999-09-02 | 2001-10-23 | Micron Technology, Inc. | Semiconductor devices having mirrored terminal arrangements, devices including same, and methods of testing such semiconductor devices |
US6594713B1 (en) | 1999-09-10 | 2003-07-15 | Texas Instruments Incorporated | Hub interface unit and application unit interfaces for expanded direct memory access processor |
US6438668B1 (en) | 1999-09-30 | 2002-08-20 | Apple Computer, Inc. | Method and apparatus for reducing power consumption in a digital processing system |
US6467013B1 (en) | 1999-09-30 | 2002-10-15 | Intel Corporation | Memory transceiver to couple an additional memory channel to an existing memory channel |
US6636912B2 (en) | 1999-10-07 | 2003-10-21 | Intel Corporation | Method and apparatus for mode selection in a computer system |
US6421744B1 (en) | 1999-10-25 | 2002-07-16 | Motorola, Inc. | Direct memory access controller and method therefor |
KR100319292B1 (ko) | 1999-12-02 | 2002-01-05 | 윤종용 | 빠른 부팅 속도를 갖는 컴퓨터 시스템 및 그 방법 |
US6501471B1 (en) | 1999-12-13 | 2002-12-31 | Intel Corporation | Volume rendering |
JP3546788B2 (ja) * | 1999-12-20 | 2004-07-28 | 日本電気株式会社 | メモリ制御回路 |
JP3356747B2 (ja) | 1999-12-22 | 2002-12-16 | エヌイーシーマイクロシステム株式会社 | 半導体記憶装置 |
US6628294B1 (en) | 1999-12-31 | 2003-09-30 | Intel Corporation | Prefetching of virtual-to-physical address translation for display data |
KR100343383B1 (ko) * | 2000-01-05 | 2002-07-15 | 윤종용 | 반도체 메모리 장치 및 이 장치의 데이터 샘플링 방법 |
JP2001193639A (ja) * | 2000-01-11 | 2001-07-17 | Toyota Autom Loom Works Ltd | 電動斜板圧縮機 |
US6745275B2 (en) * | 2000-01-25 | 2004-06-01 | Via Technologies, Inc. | Feedback system for accomodating different memory module loading |
US6823023B1 (en) | 2000-01-31 | 2004-11-23 | Intel Corporation | Serial bus communication system |
US6185352B1 (en) | 2000-02-24 | 2001-02-06 | Siecor Operations, Llc | Optical fiber ribbon fan-out cables |
JP2001265539A (ja) | 2000-03-16 | 2001-09-28 | Fuji Xerox Co Ltd | アレイ型記憶装置及び情報処理システム |
JP2001274323A (ja) * | 2000-03-24 | 2001-10-05 | Hitachi Ltd | 半導体装置とそれを搭載した半導体モジュール、および半導体装置の製造方法 |
US6728800B1 (en) * | 2000-06-28 | 2004-04-27 | Intel Corporation | Efficient performance based scheduling mechanism for handling multiple TLB operations |
US6594722B1 (en) | 2000-06-29 | 2003-07-15 | Intel Corporation | Mechanism for managing multiple out-of-order packet streams in a PCI host bridge |
US6799268B1 (en) | 2000-06-30 | 2004-09-28 | Intel Corporation | Branch ordering buffer |
JP2002014875A (ja) | 2000-06-30 | 2002-01-18 | Mitsubishi Electric Corp | 半導体集積回路、半導体集積回路のメモリリペア方法およびその方法をコンピュータに実行させるプログラムを記録したコンピュータ読み取り可能な記録媒体 |
US6754812B1 (en) * | 2000-07-06 | 2004-06-22 | Intel Corporation | Hardware predication for conditional instruction path branching |
US6816947B1 (en) | 2000-07-20 | 2004-11-09 | Silicon Graphics, Inc. | System and method for memory arbitration |
US6845409B1 (en) * | 2000-07-25 | 2005-01-18 | Sun Microsystems, Inc. | Data exchange methods for a switch which selectively forms a communication channel between a processing unit and multiple devices |
US6625687B1 (en) * | 2000-09-18 | 2003-09-23 | Intel Corporation | Memory module employing a junction circuit for point-to-point connection isolation, voltage translation, data synchronization, and multiplexing/demultiplexing |
US6453393B1 (en) | 2000-09-18 | 2002-09-17 | Intel Corporation | Method and apparatus for interfacing to a computer memory |
US6526483B1 (en) * | 2000-09-20 | 2003-02-25 | Broadcom Corporation | Page open hint in transactions |
US6523093B1 (en) * | 2000-09-29 | 2003-02-18 | Intel Corporation | Prefetch buffer allocation and filtering system |
US6523092B1 (en) * | 2000-09-29 | 2003-02-18 | Intel Corporation | Cache line replacement policy enhancement to avoid memory page thrashing |
US6859208B1 (en) | 2000-09-29 | 2005-02-22 | Intel Corporation | Shared translation address caching |
US6658509B1 (en) | 2000-10-03 | 2003-12-02 | Intel Corporation | Multi-tier point-to-point ring memory interface |
US7187742B1 (en) * | 2000-10-06 | 2007-03-06 | Xilinx, Inc. | Synchronized multi-output digital clock manager |
US6792059B2 (en) | 2000-11-30 | 2004-09-14 | Trw Inc. | Early/on-time/late gate bit synchronizer |
US6631440B2 (en) | 2000-11-30 | 2003-10-07 | Hewlett-Packard Development Company | Method and apparatus for scheduling memory calibrations based on transactions |
US6807630B2 (en) | 2000-12-15 | 2004-10-19 | International Business Machines Corporation | Method for fast reinitialization wherein a saved system image of an operating system is transferred into a primary memory from a secondary memory |
US6801994B2 (en) | 2000-12-20 | 2004-10-05 | Microsoft Corporation | Software management systems and methods for automotive computing devices |
US6622227B2 (en) * | 2000-12-27 | 2003-09-16 | Intel Corporation | Method and apparatus for utilizing write buffers in memory control/interface |
US6751703B2 (en) * | 2000-12-27 | 2004-06-15 | Emc Corporation | Data storage systems and methods which utilize an on-board cache |
US6493250B2 (en) * | 2000-12-28 | 2002-12-10 | Intel Corporation | Multi-tier point-to-point buffered memory interface |
US6889304B2 (en) * | 2001-02-28 | 2005-05-03 | Rambus Inc. | Memory device supporting a dynamically configurable core organization |
DE10110469A1 (de) | 2001-03-05 | 2002-09-26 | Infineon Technologies Ag | Integrierter Speicher und Verfahren zum Testen und Reparieren desselben |
US6782435B2 (en) | 2001-03-26 | 2004-08-24 | Intel Corporation | Device for spatially and temporally reordering for data between a processor, memory and peripherals |
US6904499B2 (en) | 2001-03-30 | 2005-06-07 | Intel Corporation | Controlling cache memory in external chipset using processor |
US7107399B2 (en) | 2001-05-11 | 2006-09-12 | International Business Machines Corporation | Scalable memory |
US6670959B2 (en) * | 2001-05-18 | 2003-12-30 | Sun Microsystems, Inc. | Method and apparatus for reducing inefficiencies in shared memory devices |
SE524110C2 (sv) | 2001-06-06 | 2004-06-29 | Kvaser Consultant Ab | Anordning och förfarande vid system med lokalt utplacerade modulenheter samt kontaktenhet för anslutning av sådan modulenhet |
US6697926B2 (en) | 2001-06-06 | 2004-02-24 | Micron Technology, Inc. | Method and apparatus for determining actual write latency and accurately aligning the start of data capture with the arrival of data at a memory device |
US6920533B2 (en) * | 2001-06-27 | 2005-07-19 | Intel Corporation | System boot time reduction method |
US20030005344A1 (en) * | 2001-06-29 | 2003-01-02 | Bhamidipati Sriram M. | Synchronizing data with a capture pulse and synchronizer |
US6721195B2 (en) * | 2001-07-12 | 2004-04-13 | Micron Technology, Inc. | Reversed memory module socket and motherboard incorporating same |
US6665498B1 (en) | 2001-07-20 | 2003-12-16 | Wenbin Jiang | High-speed optical data links |
US6792496B2 (en) | 2001-08-02 | 2004-09-14 | Intel Corporation | Prefetching data for peripheral component interconnect devices |
US6904556B2 (en) | 2001-08-09 | 2005-06-07 | Emc Corporation | Systems and methods which utilize parity sets |
US6681292B2 (en) * | 2001-08-27 | 2004-01-20 | Intel Corporation | Distributed read and write caching implementation for optimized input/output applications |
DE60211921T2 (de) | 2001-08-29 | 2006-10-05 | Analog Devices Inc., Norwood | Architektur und system von einem generischen seriellen port |
US7941056B2 (en) * | 2001-08-30 | 2011-05-10 | Micron Technology, Inc. | Optical interconnect in high-speed memory systems |
US6665202B2 (en) | 2001-09-25 | 2003-12-16 | Integrated Device Technology, Inc. | Content addressable memory (CAM) devices that can identify highest priority matches in non-sectored CAM arrays and methods of operating same |
US6718440B2 (en) * | 2001-09-28 | 2004-04-06 | Intel Corporation | Memory access latency hiding with hint buffer |
DE10153657C2 (de) * | 2001-10-31 | 2003-11-06 | Infineon Technologies Ag | Anordnung zur Datenübertragung in einem Halbleiterspeichersystem und Datenübertragungsverfahren dafür |
US6886048B2 (en) * | 2001-11-15 | 2005-04-26 | Hewlett-Packard Development Company, L.P. | Techniques for processing out-of-order requests in a processor-based system |
US6646929B1 (en) | 2001-12-05 | 2003-11-11 | Lsi Logic Corporation | Methods and structure for read data synchronization with minimal latency |
KR100454123B1 (ko) | 2001-12-06 | 2004-10-26 | 삼성전자주식회사 | 반도체 집적 회로 장치 및 그것을 구비한 모듈 |
US6775747B2 (en) | 2002-01-03 | 2004-08-10 | Intel Corporation | System and method for performing page table walks on speculative software prefetch operations |
US6804764B2 (en) | 2002-01-22 | 2004-10-12 | Mircron Technology, Inc. | Write clock and data window tuning based on rank select |
US6670833B2 (en) * | 2002-01-23 | 2003-12-30 | Intel Corporation | Multiple VCO phase lock loop architecture |
US7006533B2 (en) | 2002-02-19 | 2006-02-28 | Intel Corporation | Method and apparatus for hublink read return streaming |
US6912612B2 (en) | 2002-02-25 | 2005-06-28 | Intel Corporation | Shared bypass bus structure |
US6774687B2 (en) | 2002-03-11 | 2004-08-10 | Micron Technology, Inc. | Method and apparatus for characterizing a delay locked loop |
US6795899B2 (en) | 2002-03-22 | 2004-09-21 | Intel Corporation | Memory system with burst length shorter than prefetch length |
US6735682B2 (en) * | 2002-03-28 | 2004-05-11 | Intel Corporation | Apparatus and method for address calculation |
US7110400B2 (en) | 2002-04-10 | 2006-09-19 | Integrated Device Technology, Inc. | Random access memory architecture and serial interface with continuous packet handling capability |
US20030217223A1 (en) | 2002-05-14 | 2003-11-20 | Infineon Technologies North America Corp. | Combined command set |
US7133972B2 (en) | 2002-06-07 | 2006-11-07 | Micron Technology, Inc. | Memory hub with internal cache and/or memory access prediction |
US6731548B2 (en) | 2002-06-07 | 2004-05-04 | Micron Technology, Inc. | Reduced power registered memory module and method |
US6898674B2 (en) | 2002-06-11 | 2005-05-24 | Intel Corporation | Apparatus, method, and system for synchronizing information prefetch between processors and memory controllers |
DE10234934A1 (de) * | 2002-07-31 | 2004-03-18 | Advanced Micro Devices, Inc., Sunnyvale | Antwortreihenwiederherstellungsmechanismus |
US7117316B2 (en) * | 2002-08-05 | 2006-10-03 | Micron Technology, Inc. | Memory hub and access method having internal row caching |
US7149874B2 (en) | 2002-08-16 | 2006-12-12 | Micron Technology, Inc. | Memory hub bypass circuit and method |
US6820181B2 (en) * | 2002-08-29 | 2004-11-16 | Micron Technology, Inc. | Method and system for controlling memory accesses to memory modules having a memory hub architecture |
US7836252B2 (en) | 2002-08-29 | 2010-11-16 | Micron Technology, Inc. | System and method for optimizing interconnections of memory devices in a multichip module |
US6667926B1 (en) * | 2002-09-09 | 2003-12-23 | Silicon Integrated Systems Corporation | Memory read/write arbitration method |
US7102907B2 (en) * | 2002-09-09 | 2006-09-05 | Micron Technology, Inc. | Wavelength division multiplexed memory module, memory system and method |
US6821029B1 (en) | 2002-09-10 | 2004-11-23 | Xilinx, Inc. | High speed serial I/O technology using an optical link |
US6811320B1 (en) | 2002-11-13 | 2004-11-02 | Russell Mistretta Abbott | System for connecting a fiber optic cable to an electronic device |
DE10255937B4 (de) * | 2002-11-29 | 2005-03-17 | Advanced Micro Devices, Inc., Sunnyvale | Ordnungsregelgesteuerte Befehlsspeicherung |
US6978351B2 (en) | 2002-12-30 | 2005-12-20 | Intel Corporation | Method and system to improve prefetching operations |
US7366423B2 (en) | 2002-12-31 | 2008-04-29 | Intel Corporation | System having multiple agents on optical and electrical bus |
US6961259B2 (en) | 2003-01-23 | 2005-11-01 | Micron Technology, Inc. | Apparatus and methods for optically-coupled memory systems |
JP3841762B2 (ja) * | 2003-02-18 | 2006-11-01 | ファナック株式会社 | サーボモータ制御システム |
US7020757B2 (en) * | 2003-03-27 | 2006-03-28 | Hewlett-Packard Development Company, L.P. | Providing an arrangement of memory devices to enable high-speed data access |
US7366854B2 (en) * | 2003-05-08 | 2008-04-29 | Hewlett-Packard Development Company, L.P. | Systems and methods for scheduling memory requests utilizing multi-level arbitration |
US20050166006A1 (en) | 2003-05-13 | 2005-07-28 | Advanced Micro Devices, Inc. | System including a host connected serially in a chain to one or more memory modules that include a cache |
US7386768B2 (en) * | 2003-06-05 | 2008-06-10 | Intel Corporation | Memory channel with bit lane fail-over |
US6937076B2 (en) | 2003-06-11 | 2005-08-30 | Micron Technology, Inc. | Clock synchronizing apparatus and method using frequency dependent variable delay |
US20050015426A1 (en) | 2003-07-14 | 2005-01-20 | Woodruff Robert J. | Communicating data over a communication link |
US7174432B2 (en) | 2003-08-19 | 2007-02-06 | Nvidia Corporation | Asynchronous, independent and multiple process shared memory system in an adaptive computing architecture |
US7133991B2 (en) | 2003-08-20 | 2006-11-07 | Micron Technology, Inc. | Method and system for capturing and bypassing memory transactions in a hub-based memory system |
US7136958B2 (en) | 2003-08-28 | 2006-11-14 | Micron Technology, Inc. | Multiple processor system and method including multiple memory hub modules |
US7120743B2 (en) | 2003-10-20 | 2006-10-10 | Micron Technology, Inc. | Arbitration system and method for memory responses in a hub-based memory system |
US7177211B2 (en) * | 2003-11-13 | 2007-02-13 | Intel Corporation | Memory channel test fixture and method |
US7098714B2 (en) | 2003-12-08 | 2006-08-29 | Micron Technology, Inc. | Centralizing the lock point of a synchronous circuit |
US7529800B2 (en) | 2003-12-18 | 2009-05-05 | International Business Machines Corporation | Queuing of conflicted remotely received transactions |
US7181584B2 (en) * | 2004-02-05 | 2007-02-20 | Micron Technology, Inc. | Dynamic command and/or address mirroring system and method for memory modules |
US7788451B2 (en) | 2004-02-05 | 2010-08-31 | Micron Technology, Inc. | Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system |
US7412574B2 (en) | 2004-02-05 | 2008-08-12 | Micron Technology, Inc. | System and method for arbitration of memory responses in a hub-based memory system |
US7257683B2 (en) | 2004-03-24 | 2007-08-14 | Micron Technology, Inc. | Memory arbitration system and method having an arbitration packet protocol |
US7447240B2 (en) | 2004-03-29 | 2008-11-04 | Micron Technology, Inc. | Method and system for synchronizing communications links in a hub-based memory system |
US6980042B2 (en) | 2004-04-05 | 2005-12-27 | Micron Technology, Inc. | Delay line synchronizer apparatus and method |
US7046060B1 (en) | 2004-10-27 | 2006-05-16 | Infineon Technologies, Ag | Method and apparatus compensating for frequency drift in a delay locked loop |
-
2004
- 2004-05-28 US US10/857,467 patent/US7363419B2/en active Active
-
2005
- 2005-05-27 JP JP2007515399A patent/JP4524310B2/ja active Active
- 2005-05-27 WO PCT/US2005/018783 patent/WO2005119457A2/en active Application Filing
- 2005-05-27 EP EP20120194033 patent/EP2562653B1/en active Active
- 2005-05-27 EP EP05760644.4A patent/EP1769361B1/en active Active
- 2005-05-27 KR KR1020067027684A patent/KR100947755B1/ko active IP Right Grant
- 2005-05-30 TW TW094117699A patent/TWI341973B/zh active
-
2007
- 2007-08-27 US US11/895,894 patent/US7774559B2/en not_active Expired - Lifetime
-
2010
- 2010-04-14 JP JP2010092895A patent/JP5238747B2/ja active Active
Also Published As
Publication number | Publication date |
---|---|
US20050268060A1 (en) | 2005-12-01 |
TW200619929A (en) | 2006-06-16 |
EP1769361A2 (en) | 2007-04-04 |
KR20070024669A (ko) | 2007-03-02 |
EP2562653A2 (en) | 2013-02-27 |
EP1769361B1 (en) | 2014-01-15 |
EP2562653B1 (en) | 2015-05-13 |
US7774559B2 (en) | 2010-08-10 |
EP1769361A4 (en) | 2009-12-02 |
TWI341973B (en) | 2011-05-11 |
EP2562653A3 (en) | 2013-03-06 |
WO2005119457A2 (en) | 2005-12-15 |
US7363419B2 (en) | 2008-04-22 |
KR100947755B1 (ko) | 2010-03-18 |
JP2010157270A (ja) | 2010-07-15 |
US20070300023A1 (en) | 2007-12-27 |
JP2008501194A (ja) | 2008-01-17 |
JP5238747B2 (ja) | 2013-07-17 |
WO2005119457A3 (en) | 2007-06-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4524310B2 (ja) | ハブベースのメモリシステムにおける書込みコマンドを終了させる方法とシステム | |
EP2565794B1 (en) | Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system | |
JP4586031B2 (ja) | パケットメモリを有するアービトレーションシステムとハブに基づくメモリシステムにおけるメモリ応答の方法 | |
US7120743B2 (en) | Arbitration system and method for memory responses in a hub-based memory system | |
EP1646925B1 (en) | Apparatus and method for direct memory access in a hub-based memory system | |
US7415567B2 (en) | Memory hub bypass circuit and method | |
US20060083043A1 (en) | Memory system topology | |
US20090119429A1 (en) | Semiconductor integrated circuit |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20100113 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100115 |
|
RD13 | Notification of appointment of power of sub attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7433 Effective date: 20100204 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20100204 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100414 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20100514 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20100531 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 4524310 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130604 Year of fee payment: 3 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |