JP4521383B2 - 伸張−圧縮境界またはその付近におけるコンタクトの短絡の低減 - Google Patents
伸張−圧縮境界またはその付近におけるコンタクトの短絡の低減 Download PDFInfo
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- JP4521383B2 JP4521383B2 JP2006231300A JP2006231300A JP4521383B2 JP 4521383 B2 JP4521383 B2 JP 4521383B2 JP 2006231300 A JP2006231300 A JP 2006231300A JP 2006231300 A JP2006231300 A JP 2006231300A JP 4521383 B2 JP4521383 B2 JP 4521383B2
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- 238000007906 compression Methods 0.000 title description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 8
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- 230000006835 compression Effects 0.000 description 14
- 238000000034 method Methods 0.000 description 11
- 230000009977 dual effect Effects 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 7
- 238000001020 plasma etching Methods 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
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- 239000011800 void material Substances 0.000 description 2
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- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
尚、デュアルストレスライナーに関連する技術として、第1ストレスライナーと第2ストレスライナーのオーバーラップ部分以外でコンタクトを形成する技術が開発されている(例えば特許文献1、非特許文献1参照)。
(1)請求項1について、前記第1及び第2の各導電性プラグのエッジは、前記境界に存在し、前記境界に沿って延在している。
(2)請求項1について、前記第1及び第2の導電性プラグは、相互に異なる電位である。
(3)請求項1について、前記圧縮性応力層及び前記伸張性応力層は、前記境界において相互にオーバーラップしている。
(4)請求項1について、前記第1の導電性プラグは前記圧縮性応力層を通って完全に延在し、前記第2の導電性プラグは前記伸張性応力層を通って完全に延在している。
(5)請求項2について、前記境界の前記第1及び第2の部分は互いに平行であり、前記境界の第3の部分は前記境界の前記第1及び第2の部分と直交している。
(6)請求項2について、前記第1の導電性プラグのエッジは、前記境界の前記第1の部分に位置し、前記境界の前記第1の部分に沿って延在し、前記第2の導電性プラグのエッジは、前記境界の前記第2の部分に位置し、前記境界の前記第2の部分に沿って延在している。
(7)請求項2について、さらに、前記第1の導電性プラグに電気的に接続されている共通の第1のゲートを共有する第1のPFET及び第1のNFETと、前記第2の導電性プラグに電気的に接続されている共通の第2のゲートを共有する第2のPFET及び第2のNFETとを具備し、前記圧縮性応力層は前記第1及び第2のPFET上に配置され、前記伸張性応力層は前記第1及び第2のNFET上に配置されている。
(8)請求項2について、前記第1及び第2の導電性プラグは、相互に異なる電位を与えられる。
(9)請求項2について、前記圧縮性応力層及び前記伸張性応力層は、前記境界において互いにオーバーラップしている。
(10)請求項2について、前記圧縮性応力層と前記シリコン層との間と、前記伸張性応力層と前記シリコン層との間に配置され、前記境界を横切って延在し、前記第1の導電性プラグに電気的に接続されている第1のポリシリコン層と、前記第1のポリシリコン層から物理的に分離され、前記圧縮性応力層と前記シリコン層との間と、前記伸張性応力層と前記シリコン層との間に配置され、前記境界を横切って延在し、前記第2の導電性プラグに電気的に接続されている第2のポリシリコン層とをさらに含んでいる。
(11)請求項4について、前記第1の導電性プラグは、前記伸張性応力層に接触せず、前記第2の導電性プラグは、前記圧縮性応力層に接触しない。
(12)請求項4について、前記第1及び第2の各導電性プラグのエッジは前記境界に位置し、前記境界に沿って延在している。
(13)請求項4について、前記第1及び第2の導電性プラグは、相互に異なる電位を与えられる。
(14)請求項4について、前記圧縮性応力層及び前記伸張性応力層は、前記境界において相互にオーバーラップしている。
(15)請求項4について、前記第1の導電性プラグは、前記圧縮性応力層を通して完全に延在し、前記第2の導電性プラグは、前記伸張性応力層を通して完全に延在している。
Claims (2)
- 第1導電型の第1のウェル領域、及び第2導電型の第2のウェル領域が形成されたシリコン層と、
前記シリコン層の第1のウェル領域上に配置されている圧縮性応力層と、
前記シリコン層の第2のウェル領域上に配置され、境界において前記圧縮性応力層と接触している伸張性応力層と、
前記境界は、圧縮性応力層側にオフセットされている第1の部分と、前記伸張性応力層側にオフセットされている第2の部分と、前記第1、第2の部分と直交し、前記第1及び第2の部分を接続する第3の部分とからなり、
前記第1、第2のウェル領域上で、前記第1の部分に直交して配置された第1のゲートと、
前記第1、第2のウェル領域上で、前記第2の部分に直交して配置された第2のゲートと、
前記伸張性応力層を貫通し、前記境界の第3の部分の第1の側方に配置され、前記第1のゲートに接続される第1の導電性プラグと、
前記圧縮性応力層を貫通し、前記境界の第3の部分の前記第1の側方と反対側の第2の側方に配置され、前記第2のゲートに接続される第2の導電性プラグとを有している半導体装置。 - 前記第1の導電性プラグも前記圧縮性応力層を貫通し、前記第2の導電性プラグも前記伸張性応力層を貫通している請求項1記載の半導体装置。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/211,604 US7514752B2 (en) | 2005-08-26 | 2005-08-26 | Reduction of short-circuiting between contacts at or near a tensile-compressive boundary |
Publications (2)
Publication Number | Publication Date |
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JP2007088452A JP2007088452A (ja) | 2007-04-05 |
JP4521383B2 true JP4521383B2 (ja) | 2010-08-11 |
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JP2006231300A Expired - Fee Related JP4521383B2 (ja) | 2005-08-26 | 2006-08-28 | 伸張−圧縮境界またはその付近におけるコンタクトの短絡の低減 |
Country Status (2)
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US (1) | US7514752B2 (ja) |
JP (1) | JP4521383B2 (ja) |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070069307A1 (en) * | 2005-09-27 | 2007-03-29 | Kentaro Eda | Semiconductor device and method of manufacturing the same |
JP4765598B2 (ja) * | 2005-12-08 | 2011-09-07 | ソニー株式会社 | 半導体装置の製造方法 |
US7511360B2 (en) * | 2005-12-14 | 2009-03-31 | Freescale Semiconductor, Inc. | Semiconductor device having stressors and method for forming |
JP4764160B2 (ja) * | 2005-12-21 | 2011-08-31 | 株式会社東芝 | 半導体装置 |
JP4899085B2 (ja) * | 2006-03-03 | 2012-03-21 | 富士通セミコンダクター株式会社 | 半導体装置およびその製造方法 |
US7439120B2 (en) * | 2006-08-11 | 2008-10-21 | Advanced Micro Devices, Inc. | Method for fabricating stress enhanced MOS circuits |
US7416931B2 (en) * | 2006-08-22 | 2008-08-26 | Advanced Micro Devices, Inc. | Methods for fabricating a stress enhanced MOS circuit |
US7442601B2 (en) * | 2006-09-18 | 2008-10-28 | Advanced Micro Devices, Inc. | Stress enhanced CMOS circuits and methods for their fabrication |
US7633103B2 (en) * | 2007-08-28 | 2009-12-15 | Globalfoundries Inc. | Semiconductor device and methods for fabricating same |
JP2009105279A (ja) * | 2007-10-24 | 2009-05-14 | Fujitsu Microelectronics Ltd | 半導体装置の製造方法及び半導体装置 |
US7895548B2 (en) * | 2007-10-26 | 2011-02-22 | Synopsys, Inc. | Filler cells for design optimization in a place-and-route system |
US9472423B2 (en) * | 2007-10-30 | 2016-10-18 | Synopsys, Inc. | Method for suppressing lattice defects in a semiconductor substrate |
JP5389352B2 (ja) | 2007-12-06 | 2014-01-15 | ローム株式会社 | 半導体装置 |
JP2009188330A (ja) * | 2008-02-08 | 2009-08-20 | Fujitsu Microelectronics Ltd | 半導体装置およびその製造方法 |
JP5264834B2 (ja) | 2010-06-29 | 2013-08-14 | 東京エレクトロン株式会社 | エッチング方法及び装置、半導体装置の製造方法 |
US8859357B2 (en) * | 2010-11-03 | 2014-10-14 | Texas Instruments Incorporated | Method for improving device performance using dual stress liner boundary |
JP2013069863A (ja) * | 2011-09-22 | 2013-04-18 | Elpida Memory Inc | 半導体装置 |
US9589833B1 (en) | 2015-09-10 | 2017-03-07 | International Business Machines Corporation | Preventing leakage inside air-gap spacer during contact formation |
US10854604B1 (en) * | 2019-09-20 | 2020-12-01 | Qualcomm Incorporated | Offset gate contact |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2003086708A (ja) * | 2000-12-08 | 2003-03-20 | Hitachi Ltd | 半導体装置及びその製造方法 |
JP2003273240A (ja) * | 2002-03-19 | 2003-09-26 | Hitachi Ltd | 半導体装置及びその製造方法 |
JP2004023047A (ja) * | 2002-06-20 | 2004-01-22 | Renesas Technology Corp | 半導体装置 |
JP2004327540A (ja) * | 2003-04-22 | 2004-11-18 | Seiko Epson Corp | 半導体装置及びその製造方法 |
JP2006324278A (ja) * | 2005-05-17 | 2006-11-30 | Sony Corp | 半導体装置およびその製造方法 |
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2005
- 2005-08-26 US US11/211,604 patent/US7514752B2/en not_active Expired - Fee Related
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2006
- 2006-08-28 JP JP2006231300A patent/JP4521383B2/ja not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2003086708A (ja) * | 2000-12-08 | 2003-03-20 | Hitachi Ltd | 半導体装置及びその製造方法 |
JP2003273240A (ja) * | 2002-03-19 | 2003-09-26 | Hitachi Ltd | 半導体装置及びその製造方法 |
JP2004023047A (ja) * | 2002-06-20 | 2004-01-22 | Renesas Technology Corp | 半導体装置 |
JP2004327540A (ja) * | 2003-04-22 | 2004-11-18 | Seiko Epson Corp | 半導体装置及びその製造方法 |
JP2006324278A (ja) * | 2005-05-17 | 2006-11-30 | Sony Corp | 半導体装置およびその製造方法 |
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US20070045747A1 (en) | 2007-03-01 |
US7514752B2 (en) | 2009-04-07 |
JP2007088452A (ja) | 2007-04-05 |
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