JP4504791B2 - 半導体回路装置及びその製造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims description 80
- 238000004519 manufacturing process Methods 0.000 title claims description 29
- 239000010410 layer Substances 0.000 claims description 50
- 238000005530 etching Methods 0.000 claims description 32
- 238000000034 method Methods 0.000 claims description 31
- 229910052751 metal Inorganic materials 0.000 claims description 25
- 239000002184 metal Substances 0.000 claims description 25
- 238000005520 cutting process Methods 0.000 claims description 22
- 239000012535 impurity Substances 0.000 claims description 17
- 239000011229 interlayer Substances 0.000 claims description 17
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 16
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 16
- 238000005229 chemical vapour deposition Methods 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000011521 glass Substances 0.000 claims description 4
- 238000009413 insulation Methods 0.000 claims description 4
- 230000001678 irradiating effect Effects 0.000 claims description 3
- 150000002739 metals Chemical class 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims 4
- 150000001875 compounds Chemical class 0.000 claims 2
- 239000012528 membrane Substances 0.000 claims 2
- 230000000903 blocking effect Effects 0.000 claims 1
- 239000010408 film Substances 0.000 description 199
- 238000002161 passivation Methods 0.000 description 28
- 230000008569 process Effects 0.000 description 17
- 239000000463 material Substances 0.000 description 13
- 230000015572 biosynthetic process Effects 0.000 description 11
- 229910000679 solder Inorganic materials 0.000 description 10
- 239000011248 coating agent Substances 0.000 description 8
- 238000000576 coating method Methods 0.000 description 8
- 230000007774 longterm Effects 0.000 description 6
- 238000000151 deposition Methods 0.000 description 5
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 4
- 230000002950 deficient Effects 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 239000011800 void material Substances 0.000 description 4
- 229910000838 Al alloy Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- 238000007689 inspection Methods 0.000 description 3
- 230000035515 penetration Effects 0.000 description 3
- 230000008439 repair process Effects 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 241000951471 Citrus junos Species 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000009616 inductively coupled plasma Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 150000002736 metal compounds Chemical class 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 229910001415 sodium ion Inorganic materials 0.000 description 1
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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Description
2 金属膜
3 配線層
3a ヒューズ部
3b 配線
3c パッド
5 パッシベーション膜
11 第1の絶縁膜
12 第2の絶縁膜
13 第3の絶縁膜
31 BCB膜(表面絶縁膜)
32 バリアメタル層
33 半田バンプ
41 ボイド
42 クラック
Claims (23)
- 回路構成変更のために、必要に応じて切断処理が行われるヒューズ部を備える半導体回路装置の製造方法において、
ヒューズ部が形成された配線層を有する層間絶縁膜を形成する工程(a)と、
前記層間絶縁膜上に形成された前記半導体回路装置の最上位の配線層を被覆するとともに、当該配線層に属する部材間の空間を隙間なく充填する第1の絶縁膜を形成する工程(b)と、
前記第1の絶縁膜に比べて高い気密性を有し、当該第1の絶縁膜を被覆する第2の絶縁膜を形成する工程(c)と、
前記ヒューズ部上に存在する前記第1の絶縁膜及び前記第2の絶縁膜をエッチングすることで開口部を形成する工程(d)と、
前記第2の絶縁膜と同等以上の気密性を有し、少なくとも前記開口部を被覆する第3の絶縁膜を形成する工程(e)と、
必要に応じて、前記第3の絶縁膜の上方からレーザまたは荷電ビームを照射してヒューズ部を切断する工程(f)と、
を有し、
前記工程(e)において形成される前記第3の絶縁膜の膜厚は、前記工程(c)において形成される前記第2の絶縁膜の膜厚よりも薄く、かつ
前記工程(d)における前記エッチング工程は、前記ヒューズ部上に、前記第1の絶縁膜の一部が残存するようなエッチング工程であることを特徴とする半導体回路装置の製造方法。 - 回路構成変更のために、必要に応じて切断処理が行われるヒューズ部を備える半導体回路装置の製造方法において、
ヒューズ部が形成された配線層を有する層間絶縁膜を形成する工程(a)と、
前記層間絶縁膜上に形成された前記半導体回路装置の最上位の配線層を被覆するとともに、当該配線層に属する部材間の空間を隙間なく充填する第1の絶縁膜を形成する工程(b)と、
前記第1の絶縁膜に比べて高い気密性を有し、当該第1の絶縁膜を被覆する第2の絶縁膜を形成する工程(c)と、
前記ヒューズ部上に存在する前記第1の絶縁膜及び前記第2の絶縁膜をエッチングすることで開口部を形成する工程(d)と、
前記第2の絶縁膜と同等以上の気密性を有し、少なくとも前記開口部を被覆する第3の絶縁膜を形成する工程(e)と、
必要に応じて、前記第3の絶縁膜の上方からレーザまたは荷電ビームを照射してヒューズ部を切断する工程(f)と、
を有し、
前記工程(e)において形成される前記第3の絶縁膜の膜厚は、前記工程(c)において形成される前記第2の絶縁膜の膜厚よりも薄く、かつ
前記工程(b)と前記工程(c)の間に、
少なくとも前記ヒューズ部上を被覆するように、エッチングストッパ膜を形成し、
その後、前記第1の絶縁膜をさらに形成する工程を有することを特徴とする半導体回路装置の製造方法。 - 前記第1の絶縁膜は、高密度プラズマを利用した化学気相成長法により堆積されたNSG(Non Doped Silicon Glass)膜であり、
前記エッチングストッパ膜は、シリコン窒化膜であることを特徴とする請求項2に記載の半導体回路装置の製造方法。 - 前記第1の絶縁膜が、高密度プラズマを利用した化学気相成長法により堆積されたNSG(Non Doped Silicon Glass)膜である請求項1または2に記載の半導体回路装置の製造方法。
- 前記第1の絶縁膜が、化学気相成長法により堆積されたシリコン窒化膜である請求項1または2に記載の半導体回路装置の製造方法。
- 前記第2の絶縁膜及び前記第3の絶縁膜は、前記第1の絶縁膜よりも水分または不純物の浸入に対する高い阻止能力を有することを特徴とする請求項1〜5のいずれか1項に記載の半導体回路装置の製造方法。
- 前記ヒューズ部が形成された配線層には、さらに配線が形成されていることを特徴とする請求項1〜6のいずれか1項に記載の半導体回路装置の製造方法。
- 前記ヒューズ部は、アルミニウムを有することを特徴とする請求項1〜7のいずれか1項に記載の半導体回路装置の製造方法。
- 前記ヒューズ部は、複数種類の金属からなることを特徴とする請求項1〜7のいずれか1項に記載の半導体回路装置の製造方法。
- 前記ヒューズ部は、アルミニウムを有する金属膜と前記金属膜の化合物からなることを特徴とする請求項1〜7のいずれか1項に記載の半導体回路装置の製造方法。
- 前記工程(f)の後に、前記第3の絶縁膜の上に表面絶縁膜を形成する工程(g)をさらに有することを特徴とする請求項1〜10のいずれか1項に記載の半導体回路装置の製造方法。
- 前記工程(e)の後工程(f)の前に、前記半導体回路装置が備える外部接続用電極上に外部接続用の開口部を形成する工程(h)をさらに有することを特徴とする請求項1〜10のいずれか1項に記載の半導体回路装置の製造方法。
- 回路構成変更のために、必要に応じて切断処理が行われるヒューズ部を備える半導体回路装置において、
ヒューズ部が形成された配線層を有する層間絶縁膜と、
前記層間絶縁膜上に形成された前記半導体回路装置を構成する最上位の配線層に属する部材間に存在する空間を隙間なく充填するとともに、当該配線層を被覆する第1の絶縁膜と、
前記第1の絶縁膜に比べて高い気密性を有し、当該第1の絶縁膜を被覆する第2の絶縁膜と、
前記ヒューズ部上に、前記第2の絶縁膜の上面から所定深さにわたって形成された開口部と、
前記第2の絶縁膜と同等以上の気密性を有し、少なくとも前記開口部を被覆するとともに、必要に応じて、上方からヒューズ部切断のためにレーザまたは荷電ビームが照射される第3の絶縁膜と、
を備え、
前記開口部以外の領域において、前記第3の絶縁膜の膜厚は前記第2の絶縁膜の膜厚と比較して薄く、かつ
前記ヒューズ部上に、前記第1の絶縁膜の一部が残存していることを特徴とする半導体回路装置。 - 回路構成変更のために、必要に応じて切断処理が行われるヒューズ部を備える半導体回路装置において、
ヒューズ部が形成された配線層を有する層間絶縁膜と、
前記層間絶縁膜上に形成された前記半導体回路装置を構成する最上位の配線層に属する部材間に存在する空間を隙間なく充填するとともに、当該配線層を被覆する第1の絶縁膜と、
前記第1の絶縁膜に比べて高い気密性を有し、当該第1の絶縁膜を被覆する第2の絶縁膜と、
前記ヒューズ部上に、前記第2の絶縁膜の上面から所定深さにわたって形成された開口部と、
前記第2の絶縁膜と同等以上の気密性を有し、少なくとも前記開口部を被覆するとともに、必要に応じて、上方からヒューズ部切断のためにレーザまたは荷電ビームが照射される第3の絶縁膜と、
を備え、
前記開口部以外の領域において、前記第3の絶縁膜の膜厚は前記第2の絶縁膜の膜厚と比較して薄く、かつ
少なくとも前記ヒューズ部上に、エッチングストッパ膜が形成されていることを特徴とする半導体回路装置。 - 少なくとも前記ヒューズ部上に、エッチングストッパ膜が形成されていることを特徴とする請求項13に記載の半導体回路装置。
- 前記エッチングストッパ膜は、シリコン窒化膜であることを特徴とする請求項14または15に記載の半導体回路装置。
- 前記第2の絶縁膜はシリコン窒化膜であることを特徴とする請求項13〜16のいずれか1項に記載の半導体回路装置。
- 前記第3の絶縁膜はシリコン窒化膜であることを特徴とする請求項13〜17のいずれか1項に記載の半導体回路装置。
- 前記第3の絶縁膜の上に表面絶縁膜が形成されていることを特徴とする請求項13〜18のいずれか1項に記載の半導体回路装置。
- 前記ヒューズ部が形成された配線層には、さらに配線が形成されていることを特徴とする請求項13〜19のいずれか1項に記載の半導体回路装置。
- 前記ヒューズ部は、アルミニウムを有することを特徴とする請求項13〜19のいずれか1項に記載の半導体回路装置。
- 前記ヒューズ部は、複数種類の金属からなることを特徴とする請求項13〜19のいずれか1項に記載の半導体回路装置。
- 前記ヒューズ部は、アルミニウムを有する金属膜と前記金属膜の化合物からなることを特徴とする請求項13〜19のいずれか1項に記載の半導体回路装置。
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