JP4491587B2 - データ発生装置 - Google Patents
データ発生装置 Download PDFInfo
- Publication number
- JP4491587B2 JP4491587B2 JP2004342563A JP2004342563A JP4491587B2 JP 4491587 B2 JP4491587 B2 JP 4491587B2 JP 2004342563 A JP2004342563 A JP 2004342563A JP 2004342563 A JP2004342563 A JP 2004342563A JP 4491587 B2 JP4491587 B2 JP 4491587B2
- Authority
- JP
- Japan
- Prior art keywords
- data
- bit width
- parallel
- parallel data
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4009—Coupling between buses with data restructuring
- G06F13/4018—Coupling between buses with data restructuring with data-width conversion
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M9/00—Parallel/series conversion or vice versa
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- Analogue/Digital Conversion (AREA)
Description
18 並列データ発生回路
20 ビット幅調整回路
BWI 有効ビット幅識別信号
DCLK 第1クロック(分周クロック)
RCLK 第2クロック(基準クロック)
Claims (1)
- 有効ビット幅が選択的に変更される第1並列データを周波数が一定の第1クロックに従って供給すると共に、次に供給する上記第1並列データの有効ビット幅識別信号を供給する並列データ供給手段と、
上記第1並列データが書き込まれ、ビット幅が一定で有効なデータのみから構成される第2並列データを生成すると共に、上記有効ビット幅識別信号を受けて、次の上記第1並列データを受け入れ可能な容量に応じて、次の上記第1並列データの書き込みを制御するビット幅調整手段と、
上記第1クロックより高速な第2クロックに従って上記第2並列データを直列データに変換する並直列変換手段とを具えるデータ発生装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004342563A JP4491587B2 (ja) | 2004-11-26 | 2004-11-26 | データ発生装置 |
US11/264,985 US7890679B2 (en) | 2004-11-26 | 2005-11-01 | Data generator for generating data of arbitrary length |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004342563A JP4491587B2 (ja) | 2004-11-26 | 2004-11-26 | データ発生装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006153583A JP2006153583A (ja) | 2006-06-15 |
JP4491587B2 true JP4491587B2 (ja) | 2010-06-30 |
Family
ID=36632084
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004342563A Expired - Fee Related JP4491587B2 (ja) | 2004-11-26 | 2004-11-26 | データ発生装置 |
Country Status (2)
Country | Link |
---|---|
US (1) | US7890679B2 (ja) |
JP (1) | JP4491587B2 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8504745B1 (en) | 2009-04-02 | 2013-08-06 | Xilinx, Inc. | Method of and circuit for determining a shift pattern to generate an output data stream |
JP4743456B2 (ja) * | 2009-07-01 | 2011-08-10 | テクトロニクス・インターナショナル・セールス・ゲーエムベーハー | データ生成装置 |
JP2012257047A (ja) * | 2011-06-08 | 2012-12-27 | Fujitsu Ltd | パラレルシリアル変換回路、情報処理装置及び情報処理システム |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4839866A (en) * | 1987-05-29 | 1989-06-13 | Texas Instruments Incorporated | Cascadable first-in, first-out memory |
US4876685A (en) * | 1987-06-08 | 1989-10-24 | Teradyne, Inc. | Failure information processing in automatic memory tester |
JPS6490621A (en) * | 1987-09-30 | 1989-04-07 | Nec Corp | Decoder |
JP3051223B2 (ja) * | 1991-10-02 | 2000-06-12 | 富士通株式会社 | セル送信回路 |
JP3384838B2 (ja) * | 1992-06-29 | 2003-03-10 | シャープ株式会社 | インターフェース装置 |
US5388074A (en) * | 1992-12-17 | 1995-02-07 | Vlsi Technology, Inc. | FIFO memory using single output register |
US6032275A (en) * | 1996-01-12 | 2000-02-29 | Advantest Corp. | Test pattern generator |
US6087874A (en) * | 1997-12-23 | 2000-07-11 | Nortel Networks Corporation | Variable delay circuit for delaying logic signals, characterized by a delay time that is a linear function of a control voltage |
US6463092B1 (en) * | 1998-09-10 | 2002-10-08 | Silicon Image, Inc. | System and method for sending and receiving data signals over a clock signal line |
US6356158B1 (en) * | 2000-05-02 | 2002-03-12 | Xilinx, Inc. | Phase-locked loop employing programmable tapped-delay-line oscillator |
JP3888603B2 (ja) * | 2000-07-24 | 2007-03-07 | 株式会社ルネサステクノロジ | クロック生成回路および制御方法並びに半導体記憶装置 |
JP2002207692A (ja) | 2001-01-12 | 2002-07-26 | Ricoh Co Ltd | 画像データ転送装置、プリンタおよび画像データ転送システム |
JP3626105B2 (ja) * | 2001-03-05 | 2005-03-02 | Necマイクロシステム株式会社 | 疑似ランダム信号発生回路 |
US6658523B2 (en) * | 2001-03-13 | 2003-12-02 | Micron Technology, Inc. | System latency levelization for read data |
JP3577717B2 (ja) * | 2001-05-18 | 2004-10-13 | 日本電気株式会社 | 通信装置、スクランブラ回路とデスクランブラ回路、そのスクランブル方法とデスクランブル方法 |
-
2004
- 2004-11-26 JP JP2004342563A patent/JP4491587B2/ja not_active Expired - Fee Related
-
2005
- 2005-11-01 US US11/264,985 patent/US7890679B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2006153583A (ja) | 2006-06-15 |
US7890679B2 (en) | 2011-02-15 |
US20060155898A1 (en) | 2006-07-13 |
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