JP4450122B2 - Silicon carbide semiconductor device - Google Patents

Silicon carbide semiconductor device Download PDF

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JP4450122B2
JP4450122B2 JP32693399A JP32693399A JP4450122B2 JP 4450122 B2 JP4450122 B2 JP 4450122B2 JP 32693399 A JP32693399 A JP 32693399A JP 32693399 A JP32693399 A JP 32693399A JP 4450122 B2 JP4450122 B2 JP 4450122B2
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JP2001144292A (en
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クマール ラジェシュ
剛 山本
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Denso Corp
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Denso Corp
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H01L29/7828—Vertical transistors without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
    • H—ELECTRICITY
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • H—ELECTRICITY
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1608—Silicon carbide

Description

【０００１】
【発明の属する技術分野】
本発明は、パワーＭＯＳＦＥＴやＳＩＴ等の半導体装置及びその製造方法に関するもので、特に炭化珪素よりなる半導体装置に用いて好適である。
【０００２】
【従来の技術】
従来、ＭＯＳＦＥＴの高耐圧を維持するものとして、米国特許第５、４３８、２１５号明細書に提案されている構造がある。この構造を図８に示す。
【０００３】
図８に示すように、半導体基板１０１上にエピタキシャル成長させたｎ型エピ層１０２の表層部にｐ型ベース領域１０３が形成されていると共に、ｐ型ベース領域１０３内にｎ型ソース領域１０４が形成されている。そして、これらｎ型ソース領域１０４及びｐ型ベース領域１０３の下方には、ｎ型層１０５とｐ型層１０６とが交互に並べられて複数のＰＮ接合を構成したスーパージャンクションが形成されている。
【０００４】
このように構成されたスーパージャンクションＭＯＳＦＥＴ（Ｓ．Ｊ．ＭＯＳＦＥＴ）は、スーパージャンクションを構成する複数のＰＮ接合部において空乏層が伸び、スーパージャンクション部分をピンチオフさせることで、ＭＯＳＦＥＴの耐圧が得られるようになっている。
【０００５】
【発明が解決しようとする課題】
しかしながら、従来ではスーパージャンクションを構成する複数のＰＮ接合を、ｐ型ベース領域１０３やｎ型ソース領域１０４が形成される素子部にのみ選択的に形成するようにしているため、ＰＮ接合形成用マスクのマスクずれ等によってスーパージャンクションが正確に素子部に形成されない場合があり、ｐ型ベース領域１０３及びｎ型ソース領域１０４下を完全にピンチオフさせることができず、耐圧が確保できないという問題がある。
【０００６】
本発明は上記点に鑑みて、スーパージャンクションを構成する複数のＰＮ接合が素子部に確実に配置されるようにし、確実にＭＯＳＦＥＴの耐圧が得られるようにすることを目的とする。
【０００７】
【課題を解決するための手段】
上記目的を達成するため、請求項１に記載の発明では、半導体基板（１）の主表面（１ａ）上に形成され、該主表面上において複数の第１導電型層（２）と複数の第２導電型層（３）とが交互に配置されて形成された複数のＰＮ接合からなるスーパージャンクションを備え、スーパージャンクションを構成する第１導電型層及び第２導電型層は、半導体基板の主表面全面に形成されていることを特徴としている。
【０００８】
このように、スーパージャンクションが半導体基板の主表面全面に形成されていれば、マスクずれ等によってスーパージャンクションの形成位置がずれても、必ずベース領域やソース領域下にスーパージャンクションが形成されるため、確実にＭＯＳＦＥＴの耐圧を得ることができる。
【００１１】
さらに、請求項１に記載の発明においては、セル領域及びガードリング領域の全域においてスーパージャンクションを備え、該スーパージャンクションを構成する第１導電型層及び第２導電型層が繰り返し連続的につながるようにしている。
【００１２】
このように、セル領域を囲む外周部にガードリングを形成する場合には、ガードリング領域までスーパージャンクションを形成するようにしても、上記の効果を得ることができる。
【００１３】
請求項２に記載の発明は、請求項１に記載の半導体装置の製造方法である。具体的には、半導体基板の主表面上全面に第１導電型層を形成し、該第１導電型層に第２導電型不純物のイオン注入を行ったあと、該第２導電型不純物を活性化させて第２導電型層を形成することで、半導体基板の主表面全面に第１導電型層と第２導電型層を形成することができる。
【００１４】
この場合、第２導電型層を形成する工程において、第１導電型層のうち第２導電型不純物をイオン注入する領域に不活性なイオン種をイオン注入しておき、不活性なイオン種を注入したのち、第２導電型不純物を活性化させるようにすることができる。すなわち、不活性なイオン種によって炭素サイトの空孔を無くすことができるため、炭素サイトの空孔に基づく第２導電型不純物の拡散を抑制することができ、第１導電型層と第２導電型層の幅を正確に規定することができる。
【００１５】
なお、上記各手段の括弧内の符号は、後述する実施形態に記載の具体的手段との対応関係を示すものである。
【００１６】
【発明の実施の形態】
（第１実施形態）
図１に本発明の第１実施形態におけるスーパージャンクションＭＯＳＦＥＴを示す。この図は半導体装置の素子部を構成するＭＯＳＦＥＴの１ユニットセルを示したものであり、実際には複数のユニットセル若しくは他の回路素子と共に半導体装置を構成している。以下、図１に基づいて本実施形態におけるＭＯＳＦＥＴの構成について説明する。
【００１７】
図１に示すように、炭化珪素からなるｎ+ 型基板１は上面を主表面１ａとし、主表面１ａの反対面である下面を裏面１ｂとしている。このｎ+ 型基板１の主表面１ａの上の全面に、炭化珪素からなるｎ型層２とｐ型層３とが延設され、これらｎ型層２とｐ型層３とが交互に並べられて複数のＰＮ接合が形成されている。これら複数のＰＮ接合がスーパージャンクションを構成している。このスーパージャンクションを構成するＰＮ接合は、ｎ+型基板１の主表面１ａすべてに形成されている。すなわち、複数のユニットセル若しくは他の回路素子が形成される領域にもすべてスーパージャンクションが形成され、これらすべてのスーパージャンクションが断続せずに繰り返し連続的に繋がった状態となっている。
【００１８】
スーパージャンクションの複数のＰＮ接合を構成する各ｎ型層２とｐ型層３は、同等の厚さ３μｍで構成され、ｎ型層２の幅Ｗｎとｐ型層３の幅Ｗｐとは同等で１μｍとされている。また、ｎ型層２は不純物濃度が２×１０17ｃｍ-3程度とされており、ｐ型層３は不純物濃度が２×１０17ｃｍ-3程度とされている。
【００１９】
この濃度と幅は、Ｊｐｎ．Ｊ．Ａｐｐｌ．Ｐｈｙｓ．Ｖｏｌ．３６（１９９７）ｐｐ ６２５４−６２６２に記載されていた関係式を満たすように設定すればよい。
【００２０】
スーパージャンクションを構成する複数のＰＮ接合の上には、ｎ+型基板１よりも低い不純物濃度を有する炭化珪素からなるｎ- 型エピタキシャル層４が厚さ２μｍ程度で積層されている。このｎ- 型エピ層４の不純物濃度はｎ型層２の不純物濃度と同等となっている。
【００２１】
ｎ- 型エピ層４の表層部における所定領域には、所定深さを有するｐ型ベース領域５が形成されている。このｐ- 型ベース領域５はＢをドーパントとして形成されており、略１×１０17ｃｍ-3以上の濃度となっている。
【００２２】
また、ｐ型ベース領域５の表層部の所定領域には、該ベース領域５よりも浅いｎ+ 型ソース領域６が形成されている。
【００２３】
さらに、ｎ+ 型ソース領域６とｎ- 型エピ層２とを繋ぐように、ｐ型ベース領域５の表面部にはｎ- 型ＳｉＣ層７が延設されている。このｎ- 型ＳｉＣ層７は、エピタキシャル成長にて形成されたものであり、エピタキシャル膜の結晶が４Ｈ、６Ｈ、３Ｃ、１５Ｒのものを用いる。尚、このｎ- 型ＳｉＣ層７はデバイスの動作時にチャネル形成層として機能する。以下、ｎ- 型ＳｉＣ層７を表面チャネル層という。
【００２４】
表面チャネル層７はＮ（窒素）をドーパントに用いて形成されており、そのドーパント濃度は、例えば１×１０15ｃｍ-3〜１×１０17ｃｍ-3程度の低濃度で、かつ、ｎ- 型エピ層４及びｐ- 型ベース領域５のドーパント濃度以下となっている。これにより、低オン抵抗化が図られている。
【００２５】
表面チャネル層７の上面およびｎ+ 型ソース領域６の上面には熱酸化にてゲート酸化膜８が形成されている。さらに、ゲート酸化膜８の上にはゲート電極９が形成されている。
【００２６】
また、ｎ+ 型ソース領域６およびｐ型ベース領域５と接するようにソース電極１０が形成されている。また、ｎ+ 型基板１の裏面１ｂには、ドレイン電極１１が形成されている。
【００２７】
なお、ｐ型ベース領域５のうちソース電極１０とコンタクトが取られる部位の下方は、ｐ型ベース領域５の他の部分よりも接合深さが深くされたディープベース層５ａとなっている。このディープベース層５ａは、ｐ型ベース領域５の他の部分よりもｐ型不純物濃度が高くされており、逆バイアス時に優先的にアバランシェブレークダウンするようになっている。
【００２８】
そして、上記したスーパージャンクションを構成するＰＮ接合のうちのｐ型層３とｐ型ベース領域５とが図１とは別断面において、アース接続されている。
【００２９】
このように、各素子部のスーパージャンクションを断続させずに連続的に繋げた状態としているため、各素子部に確実にスーパージャンクションが備えられた状態となり、確実にｐ型ベース領域５及びｎ+型ソース領域６の下方をピンチオフさせることができ、確実にＭＯＳＦＥＴの耐圧が得られるようにできる。
【００３０】
上記構成のスーパージャンクションＭＯＳＦＥＴの耐圧及びオン抵抗特性について実験により調べた。その結果をそれぞれ図２（ａ）、（ｂ）に示す。
【００３１】
図２（ａ）に示されるように、逆バイアス時においてドレイン電極１１への印加電圧が１０３７Ｖのときにアバランシェブレークダウンが生じ、耐圧が得られるようになっている。
【００３２】
一方、図２（ｂ）に示すように、本実施形態におけるスーパージャンクションＭＯＳＦＥＴはスーパージャンクションを形成していないＭＯＳＦＥＴと比べてドレイン電流が大きくなっており、オン抵抗が低減されていることが判る。
【００３３】
これは、スーパージャンクションを形成することにより、この領域の不純物濃度を高濃度にすること、つまり低抵抗にすることができるため、オン抵抗を低減することができるのである。
【００３４】
このように、本実施形態によるスーパージャンクションＭＯＳＦＥＴにより、確実にＭＯＳＦＥＴの耐圧を得ることができると共に、ＭＯＳＦＥＴのオン抵抗を低減することができる。
【００３５】
次に、図１に示すＭＯＳＦＥＴの製造工程を、図３〜図６に基づいて説明する。
【００３６】
〔図３（ａ）に示す工程〕
まず、ｎ型４Ｈ、６Ｈ、３Ｃ、もしくは１５Ｒ−ＳｉＣ基板、すなわちｎ+ 型基板１を用意する。このｎ+ 型基板１は厚さが４００μｍであり、主表面１ａが（０００１）Ｓｉ面、又は、（１１２−０）ａ面となっている。
【００３７】
〔図３（ｂ）に示す工程〕
ｎ+型基板１の主表面１ａに、厚さ３μｍのｎ型層２をエピタキシャル成長させる。このとき、ｎ型層２は下地のｎ+型基板１と同様の結晶が得られ、ｎ型４Ｈ、６Ｈ、３Ｃもしくは１５Ｒ−ＳｉＣ層となる。
【００３８】
〔図３（ｃ）に示す工程〕
そして、ｎ型層２の表面にｐ型層形成予定領域が開口するマスクを配置し、ＢやＡｌ等のｐ型不純物をイオン注入したのち、ｐ型不純物を熱処理によって活性化させてｐ型層３を形成する。このとき、ｐ型層３をｎ+型基板１の全面（若しくは素子が形成されダイシングによって除去される不要部分とならない領域すべて）に形成する。
【００３９】
これにより、ｎ+型基板１の全面にｎ型層２とｐ型層３とが交互に並べられたスーパージャンクションが形成される。このため、このあとに形成する各素子部の形成時にマスクずれが生じても、各素子部のそれぞれに必ずスーパージャンクションが形成されていることになる。
【００４０】
またこのとき、ＢやＡｌを注入する前にＣ（炭素）等の不活性なイオン種を注入してもよい。このように、ｐ型不純物を活性化させる前にＣ等の不活性なイオン種を注入しておくことにより、エピタキシャル成長時等にｎ型層２に形成された炭素サイトの空孔内に不活性なイオン種が入り込み、ｎ型層２の炭素サイトの空孔をなくすことができるため、炭素サイトの空孔に起因するｐ型不純物の拡散が抑制され、ｎ型層２とｐ型層３との幅を正確に規定することができる。
【００４１】
〔図４（ａ）に示す工程〕
次に、スーパージャンクションを構成するｎ型層２とｐ型層３の上に、厚さ５μｍ程度のｎ-型エピ層４をエピタキシャル成長させる。このとき、ｎ-型エピ層４は下地のｎ型層２及びｐ型層３と同様の結晶が得られ、ｎ型４Ｈ、６Ｈ、３Ｃ、もしくは１５Ｒ−ＳｉＣ層となる。
【００４２】
〔図４（ｂ）に示す工程〕
ｎ- 型エピ層４の上の所定領域にＬＴＯ（Ｌｏｗ Ｔｅｍｐｅｒａｔｕｒｅ Ｏｘｉｄａｔｉｏｎ）膜２０を配置し、これをマスクとしてＢ若しくはＡｌ等のｐ型不純物のイオン注入を行う。このとき、イオン注入条件は、温度が７００℃、ドーズ量が１×１０16ｃｍ-2としている。これにより、ｎ- 型エピ層４の表面から所定深さの位置に、Ｂよりなるボックスプロファイルが形成される。
【００４３】
その後、熱処理として、１６００℃、３０分間の活性化アニールを施し、Ｂを活性化させてｐ型ベース領域５を形成する。
【００４４】
このとき、上記ｐ型層３の形成と同様に、ｐ型ベース領域５とする部分にＣ等の不活性なイオン種をイオン注入しておけば、ｐ型ベース領域形成用に注入されたｐ型不純物の熱拡散が抑制され、ｐ型ベース領域５の形成位置が正確に規定される。これにより、ｐ型ベース領域５の間が狭くなることを防止でき、Ｊ−ＦＥＴ部の幅が狭まらないようにすることができる。
【００４５】
〔図５（ａ）に示す工程〕
ＬＴＯ膜２０を除去したのち、ｐ型ベース領域５を含むｎ- 型エピ層４の表面に、例えば０．３μｍ以下の膜厚で表面チャネル層７をエピタキシャル成長させる。
【００４６】
このとき、縦型パワーＭＯＳＦＥＴをノーマリオフ型にするために、表面チャネル層７の厚み（膜厚）を、ゲート電極９に電圧を印加していない時におけるｐ型ベース領域５から表面チャネル層７に広がる空乏層の伸び量と、ゲート酸化膜８から表面チャネル層７に広がる空乏層の伸び量との和よりも小さくなるようにしている。
【００４７】
具体的には、ｐ型ベース領域５から表面チャネル層７に広がる空乏層の伸び量は、表面チャネル層７とｐ型ベース領域５とのＰＮ接合のビルトイン電圧によって決定され、ゲート酸化膜８から表面チャネル層７に広がる空乏層の伸び量は、ゲート酸化膜８の電荷及びゲート電極９（金属）と表面チャネル層７（半導体）との仕事関数差によって決定されるため、これらに基づいて表面チャネル層７の膜厚を決定している。
【００４８】
このようなノーマリオフ型の縦型パワーＭＯＳＦＥＴは、故障などによってゲート電極に電圧が印加できないような状態となっても、電流が流れないようにすることができるため、ノーマリオン型のものと比べて安全性を確保することができる。
【００４９】
〔図５（ｂ）に示す工程〕
表面チャネル層７の上の所定領域にＬＴＯ膜２１を配置したのち、これをマスクとしてＢ若しくはＡｌ等のｐ型不純物をイオン注入し、ディープベース層５ａを形成する。
【００５０】
〔図６（ａ）に示す工程〕
表面チャネル層７の上の所定領域にＬＴＯ膜２２を配置したのち、これをマスクとしてＮ（窒素）等のｎ型不純物をイオン注入し、ｎ+ 型ソース領域６を形成する。このときのイオン注入条件は、７００℃、ドーズ量は１×１０15ｃｍ-2としている。
【００５１】
〔図６（ｂ）に示す工程〕
ＬＴＯ膜２２を除去した後、基板の上にウェット酸化（Ｈ2 ＋Ｏ2 によるパイロジェニック法を含む）によりゲート酸化膜８を形成する。このとき、雰囲気温度は１０８０℃とする。その後、ゲート酸化膜８の上にポリシリコンからなるゲート電極９をＬＰＣＶＤにより堆積する。このときの成膜温度は６００℃とする。そして、ゲート電極９及びゲート酸化膜８の不要部分を除去する。
【００５２】
この後、図示しないがＬＴＯよりなる絶縁膜を形成してゲート酸化膜８を覆ったのち、絶縁膜にコンタクトホールを形成し、室温での金属スパッタリングによりソース電極１０及びドレイン電極１１を配置し、成膜後に１０００℃のアニールを行う。このようにして、図１に示す縦型パワーＭＯＳＦＥＴが完成する。
【００５３】
（第２実施形態）
本実施形態では、第１実施形態に示した縦型パワーＭＯＳＦＥＴの周囲にガードリングやＥＱＲを配置する場合について説明する。図７に、ガードリング及びＥＱＲを備えた縦型パワーＭＯＳＦＥＴの断面構成を示す。
【００５４】
図７に示すように、図１と同様の構成のＭＯＳＦＥＴが備えられている。このＭＯＳＦＥＴから離間された位置において、ｎ-型エピ層４の表層部には複数のｐ型層１２が所定間隔おきに配置されている。このｐ型層１２はＭＯＳＦＥＴの周囲を囲むようにリング状に形成されている。これら複数のｐ型層１２がガードリングを構成している。また、ガードリングを構成するｐ型層１２のリング外側にはｎ-型エピ層４の表層部に形成されたｎ型層１３及びｎ型層１３の上に形成された電極１４とからなるＥＱＲが備えられている。
【００５５】
そして、ＭＯＳＦＥＴが形成されたセル領域、ガードリングが形成されたガードリング領域、及びＥＱＲが形成された領域全域において、ｎ+型基板１の主表面１ａの上には、全面にｎ型層２及びｐ型層３からなるスーパージャンクションが構成されている。このように、ガードリングやＥＱＲ等のＭＯＳＦＥＴとは異なる部分を形成する場合においては、これらガードリングやＥＱＲが形成される領域にもスーパージャンクションを形成するようにしている。
【００５６】
このように、ｎ+型基板１の全面にスーパージャンクションを構成するｎ型層２とｐ型層３を交互に配置することで、ＭＯＳＦＥＴ等の形成時においてマスクずれ等が発生しても、ＭＯＳＦＥＴが形成される領域に必ずスーパージャンクションが配置されることになる。このため、確実にｐ型ベース領域５及びソース領域６下をピンチオフさせることができ、確実にＭＯＳＦＥＴの耐圧が得られるようにできる。
【００５７】
（他の実施形態）
上記実施形態では、スーパージャンクションを構成するｎ型層２とｐ型層３とが交互に配置されることについて説明したが、ｎ型層２とｐ型層３とが交互に配置され、これらによって形成されるＰＮ接合によってスーパージャンクションがピンチオフされるような構成であればどのようなレイアウトであってもよい。
【００５８】
例えば、ｎ型層２とｐ型層３とをストライプ状に配置してもよく、ｎ+型基板１の主表面１ａの垂直方向から見てｎ型層２とｐ型層３とが共に六角形状になるようにし、一断面を見るとｎ型層２とｐ型層３とが交互に配置されるようにしてもよい。
【図面の簡単な説明】
【図１】本発明の第１実施形態におけるスーパージャンクションＭＯＳＦＥＴの断面構成を示す図である。
【図２】（ａ）は、図１のＭＯＳＦＥＴの耐圧を示す特性図であり、（ｂ）は図１のＭＯＳＦＥＴのオン抵抗を示す特性図である。
【図３】図１に示す縦型パワーＭＯＳＦＥＴの製造工程を示す図である。
【図４】図３に続く縦型パワーＭＯＳＦＥＴの製造工程を示す図である。
【図５】図４に続く縦型パワーＭＯＳＦＥＴの製造工程を示す図である。
【図６】図５に続く縦型パワーＭＯＳＦＥＴの製造工程を示す図である。
【図７】本発明の第２実施形態における縦型パワーＭＯＳＦＥＴにガードリング及びＥＱＲを備えた場合の断面構成を示す図である。
【図８】従来のスーパージャンクションを備えたＭＯＳＦＥＴの断面構成を示す図である。
【符号の説明】
１…ｎ+型基板、２…ｎ型層、３…ｐ型層、４…ｎ-型エピ層、
５…ｐ型ベース領域、６…ｎ+型ソース領域、７…表面チャネル層、
８…ゲート酸化膜、９…ゲート電極、１０…ソース電極、１１…ドレイン電極。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device such as a power MOSFET or SIT and a manufacturing method thereof, and is particularly suitable for use in a semiconductor device made of silicon carbide.
[0002]
[Prior art]
Conventionally, there is a structure proposed in US Pat. No. 5,438,215 for maintaining a high breakdown voltage of a MOSFET. This structure is shown in FIG.
[0003]
As shown in FIG. 8, a p-type base region 103 is formed in a surface layer portion of an n-type epi layer 102 epitaxially grown on a semiconductor substrate 101, and an n-type source region 104 is formed in the p-type base region 103. Has been. Under the n-type source region 104 and the p-type base region 103, n-type layers 105 and p-type layers 106 are alternately arranged to form a super junction having a plurality of PN junctions.
[0004]
The super junction MOSFET (SJ MOSFET) configured as described above has a depletion layer extending at a plurality of PN junctions constituting the super junction and pinches off the super junction portion, so that the breakdown voltage of the MOSFET can be obtained. It has become.
[0005]
[Problems to be solved by the invention]
However, conventionally, a plurality of PN junctions constituting a super junction are selectively formed only in an element portion where the p-type base region 103 and the n-type source region 104 are formed. In some cases, the super junction is not accurately formed in the element portion due to the mask displacement or the like, and the p-type base region 103 and the n-type source region 104 cannot be completely pinched off, so that the withstand voltage cannot be secured.
[0006]
In view of the above-described points, an object of the present invention is to ensure that a plurality of PN junctions constituting a super junction are arranged in an element portion and to ensure the withstand voltage of a MOSFET.
[0007]
[Means for Solving the Problems]
In order to achieve the above object, according to the first aspect of the present invention, a plurality of first conductivity type layers (2) and a plurality of layers are formed on the main surface (1a) of the semiconductor substrate (1). The first conductivity type layer and the second conductivity type layer constituting the super junction are provided with a super junction composed of a plurality of PN junctions formed by alternately arranging the second conductivity type layers (3). It is characterized by being formed on the entire main surface.
[0008]
Thus, if the super junction is formed on the entire main surface of the semiconductor substrate, the super junction is always formed under the base region and the source region even if the super junction formation position is shifted due to mask displacement or the like. The breakdown voltage of the MOSFET can be reliably obtained.
[0011]
Further, in the first aspect of the present invention, a super junction is provided in the entire cell region and guard ring region, and the first conductivity type layer and the second conductivity type layer constituting the super junction are repeatedly and continuously connected. I have to.
[0012]
As described above, when the guard ring is formed on the outer peripheral portion surrounding the cell region, the above effect can be obtained even if the super junction is formed up to the guard ring region.
[0013]
A second aspect of the present invention is a method for manufacturing a semiconductor device according to the first aspect . Specifically, a first conductivity type layer is formed on the whole main surface of the semi-conductor substrate, after performing ion implantation of a second conductivity type impurity into the first conductivity type layer, a second conductivity type impurity By activating and forming the second conductivity type layer, the first conductivity type layer and the second conductivity type layer can be formed on the entire main surface of the semiconductor substrate.
[0014]
In this case , in the step of forming the second conductivity type layer, an inactive ion species is ion-implanted in a region of the first conductivity type layer where the second conductivity type impurity is ion-implanted, and the inactive ion species is After the implantation, the second conductivity type impurity can be activated. That is, since the vacancy of the carbon site can be eliminated by the inert ion species, diffusion of the second conductivity type impurity based on the vacancy of the carbon site can be suppressed, and the first conductivity type layer and the second conductivity type can be suppressed. The width of the mold layer can be accurately defined.
[0015]
In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
FIG. 1 shows a super junction MOSFET according to a first embodiment of the present invention. This figure shows one unit cell of MOSFET constituting the element portion of the semiconductor device. In practice, the semiconductor device is constituted with a plurality of unit cells or other circuit elements. Hereinafter, the configuration of the MOSFET in this embodiment will be described with reference to FIG.
[0017]
As shown in FIG. 1, n + type substrate 1 made of silicon carbide has a top surface as main surface 1a and a bottom surface opposite to main surface 1a as back surface 1b. N-type layer 2 and p-type layer 3 made of silicon carbide extend over the entire surface of main surface 1a of n + -type substrate 1, and these n-type layer 2 and p-type layer 3 are alternately arranged. Thus, a plurality of PN junctions are formed. The plurality of PN junctions constitute a super junction. The PN junction constituting the super junction is formed on all the main surfaces 1 a of the n + type substrate 1. That is, all the super junctions are also formed in the region where a plurality of unit cells or other circuit elements are formed, and all these super junctions are continuously connected without being interrupted.
[0018]
Each n-type layer 2 and p-type layer 3 constituting a plurality of PN junctions of a super junction are configured with an equivalent thickness of 3 μm, and the width Wn of the n-type layer 2 and the width Wp of the p-type layer 3 are the same. 1 μm. The n-type layer 2 has an impurity concentration of about 2 × 10 17 cm −3, and the p-type layer 3 has an impurity concentration of about 2 × 10 17 cm −3 .
[0019]
This concentration and width are shown in Jpn. J. et al. Appl. Phys. Vol. 36 (1997) pp 6254-6262 may be set so as to satisfy the relational expression.
[0020]
On a plurality of PN junctions constituting a super junction, an n − type epitaxial layer 4 made of silicon carbide having an impurity concentration lower than that of the n + type substrate 1 is laminated with a thickness of about 2 μm. The impurity concentration of the n − type epi layer 4 is equal to the impurity concentration of the n type layer 2.
[0021]
A p-type base region 5 having a predetermined depth is formed in a predetermined region in the surface layer portion of the n − -type epi layer 4. The p − type base region 5 is formed using B as a dopant, and has a concentration of approximately 1 × 10 17 cm −3 or more.
[0022]
Further, an n + type source region 6 shallower than the base region 5 is formed in a predetermined region of the surface layer portion of the p type base region 5.
[0023]
Further, an n − type SiC layer 7 is extended on the surface portion of the p type base region 5 so as to connect the n + type source region 6 and the n − type epi layer 2. The n − -type SiC layer 7 is formed by epitaxial growth, and the epitaxial film having 4H, 6H, 3C, or 15R is used. The n − type SiC layer 7 functions as a channel forming layer during device operation. Hereinafter, the n − type SiC layer 7 is referred to as a surface channel layer.
[0024]
The surface channel layer 7 is formed using N (nitrogen) as a dopant, and the dopant concentration is, for example, a low concentration of about 1 × 10 15 cm −3 to 1 × 10 17 cm −3 , and n − The dopant concentration is lower than that of the type epi layer 4 and the p − type base region 5. Thereby, low on-resistance is achieved.
[0025]
A gate oxide film 8 is formed on the upper surface of the surface channel layer 7 and the upper surface of the n + -type source region 6 by thermal oxidation. Further, a gate electrode 9 is formed on the gate oxide film 8.
[0026]
A source electrode 10 is formed in contact with the n + type source region 6 and the p type base region 5. A drain electrode 11 is formed on the back surface 1 b of the n + type substrate 1.
[0027]
Note that a portion of the p-type base region 5 that is in contact with the source electrode 10 is a deep base layer 5 a having a junction depth deeper than other portions of the p-type base region 5. The deep base layer 5a has a higher p-type impurity concentration than the other parts of the p-type base region 5, and preferentially avalanche breaks down during reverse bias.
[0028]
The p-type layer 3 and the p-type base region 5 in the PN junction constituting the super junction are grounded in a cross section different from that shown in FIG.
[0029]
Thus, since the super junction of each element part is connected continuously without being interrupted, the super junction is surely provided in each element part, and the p-type base region 5 and the n + The lower part of the mold source region 6 can be pinched off, and the MOSFET withstand voltage can be surely obtained.
[0030]
The breakdown voltage and on-resistance characteristics of the super junction MOSFET having the above-described configuration were examined by experiments. The results are shown in FIGS. 2 (a) and 2 (b), respectively.
[0031]
As shown in FIG. 2A, an avalanche breakdown occurs when the applied voltage to the drain electrode 11 is 1037 V during reverse bias, and a breakdown voltage is obtained.
[0032]
On the other hand, as shown in FIG. 2B, it can be seen that the super junction MOSFET in the present embodiment has a larger drain current than the MOSFET not forming the super junction, and the on-resistance is reduced.
[0033]
This is because by forming a super junction, the impurity concentration in this region can be increased, that is, the resistance can be lowered, so that the on-resistance can be reduced.
[0034]
As described above, the super junction MOSFET according to the present embodiment can surely obtain the withstand voltage of the MOSFET and reduce the on-resistance of the MOSFET.
[0035]
Next, the manufacturing process of the MOSFET shown in FIG. 1 will be described with reference to FIGS.
[0036]
[Step shown in FIG. 3 (a)]
First, an n-type 4H, 6H, 3C, or 15R—SiC substrate, that is, an n + -type substrate 1 is prepared. The n + type substrate 1 has a thickness of 400 μm, and the main surface 1a is a (0001) Si surface or a (112-0) a surface.
[0037]
[Step shown in FIG. 3B]
N-type layer 2 having a thickness of 3 μm is epitaxially grown on main surface 1a of n + -type substrate 1. At this time, the n-type layer 2 has the same crystal as the underlying n + -type substrate 1 and becomes an n-type 4H, 6H, 3C, or 15R—SiC layer.
[0038]
[Step shown in FIG. 3 (c)]
Then, a mask in which a p-type layer formation scheduled region is opened is arranged on the surface of the n-type layer 2, and after p-type impurities such as B and Al are ion-implanted, the p-type impurities are activated by heat treatment, and the p-type layer 3 is formed. At this time, the p-type layer 3 is formed on the entire surface of the n + -type substrate 1 (or all the regions where elements are formed and which are not unnecessary portions removed by dicing).
[0039]
Thereby, a super junction in which the n-type layer 2 and the p-type layer 3 are alternately arranged is formed on the entire surface of the n + -type substrate 1. For this reason, even if a mask shift occurs during the formation of each element portion to be formed thereafter, a super junction is always formed in each element portion.
[0040]
At this time, an inert ion species such as C (carbon) may be implanted before implanting B or Al. In this way, by injecting an inactive ion species such as C before activating the p-type impurity, it becomes inactive in the vacancy of the carbon site formed in the n-type layer 2 during the epitaxial growth or the like. Ionic species can enter and the vacancy of the carbon site of the n-type layer 2 can be eliminated, so that the diffusion of p-type impurities due to the vacancy of the carbon site is suppressed, and the n-type layer 2 and the p-type layer 3 The width of can be accurately defined.
[0041]
[Step shown in FIG. 4 (a)]
Next, an n − type epi layer 4 having a thickness of about 5 μm is epitaxially grown on the n type layer 2 and the p type layer 3 constituting the super junction. At this time, the n − -type epi layer 4 is obtained with the same crystal as the underlying n-type layer 2 and p-type layer 3 and becomes an n-type 4H, 6H, 3C, or 15R—SiC layer.
[0042]
[Step shown in FIG. 4B]
An LTO (Low Temperature Oxidation) film 20 is disposed in a predetermined region on the n − -type epi layer 4, and ion implantation of p-type impurities such as B or Al is performed using this film as a mask. At this time, the ion implantation conditions are a temperature of 700 ° C. and a dose of 1 × 10 16 cm −2 . Thereby, a box profile made of B is formed at a predetermined depth from the surface of the n − -type epi layer 4.
[0043]
Thereafter, activation annealing is performed at 1600 ° C. for 30 minutes as a heat treatment, and B is activated to form the p-type base region 5.
[0044]
At this time, similarly to the formation of the p-type layer 3, if an inactive ion species such as C is ion-implanted into the portion to be the p-type base region 5, the p implanted for forming the p-type base region is used. The thermal diffusion of the type impurities is suppressed, and the formation position of the p-type base region 5 is accurately defined. As a result, the gap between the p-type base regions 5 can be prevented from being narrowed, and the width of the J-FET portion can be prevented from being narrowed.
[0045]
[Step shown in FIG. 5A]
After removing the LTO film 20, the surface channel layer 7 is epitaxially grown on the surface of the n − -type epi layer 4 including the p-type base region 5 with a film thickness of, for example, 0.3 μm or less.
[0046]
At this time, in order to make the vertical power MOSFET normally-off type, the thickness (film thickness) of the surface channel layer 7 is changed from the p-type base region 5 to the surface channel layer 7 when no voltage is applied to the gate electrode 9. The expansion amount of the depletion layer is made smaller than the sum of the extension amount of the depletion layer extending from the gate oxide film 8 to the surface channel layer 7.
[0047]
Specifically, the extension amount of the depletion layer extending from the p-type base region 5 to the surface channel layer 7 is determined by the built-in voltage of the PN junction between the surface channel layer 7 and the p-type base region 5, and from the gate oxide film 8. The amount of extension of the depletion layer extending to the surface channel layer 7 is determined by the charge of the gate oxide film 8 and the work function difference between the gate electrode 9 (metal) and the surface channel layer 7 (semiconductor). The film thickness of the channel layer 7 is determined.
[0048]
Such a normally-off type vertical power MOSFET can prevent current from flowing even when a voltage cannot be applied to the gate electrode due to a failure or the like. Safety can be ensured.
[0049]
[Step shown in FIG. 5B]
After the LTO film 21 is disposed in a predetermined region on the surface channel layer 7, a p-type impurity such as B or Al is ion-implanted using this as a mask to form the deep base layer 5a.
[0050]
[Step shown in FIG. 6A]
After the LTO film 22 is disposed in a predetermined region on the surface channel layer 7, n-type impurities such as N (nitrogen) are ion-implanted using the LTO film 22 as a mask to form the n + -type source region 6. The ion implantation conditions at this time are 700 ° C. and the dose is 1 × 10 15 cm −2 .
[0051]
[Step shown in FIG. 6B]
After removing the LTO film 22, a gate oxide film 8 is formed on the substrate by wet oxidation (including a pyrogenic method using H 2 + O 2 ). At this time, the ambient temperature is set to 1080 ° C. Thereafter, a gate electrode 9 made of polysilicon is deposited on the gate oxide film 8 by LPCVD. The film forming temperature at this time is 600 ° C. Then, unnecessary portions of the gate electrode 9 and the gate oxide film 8 are removed.
[0052]
Thereafter, although not shown, an insulating film made of LTO is formed and the gate oxide film 8 is covered. Then, a contact hole is formed in the insulating film, and the source electrode 10 and the drain electrode 11 are disposed by metal sputtering at room temperature. After film formation, annealing at 1000 ° C. is performed. In this way, the vertical power MOSFET shown in FIG. 1 is completed.
[0053]
(Second Embodiment)
In the present embodiment, a case where a guard ring or an EQR is arranged around the vertical power MOSFET shown in the first embodiment will be described. FIG. 7 shows a cross-sectional configuration of a vertical power MOSFET provided with a guard ring and an EQR.
[0054]
As shown in FIG. 7, a MOSFET having the same configuration as that of FIG. 1 is provided. A plurality of p-type layers 12 are arranged at predetermined intervals in the surface layer portion of the n − -type epi layer 4 at positions spaced from the MOSFET. The p-type layer 12 is formed in a ring shape so as to surround the periphery of the MOSFET. The plurality of p-type layers 12 form a guard ring. Further, an EQR comprising an n-type layer 13 formed on the surface layer portion of the n − -type epi layer 4 and an electrode 14 formed on the n-type layer 13 outside the ring of the p-type layer 12 constituting the guard ring. Is provided.
[0055]
Then, in the entire cell region where the MOSFET is formed, the guard ring region where the guard ring is formed, and the region where the EQR is formed, the entire surface of the n + -type substrate 1 over the main surface 1a is the n-type layer 2. And the super junction which consists of the p-type layer 3 is comprised. As described above, when a portion different from a MOSFET such as a guard ring or EQR is formed, a super junction is also formed in a region where the guard ring or EQR is formed.
[0056]
In this way, by alternately arranging the n-type layer 2 and the p-type layer 3 constituting the super junction on the entire surface of the n + -type substrate 1, even if a mask shift or the like occurs during the formation of the MOSFET, the MOSFET The super junction is always arranged in the region where the is formed. Therefore, the p-type base region 5 and the source region 6 can be reliably pinched off, and the breakdown voltage of the MOSFET can be reliably obtained.
[0057]
(Other embodiments)
In the embodiment described above, the n-type layer 2 and the p-type layer 3 constituting the super junction are alternately arranged. However, the n-type layer 2 and the p-type layer 3 are alternately arranged. Any layout may be used as long as the super junction is pinched off by the formed PN junction.
[0058]
For example, the n-type layer 2 and the p-type layer 3 may be arranged in stripes, and the n-type layer 2 and the p-type layer 3 are both hexagonal when viewed from the direction perpendicular to the main surface 1a of the n + -type substrate 1. The n-type layer 2 and the p-type layer 3 may be alternately arranged when viewed in a cross section.
[Brief description of the drawings]
FIG. 1 is a diagram showing a cross-sectional configuration of a super junction MOSFET in a first embodiment of the present invention.
2A is a characteristic diagram showing a withstand voltage of the MOSFET of FIG. 1, and FIG. 2B is a characteristic diagram showing an on-resistance of the MOSFET of FIG. 1;
3 is a diagram showing a manufacturing process of the vertical power MOSFET shown in FIG. 1. FIG.
4 is a diagram showing manufacturing steps of the vertical power MOSFET subsequent to FIG. 3. FIG.
5 is a diagram showing the manufacturing process of the vertical power MOSFET subsequent to FIG. 4. FIG.
6 is a diagram showing the manufacturing process of the vertical power MOSFET subsequent to FIG. 5. FIG.
FIG. 7 is a diagram showing a cross-sectional configuration when a vertical power MOSFET according to a second embodiment of the present invention includes a guard ring and an EQR.
FIG. 8 is a diagram showing a cross-sectional configuration of a MOSFET having a conventional super junction.
[Explanation of symbols]
1 ... n + type substrate, 2 ... n type layer, 3 ... p type layer, 4 ... n - type epi layer,
5 ... p-type base region, 6 ... n + type source region, 7 ... surface channel layer,
8 ... Gate oxide film, 9 ... Gate electrode, 10 ... Source electrode, 11 ... Drain electrode.

Claims (2)

主表面（１ａ）と該主表面の反対面である裏面（１ｂ）を有し、炭化珪素よりなる第１導電型の半導体基板（１）と、
前記半導体基板の前記主表面側に形成され前記半導体基板よりも高抵抗な第１導電型の半導体層（４）と、
前記半導体層の表層部の所定領域に形成され、所定深さを有する第２導電型のベース領域（５）と、
前記ベース領域の表層部の所定領域に形成され、該ベース領域の深さよりも浅い第１導電型のソース領域（６）と、
前記ベース領域のうち、前記半導体層及び前記ソース領域に挟まれた部分の上に形成されたゲート絶縁膜（８）と、
前記ゲート絶縁膜の上に形成されたゲート電極（９）と、
前記ベース領域及び前記ソース領域に接触するように形成されたソース電極（１０）と、
前記半導体基板の前記裏面に形成されたドレイン電極（１１）と、を有してなるＦＥＴが形成されるセル領域と、
該セル領域から所定間隔離間して該セル領域を囲むように、前記半導体層の表層部に形成された複数の第２導電型のウェル領域からなるガードリング領域と、を備え、
前記セル領域及び前記ガードリング領域の全域において、前記半導体基板と前記半導体層との間には、複数の第１導電型（２）と複数の第２導電型層（３）とが交互に配置されて形成された複数のＰＮ接合からなるスーパージャンクションが備えられており、該スーパージャンクションを構成する前記第１導電型層及び前記第２導電型層が繰り返し連続的につながっていることを特徴とする炭化珪素半導体装置。A first conductivity type semiconductor substrate (1) having a main surface (1a) and a back surface (1b) opposite to the main surface and made of silicon carbide;
A first conductivity type semiconductor layer (4) formed on the main surface side of the semiconductor substrate and having a higher resistance than the semiconductor substrate;
A second conductivity type base region (5) formed in a predetermined region of a surface layer portion of the semiconductor layer and having a predetermined depth;
A source region (6) of a first conductivity type formed in a predetermined region of a surface layer portion of the base region and shallower than a depth of the base region;
A gate insulating film (8) formed on a portion of the base region sandwiched between the semiconductor layer and the source region;
A gate electrode (9) formed on the gate insulating film;
A source electrode (10) formed in contact with the base region and the source region;
A drain region (11) formed on the back surface of the semiconductor substrate, and a cell region in which an FET is formed,
A guard ring region composed of a plurality of second conductivity type well regions formed in a surface layer portion of the semiconductor layer so as to surround the cell region at a predetermined interval from the cell region,
A plurality of first conductivity type (2) and a plurality of second conductivity type layers (3) are alternately arranged between the semiconductor substrate and the semiconductor layer in the entire area of the cell region and the guard ring region. A super junction composed of a plurality of PN junctions formed, and the first conductivity type layer and the second conductivity type layer constituting the super junction are repeatedly connected continuously. A silicon carbide semiconductor device. 主表面（１ａ）と該主表面の反対面である裏面（１ｂ）を有した炭化珪素よりなる第１導電型の半導体基板（１）を用意する工程と、
前記半導体基板の前記主表面上に第１導電型層（２）及び第２導電型層（３）を交互に配置し、複数のＰＮ接合からなるスーパージャンクションを形成する工程と、
前記スーパージャンクション上に前記半導体基板よりも高抵抗な第１導電型の半導体層（４）を形成する工程と、
前記半導体層の表層部の所定領域に、所定深さを有する第２導電型のベース領域（５）を形成する工程と、
前記ベース領域の表層部の所定領域に、該ベース領域の深さよりも浅い第１導電型のソース領域（６）を形成する工程と、
前記ベース領域のうち、前記半導体層及び前記ソース領域に挟まれた部分の上にゲート絶縁膜（８）を形成する工程と、
前記ゲート絶縁膜の上にゲート電極（９）を形成する工程と、
前記ベース領域及び前記ソース領域に接触するようにソース電極（１０）を形成する工程と、
前記半導体基板の前記裏面にドレイン電極（１１）を形成する工程とを有し、
前記スーパージャンクションを形成する工程は、該スーパージャンクションを構成する前記第１導電型層及び前記第２導電型層が前記半導体基板の前記主表面全面に形成されるようにするもので、前記半導体基板の前記主表面上全面に前記第１導電型層を形成する工程と、前記第１導電型層に第２導電型不純物のイオン注入を行ったあと、該第２導電型不純物を活性化させ、前記第２導電型層を形成する工程と、を有し、
前記第２導電型層を形成する工程では、前記第１導電型層のうち前記第２導電型不純物をイオン注入する領域に不活性なイオン種をイオン注入する工程を有し、該不活性なイオン種を注入したのち、前記第２導電型不純物を活性化させることを特徴とする炭化珪素半導体装置の製造方法。Providing a first conductivity type semiconductor substrate (1) made of silicon carbide having a main surface (1a) and a back surface (1b) opposite to the main surface;
A step of alternately disposing a first conductivity type layer (2) and a second conductivity type layer (3) on the main surface of the semiconductor substrate to form a super junction comprising a plurality of PN junctions;
Forming a first conductive type semiconductor layer (4) having a higher resistance than the semiconductor substrate on the super junction;
Forming a second conductivity type base region (5) having a predetermined depth in a predetermined region of a surface layer portion of the semiconductor layer;
Forming a first conductivity type source region (6) shallower than a depth of the base region in a predetermined region of a surface layer portion of the base region;
Forming a gate insulating film (8) on a portion of the base region sandwiched between the semiconductor layer and the source region;
Forming a gate electrode (9) on the gate insulating film;
Forming a source electrode (10) in contact with the base region and the source region;
Forming a drain electrode (11) on the back surface of the semiconductor substrate,
As engineering of forming the super junction is intended to make the first conductivity type layer and the second conductivity type layer constituting the super junction is formed in the main the entire surface of the semiconductor substrate, the semiconductor Forming the first conductivity type layer over the entire main surface of the substrate; and ion-implanting the second conductivity type impurity into the first conductivity type layer, and then activating the second conductivity type impurity. And forming the second conductivity type layer,
The step of forming the second conductivity type layer includes a step of ion-implanting an inactive ion species into a region of the first conductivity type layer into which the second conductivity-type impurity is ion-implanted. A method for manufacturing a silicon carbide semiconductor device , wherein the second conductivity type impurity is activated after ion species are implanted .
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