JP2001144292A - Silicon carbide semiconductor device - Google Patents

Silicon carbide semiconductor device

Info

Publication number
JP2001144292A
JP2001144292A JP32693399A JP32693399A JP2001144292A JP 2001144292 A JP2001144292 A JP 2001144292A JP 32693399 A JP32693399 A JP 32693399A JP 32693399 A JP32693399 A JP 32693399A JP 2001144292 A JP2001144292 A JP 2001144292A
Authority
JP
Japan
Prior art keywords
layer
conductivity type
region
semiconductor substrate
main surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP32693399A
Other languages
Japanese (ja)
Other versions
JP4450122B2 (en
Inventor
Kumar Rajesh
クマール ラジェシュ
Takeshi Yamamoto
剛 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
Denso Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Corp filed Critical Denso Corp
Priority to JP32693399A priority Critical patent/JP4450122B2/en
Publication of JP2001144292A publication Critical patent/JP2001144292A/en
Application granted granted Critical
Publication of JP4450122B2 publication Critical patent/JP4450122B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H01L29/7828—Vertical transistors without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PROBLEM TO BE SOLVED: To surely provide withstand voltage to a MOSFET by allowing a plurality of P-N junctions constituting a super-junction to be provided to an element part with sure. SOLUTION: A super-junction comprises, formed on a main surface 1a of an n+ type substrate 1, a plurality of P-N junctions where a plurality of n-type layers 2 and p-type layers 3 are provided alternately on the main surface 1a, with the n-type layers 2 and p-type layers 3, constituting the super-junction formed on the entire surface of main surface 1a of the n+ type substrate 1. With the super-junction formed over the entire surface of the main surface 1a of the n+ type substrate 1, the super-junction is formed surely under a p-type base region 5 and n-type source region 6, even if the super-junction formation position deviates due to dislocation of a mask, etc., providing surely an MOSFET with withstand voltage.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、パワーＭＯＳＦＥ
ＴやＳＩＴ等の半導体装置及びその製造方法に関するも
ので、特に炭化珪素よりなる半導体装置に用いて好適で
ある。The present invention relates to a power MOSFET.
The present invention relates to a semiconductor device such as T or SIT and a method for manufacturing the same, and is particularly suitable for use in a semiconductor device made of silicon carbide.

【０００２】[0002]

【従来の技術】従来、ＭＯＳＦＥＴの高耐圧を維持する
ものとして、米国特許第５、４３８、２１５号明細書に
提案されている構造がある。この構造を図８に示す。2. Description of the Related Art Conventionally, there is a structure proposed in US Pat. No. 5,438,215 for maintaining a high breakdown voltage of a MOSFET. This structure is shown in FIG.

【０００３】図８に示すように、半導体基板１０１上に
エピタキシャル成長させたｎ型エピ層１０２の表層部に
ｐ型ベース領域１０３が形成されていると共に、ｐ型ベ
ース領域１０３内にｎ型ソース領域１０４が形成されて
いる。そして、これらｎ型ソース領域１０４及びｐ型ベ
ース領域１０３の下方には、ｎ型層１０５とｐ型層１０
６とが交互に並べられて複数のＰＮ接合を構成したスー
パージャンクションが形成されている。As shown in FIG. 8, a p-type base region 103 is formed in a surface portion of an n-type epi layer 102 epitaxially grown on a semiconductor substrate 101, and an n-type source region is formed in the p-type base region 103. 104 are formed. Under the n-type source region 104 and the p-type base region 103, an n-type layer 105 and a p-type
6 are alternately arranged to form a super junction in which a plurality of PN junctions are formed.

【０００４】このように構成されたスーパージャンクシ
ョンＭＯＳＦＥＴ（Ｓ．Ｊ．ＭＯＳＦＥＴ）は、スーパ
ージャンクションを構成する複数のＰＮ接合部において
空乏層が伸び、スーパージャンクション部分をピンチオ
フさせることで、ＭＯＳＦＥＴの耐圧が得られるように
なっている。In the super junction MOSFET (SJ MOSFET) configured as described above, a depletion layer extends at a plurality of PN junctions constituting the super junction, and the breakdown voltage of the MOSFET is reduced by pinching off the super junction. You can get it.

【０００５】[0005]

【発明が解決しようとする課題】しかしながら、従来で
はスーパージャンクションを構成する複数のＰＮ接合
を、ｐ型ベース領域１０３やｎ型ソース領域１０４が形
成される素子部にのみ選択的に形成するようにしている
ため、ＰＮ接合形成用マスクのマスクずれ等によってス
ーパージャンクションが正確に素子部に形成されない場
合があり、ｐ型ベース領域１０３及びｎ型ソース領域１
０４下を完全にピンチオフさせることができず、耐圧が
確保できないという問題がある。However, conventionally, a plurality of PN junctions constituting a super junction are selectively formed only in an element portion where the p-type base region 103 and the n-type source region 104 are formed. Therefore, a super junction may not be accurately formed in the element portion due to a mask shift of a mask for forming a PN junction or the like, and the p-type base region 103 and the n-type source region 1 may not be formed.
There is a problem that it is not possible to completely pinch off the area underneath 04 and a withstand voltage cannot be secured.

【０００６】本発明は上記点に鑑みて、スーパージャン
クションを構成する複数のＰＮ接合が素子部に確実に配
置されるようにし、確実にＭＯＳＦＥＴの耐圧が得られ
るようにすることを目的とする。SUMMARY OF THE INVENTION In view of the foregoing, it is an object of the present invention to ensure that a plurality of PN junctions forming a super junction are arranged in an element portion and that a withstand voltage of a MOSFET can be reliably obtained.

【０００７】[0007]

【課題を解決するための手段】上記目的を達成するた
め、請求項１に記載の発明では、半導体基板（１）の主
表面（１ａ）上に形成され、該主表面上において複数の
第１導電型層（２）と複数の第２導電型層（３）とが交
互に配置されて形成された複数のＰＮ接合からなるスー
パージャンクションを備え、スーパージャンクションを
構成する第１導電型層及び第２導電型層は、半導体基板
の主表面全面に形成されていることを特徴としている。In order to achieve the above object, according to the first aspect of the present invention, a semiconductor device is formed on a main surface (1a) of a semiconductor substrate (1), and a plurality of first surfaces are formed on the main surface. A first conductivity type layer comprising a plurality of PN junctions formed by alternately arranging the conductivity type layers (2) and the plurality of second conductivity type layers (3); The two-conductivity-type layer is characterized in that it is formed over the entire main surface of the semiconductor substrate.

【０００８】このように、スーパージャンクションが半
導体基板の主表面全面に形成されていれば、マスクずれ
等によってスーパージャンクションの形成位置がずれて
も、必ずベース領域やソース領域下にスーパージャンク
ションが形成されるため、確実にＭＯＳＦＥＴの耐圧を
得ることができる。As described above, if the super junction is formed on the entire main surface of the semiconductor substrate, the super junction is always formed under the base region and the source region even if the formation position of the super junction is shifted due to a mask shift or the like. Therefore, the breakdown voltage of the MOSFET can be reliably obtained.

【０００９】請求項２に記載の発明においては、ＦＥＴ
をユニットセルとし、該ユニットセルが複数形成される
セル領域に、複数のＰＮ接合からなるスーパージャンク
ションを備え、セル領域下部全域を第１導電型層及び第
２導電型層が繰り返し連続的につながるようにしてい
る。According to the second aspect of the present invention, the FET
Is provided as a unit cell, a cell region in which a plurality of the unit cells are formed is provided with a super junction composed of a plurality of PN junctions, and the first conductive type layer and the second conductive type layer are repeatedly and continuously connected to the entire lower region of the cell region. Like that.

【００１０】このように、複数のＦＥＴが形成されるセ
ル領域全域において、各ユニットセルの第１導電型層及
び第２導電型層が繰り返し連続的につながるようにすれ
ば、請求項１の効果を得ることができる。As described above, if the first conductivity type layer and the second conductivity type layer of each unit cell are connected repeatedly and continuously over the entire cell region where a plurality of FETs are formed, the effect of claim 1 is achieved. Can be obtained.

【００１１】請求項３に記載の発明においては、セル領
域及びガードリング領域の全域においてスーパージャン
クションを備え、該スーパージャンクションを構成する
第１導電型層及び第２導電型層が繰り返し連続的につな
がるようにしている。According to the third aspect of the present invention, a super junction is provided in the entire area of the cell region and the guard ring region, and the first conductivity type layer and the second conductivity type layer forming the super junction are connected repeatedly and continuously. Like that.

【００１２】このように、セル領域を囲む外周部にガー
ドリングを形成する場合には、ガードリング領域までス
ーパージャンクションを形成するようにしても、請求項
１の効果を得ることができる。As described above, when the guard ring is formed in the outer peripheral portion surrounding the cell region, the effect of claim 1 can be obtained even if a super junction is formed up to the guard ring region.

【００１３】請求項４に記載の発明は、請求項１乃至３
に記載の半導体装置の製造方法である。具体的には、請
求項５に示すように、半導体基板の主表面上全面に第１
導電型層を形成し、該第１導電型層に第２導電型不純物
のイオン注入を行ったあと、該第２導電型不純物を活性
化させて第２導電型層を形成することで、半導体基板の
主表面全面に第１導電型層と第２導電型層を形成するこ
とができる。The invention described in claim 4 is the first to third aspects of the present invention.
3. The method for manufacturing a semiconductor device according to (1). Specifically, the first surface is formed on the entire surface of the main surface of the semiconductor substrate.
A semiconductor is formed by forming a conductive type layer, ion-implanting a second conductive type impurity into the first conductive type layer, and then activating the second conductive type impurity to form a second conductive type layer. The first conductivity type layer and the second conductivity type layer can be formed on the entire main surface of the substrate.

【００１４】この場合、請求項６に示すように、第２導
電型層を形成する工程において、第１導電型層のうち第
２導電型不純物をイオン注入する領域に不活性なイオン
種をイオン注入しておき、不活性なイオン種を注入した
のち、第２導電型不純物を活性化させるようにすること
ができる。すなわち、不活性なイオン種によって炭素サ
イトの空孔を無くすことができるため、炭素サイトの空
孔に基づく第２導電型不純物の拡散を抑制することがで
き、第１導電型層と第２導電型層の幅を正確に規定する
ことができる。In this case, in the step of forming the second conductivity type layer, an inert ion species is ionized into a region of the first conductivity type layer where the second conductivity type impurity is ion-implanted. After the implantation and the implantation of the inactive ion species, the second conductivity type impurity can be activated. That is, since the vacancies at the carbon site can be eliminated by the inert ion species, the diffusion of the second conductivity type impurity based on the vacancy at the carbon site can be suppressed, and the first conductivity type layer and the second conductivity type layer can be prevented from diffusing. The width of the mold layer can be precisely defined.

【００１５】なお、上記各手段の括弧内の符号は、後述
する実施形態に記載の具体的手段との対応関係を示すも
のである。The reference numerals in parentheses of the above-mentioned means indicate the correspondence with the concrete means described in the embodiments described later.

【００１６】[0016]

【発明の実施の形態】（第１実施形態）図１に本発明の
第１実施形態におけるスーパージャンクションＭＯＳＦ
ＥＴを示す。この図は半導体装置の素子部を構成するＭ
ＯＳＦＥＴの１ユニットセルを示したものであり、実際
には複数のユニットセル若しくは他の回路素子と共に半
導体装置を構成している。以下、図１に基づいて本実施
形態におけるＭＯＳＦＥＴの構成について説明する。(First Embodiment) FIG. 1 shows a super junction MOSF according to a first embodiment of the present invention.
Indicates ET. This figure shows M which constitutes the element portion of the semiconductor device.
The figure shows one unit cell of the OSFET, and actually constitutes a semiconductor device together with a plurality of unit cells or other circuit elements. Hereinafter, the configuration of the MOSFET according to the present embodiment will be described with reference to FIG.

【００１７】図１に示すように、炭化珪素からなるｎ+
型基板１は上面を主表面１ａとし、主表面１ａの反対面
である下面を裏面１ｂとしている。このｎ+ 型基板１の
主表面１ａの上の全面に、炭化珪素からなるｎ型層２と
ｐ型層３とが延設され、これらｎ型層２とｐ型層３とが
交互に並べられて複数のＰＮ接合が形成されている。こ
れら複数のＰＮ接合がスーパージャンクションを構成し
ている。このスーパージャンクションを構成するＰＮ接
合は、ｎ+型基板１の主表面１ａすべてに形成されてい
る。すなわち、複数のユニットセル若しくは他の回路素
子が形成される領域にもすべてスーパージャンクション
が形成され、これらすべてのスーパージャンクションが
断続せずに繰り返し連続的に繋がった状態となってい
る。As shown in FIG. 1, n + made of silicon carbide
The upper surface of the mold substrate 1 is a main surface 1a, and the lower surface opposite to the main surface 1a is a back surface 1b. An n-type layer 2 and a p-type layer 3 made of silicon carbide extend over the entire surface of main surface 1a of n + -type substrate 1, and these n-type layers 2 and p-type layers 3 are alternately arranged. Thus, a plurality of PN junctions are formed. These plural PN junctions constitute a super junction. The PN junction constituting the super junction is formed on the entire main surface 1a of the n + type substrate 1. In other words, super junctions are all formed in regions where a plurality of unit cells or other circuit elements are formed, and all of these super junctions are connected continuously without interruption.

【００１８】スーパージャンクションの複数のＰＮ接合
を構成する各ｎ型層２とｐ型層３は、同等の厚さ３μｍ
で構成され、ｎ型層２の幅Ｗｎとｐ型層３の幅Ｗｐとは
同等で１μｍとされている。また、ｎ型層２は不純物濃
度が２×１０17ｃｍ-3程度とされており、ｐ型層３は不
純物濃度が２×１０17ｃｍ-3程度とされている。Each of the n-type layers 2 and the p-type layers 3 constituting the plurality of PN junctions of the super junction have an equivalent thickness of 3 μm.
The width Wn of the n-type layer 2 and the width Wp of the p-type layer 3 are equal to 1 μm. The n-type layer 2 has an impurity concentration of about 2 × 10 17 cm −3, and the p-type layer 3 has an impurity concentration of about 2 × 10 17 cm −3 .

【００１９】この濃度と幅は、Ｊｐｎ．Ｊ．Ａｐｐｌ．
Ｐｈｙｓ．Ｖｏｌ．３６（１９９７）ｐｐ ６２５４−
６２６２に記載されていた関係式を満たすように設定す
ればよい。The density and width are determined according to Jpn. J. Appl.
Phys. Vol. 36 (1997) pp 6254-
What is necessary is just to set so that the relational expression described in 6262 may be satisfied.

【００２０】スーパージャンクションを構成する複数の
ＰＮ接合の上には、ｎ+型基板１よりも低い不純物濃度
を有する炭化珪素からなるｎ- 型エピタキシャル層４が
厚さ２μｍ程度で積層されている。このｎ- 型エピ層４
の不純物濃度はｎ型層２の不純物濃度と同等となってい
る。On the plurality of PN junctions constituting the super junction, an n − -type epitaxial layer 4 made of silicon carbide having a lower impurity concentration than n + -type substrate 1 is laminated with a thickness of about 2 μm. This n - type epi layer 4
Is equal to the impurity concentration of the n-type layer 2.

【００２１】ｎ- 型エピ層４の表層部における所定領域
には、所定深さを有するｐ型ベース領域５が形成されて
いる。このｐ- 型ベース領域５はＢをドーパントとして
形成されており、略１×１０17ｃｍ-3以上の濃度となっ
ている。A p-type base region 5 having a predetermined depth is formed in a predetermined region in a surface portion of the n − -type epi layer 4. This p − -type base region 5 is formed using B as a dopant, and has a concentration of about 1 × 10 17 cm −3 or more.

【００２２】また、ｐ型ベース領域５の表層部の所定領
域には、該ベース領域５よりも浅いｎ+ 型ソース領域６
が形成されている。In a predetermined region of the surface layer of the p-type base region 5, an n + -type source region 6 shallower than the base region 5 is provided.
Are formed.

【００２３】さらに、ｎ+ 型ソース領域６とｎ- 型エピ
層２とを繋ぐように、ｐ型ベース領域５の表面部にはｎ
- 型ＳｉＣ層７が延設されている。このｎ- 型ＳｉＣ層
７は、エピタキシャル成長にて形成されたものであり、
エピタキシャル膜の結晶が４Ｈ、６Ｈ、３Ｃ、１５Ｒの
ものを用いる。尚、このｎ- 型ＳｉＣ層７はデバイスの
動作時にチャネル形成層として機能する。以下、ｎ- 型
ＳｉＣ層７を表面チャネル層という。Furthermore, n + -type source region 6 and the n - so as to connect the type epi layer 2, the surface portion of the p-type base region 5 n
The -type SiC layer 7 extends. This n − -type SiC layer 7 is formed by epitaxial growth.
The crystal of the epitaxial film is 4H, 6H, 3C, 15R. The n − -type SiC layer 7 functions as a channel forming layer during operation of the device. Hereinafter, n − -type SiC layer 7 is referred to as a surface channel layer.

【００２４】表面チャネル層７はＮ（窒素）をドーパン
トに用いて形成されており、そのドーパント濃度は、例
えば１×１０15ｃｍ-3〜１×１０17ｃｍ-3程度の低濃度
で、かつ、ｎ- 型エピ層４及びｐ- 型ベース領域５のド
ーパント濃度以下となっている。これにより、低オン抵
抗化が図られている。The surface channel layer 7 is formed using N (nitrogen) as a dopant, and the dopant concentration is as low as about 1 × 10 15 cm −3 to 1 × 10 17 cm −3 , and , N − -type epi layer 4 and p − -type base region 5 are lower than the dopant concentration. Thereby, low on-resistance is achieved.

【００２５】表面チャネル層７の上面およびｎ+ 型ソー
ス領域６の上面には熱酸化にてゲート酸化膜８が形成さ
れている。さらに、ゲート酸化膜８の上にはゲート電極
９が形成されている。A gate oxide film 8 is formed on the upper surface of the surface channel layer 7 and the upper surface of the n + type source region 6 by thermal oxidation. Further, a gate electrode 9 is formed on the gate oxide film 8.

【００２６】また、ｎ+ 型ソース領域６およびｐ型ベー
ス領域５と接するようにソース電極１０が形成されてい
る。また、ｎ+ 型基板１の裏面１ｂには、ドレイン電極
１１が形成されている。A source electrode 10 is formed in contact with n + type source region 6 and p type base region 5. A drain electrode 11 is formed on the back surface 1b of the n + type substrate 1.

【００２７】なお、ｐ型ベース領域５のうちソース電極
１０とコンタクトが取られる部位の下方は、ｐ型ベース
領域５の他の部分よりも接合深さが深くされたディープ
ベース層５ａとなっている。このディープベース層５ａ
は、ｐ型ベース領域５の他の部分よりもｐ型不純物濃度
が高くされており、逆バイアス時に優先的にアバランシ
ェブレークダウンするようになっている。The lower part of the p-type base region 5 below the part in contact with the source electrode 10 is a deep base layer 5a having a junction depth deeper than other parts of the p-type base region 5. I have. This deep base layer 5a
Has a higher p-type impurity concentration than other portions of the p-type base region 5, so that avalanche breakdown occurs preferentially during reverse bias.

【００２８】そして、上記したスーパージャンクション
を構成するＰＮ接合のうちのｐ型層３とｐ型ベース領域
５とが図１とは別断面において、アース接続されてい
る。The p-type layer 3 and the p-type base region 5 of the PN junction constituting the above-mentioned super junction are connected to ground in a section different from that of FIG.

【００２９】このように、各素子部のスーパージャンク
ションを断続させずに連続的に繋げた状態としているた
め、各素子部に確実にスーパージャンクションが備えら
れた状態となり、確実にｐ型ベース領域５及びｎ+型ソ
ース領域６の下方をピンチオフさせることができ、確実
にＭＯＳＦＥＴの耐圧が得られるようにできる。As described above, since the super junctions of the respective element portions are continuously connected without being interrupted, a super junction is reliably provided in each of the element portions, and the p-type base region 5 is surely provided. And pinch-off under the n + -type source region 6, so that the breakdown voltage of the MOSFET can be reliably obtained.

【００３０】上記構成のスーパージャンクションＭＯＳ
ＦＥＴの耐圧及びオン抵抗特性について実験により調べ
た。その結果をそれぞれ図２（ａ）、（ｂ）に示す。The super junction MOS having the above configuration
The breakdown voltage and on-resistance characteristics of the FET were examined by experiments. The results are shown in FIGS. 2A and 2B, respectively.

【００３１】図２（ａ）に示されるように、逆バイアス
時においてドレイン電極１１への印加電圧が１０３７Ｖ
のときにアバランシェブレークダウンが生じ、耐圧が得
られるようになっている。As shown in FIG. 2A, the voltage applied to the drain electrode 11 at the time of reverse bias is 1037 V
In this case, avalanche breakdown occurs, and a withstand voltage can be obtained.

【００３２】一方、図２（ｂ）に示すように、本実施形
態におけるスーパージャンクションＭＯＳＦＥＴはスー
パージャンクションを形成していないＭＯＳＦＥＴと比
べてドレイン電流が大きくなっており、オン抵抗が低減
されていることが判る。On the other hand, as shown in FIG. 2B, the super-junction MOSFET in the present embodiment has a larger drain current and lower on-resistance than a MOSFET without a super-junction. I understand.

【００３３】これは、スーパージャンクションを形成す
ることにより、この領域の不純物濃度を高濃度にするこ
と、つまり低抵抗にすることができるため、オン抵抗を
低減することができるのである。This is because, by forming a super junction, the impurity concentration in this region can be increased, that is, the resistance can be reduced, so that the on-resistance can be reduced.

【００３４】このように、本実施形態によるスーパージ
ャンクションＭＯＳＦＥＴにより、確実にＭＯＳＦＥＴ
の耐圧を得ることができると共に、ＭＯＳＦＥＴのオン
抵抗を低減することができる。As described above, the super-junction MOSFET according to the present embodiment ensures that the MOSFET
And the on-resistance of the MOSFET can be reduced.

【００３５】次に、図１に示すＭＯＳＦＥＴの製造工程
を、図３〜図６に基づいて説明する。Next, a manufacturing process of the MOSFET shown in FIG. 1 will be described with reference to FIGS.

【００３６】〔図３（ａ）に示す工程〕まず、ｎ型４
Ｈ、６Ｈ、３Ｃ、もしくは１５Ｒ−ＳｉＣ基板、すなわ
ちｎ+ 型基板１を用意する。このｎ+ 型基板１は厚さが
４００μｍであり、主表面１ａが（０００１）Ｓｉ面、
又は、（１１２−０）ａ面となっている。[Step shown in FIG. 3A] First, the n-type 4
An H, 6H, 3C, or 15R-SiC substrate, that is, an n + type substrate 1 is prepared. This n + -type substrate 1 has a thickness of 400 μm, and has a main surface 1a of (0001) Si plane,
Or, it is the (112-0) a plane.

【００３７】〔図３（ｂ）に示す工程〕ｎ+型基板１の
主表面１ａに、厚さ３μｍのｎ型層２をエピタキシャル
成長させる。このとき、ｎ型層２は下地のｎ+型基板１
と同様の結晶が得られ、ｎ型４Ｈ、６Ｈ、３Ｃもしくは
１５Ｒ−ＳｉＣ層となる。[Step shown in FIG. 3B] An n-type layer 2 having a thickness of 3 μm is epitaxially grown on the main surface 1a of the n + -type substrate 1. At this time, n-type layer 2 underlying n + -type substrate 1
A crystal similar to the above is obtained, and becomes an n-type 4H, 6H, 3C or 15R-SiC layer.

【００３８】〔図３（ｃ）に示す工程〕そして、ｎ型層
２の表面にｐ型層形成予定領域が開口するマスクを配置
し、ＢやＡｌ等のｐ型不純物をイオン注入したのち、ｐ
型不純物を熱処理によって活性化させてｐ型層３を形成
する。このとき、ｐ型層３をｎ+型基板１の全面（若し
くは素子が形成されダイシングによって除去される不要
部分とならない領域すべて）に形成する。[Step shown in FIG. 3C] Then, a mask is formed on the surface of the n-type layer 2 so as to open a region where a p-type layer is to be formed, and p-type impurities such as B and Al are ion-implanted. p
The p-type layer 3 is formed by activating the type impurities by heat treatment. At this time, the p-type layer 3 is formed on the entire surface of the n + -type substrate 1 (or on all regions where elements are formed and are not unnecessary portions removed by dicing).

【００３９】これにより、ｎ+型基板１の全面にｎ型層
２とｐ型層３とが交互に並べられたスーパージャンクシ
ョンが形成される。このため、このあとに形成する各素
子部の形成時にマスクずれが生じても、各素子部のそれ
ぞれに必ずスーパージャンクションが形成されているこ
とになる。Thus, a super junction in which the n-type layers 2 and the p-type layers 3 are alternately arranged on the entire surface of the n + type substrate 1 is formed. For this reason, even when a mask shift occurs during the formation of each element portion to be formed thereafter, a super junction is always formed in each element portion.

【００４０】またこのとき、ＢやＡｌを注入する前にＣ
（炭素）等の不活性なイオン種を注入してもよい。この
ように、ｐ型不純物を活性化させる前にＣ等の不活性な
イオン種を注入しておくことにより、エピタキシャル成
長時等にｎ型層２に形成された炭素サイトの空孔内に不
活性なイオン種が入り込み、ｎ型層２の炭素サイトの空
孔をなくすことができるため、炭素サイトの空孔に起因
するｐ型不純物の拡散が抑制され、ｎ型層２とｐ型層３
との幅を正確に規定することができる。At this time, before the implantation of B or Al, C
An inert ion species such as (carbon) may be implanted. As described above, by implanting an inactive ion species such as C before activating the p-type impurity, the inactive holes in the carbon sites formed in the n-type layer 2 during the epitaxial growth and the like are formed. Ionic species can enter and the vacancies at the carbon sites of the n-type layer 2 can be eliminated, so that the diffusion of p-type impurities due to the vacancies at the carbon sites is suppressed, and the n-type layer 2 and the p-type layer 3
Can be accurately defined.

【００４１】〔図４（ａ）に示す工程〕次に、スーパー
ジャンクションを構成するｎ型層２とｐ型層３の上に、
厚さ５μｍ程度のｎ-型エピ層４をエピタキシャル成長
させる。このとき、ｎ-型エピ層４は下地のｎ型層２及
びｐ型層３と同様の結晶が得られ、ｎ型４Ｈ、６Ｈ、３
Ｃ、もしくは１５Ｒ−ＳｉＣ層となる。[Step shown in FIG. 4A] Next, on the n-type layer 2 and the p-type layer 3 constituting the super junction,
An n − -type epi layer 4 having a thickness of about 5 μm is epitaxially grown. At this time, the same crystal as that of the underlying n-type layer 2 and p-type layer 3 is obtained from the n − -type epi layer 4 and
C or a 15R-SiC layer.

【００４２】〔図４（ｂ）に示す工程〕ｎ- 型エピ層４
の上の所定領域にＬＴＯ（Ｌｏｗ Ｔｅｍｐｅｒａｔｕ
ｒｅＯｘｉｄａｔｉｏｎ）膜２０を配置し、これをマス
クとしてＢ若しくはＡｌ等のｐ型不純物のイオン注入を
行う。このとき、イオン注入条件は、温度が７００℃、
ドーズ量が１×１０16ｃｍ-2としている。これにより、
ｎ- 型エピ層４の表面から所定深さの位置に、Ｂよりな
るボックスプロファイルが形成される。[Step shown in FIG. 4B] n - type epi layer 4
LTO (Low Temperatu)
A reoxidation film 20 is disposed, and ions of a p-type impurity such as B or Al are implanted using the film 20 as a mask. At this time, the ion implantation conditions are a temperature of 700 ° C.
The dose is 1 × 10 16 cm −2 . This allows
A box profile made of B is formed at a position at a predetermined depth from the surface of the n − -type epi layer 4.

【００４３】その後、熱処理として、１６００℃、３０
分間の活性化アニールを施し、Ｂを活性化させてｐ型ベ
ース領域５を形成する。Thereafter, as heat treatment, 1600 ° C., 30
Then, activation annealing is performed for a minute to activate B to form the p-type base region 5.

【００４４】このとき、上記ｐ型層３の形成と同様に、
ｐ型ベース領域５とする部分にＣ等の不活性なイオン種
をイオン注入しておけば、ｐ型ベース領域形成用に注入
されたｐ型不純物の熱拡散が抑制され、ｐ型ベース領域
５の形成位置が正確に規定される。これにより、ｐ型ベ
ース領域５の間が狭くなることを防止でき、Ｊ−ＦＥＴ
部の幅が狭まらないようにすることができる。At this time, similarly to the formation of the p-type layer 3,
If an inert ion species such as C is ion-implanted into a portion to be the p-type base region 5, thermal diffusion of the p-type impurity implanted for forming the p-type base region is suppressed, and the p-type base region 5 Is precisely defined. Thereby, the space between the p-type base regions 5 can be prevented from becoming narrow, and the J-FET
The width of the portion can be prevented from being reduced.

【００４５】〔図５（ａ）に示す工程〕ＬＴＯ膜２０を
除去したのち、ｐ型ベース領域５を含むｎ- 型エピ層４
の表面に、例えば０．３μｍ以下の膜厚で表面チャネル
層７をエピタキシャル成長させる。[Step shown in FIG. 5A] After removing the LTO film 20, the n − -type epi layer 4 including the p-type base region 5 is removed.
The surface channel layer 7 is epitaxially grown to a thickness of, for example, 0.3 μm or less on the surface of the substrate.

【００４６】このとき、縦型パワーＭＯＳＦＥＴをノー
マリオフ型にするために、表面チャネル層７の厚み（膜
厚）を、ゲート電極９に電圧を印加していない時におけ
るｐ型ベース領域５から表面チャネル層７に広がる空乏
層の伸び量と、ゲート酸化膜８から表面チャネル層７に
広がる空乏層の伸び量との和よりも小さくなるようにし
ている。At this time, in order to make the vertical power MOSFET a normally-off type, the thickness (film thickness) of the surface channel layer 7 is changed from the p-type base region 5 when the voltage is not applied to the gate electrode 9 to the surface channel. It is set to be smaller than the sum of the extension amount of the depletion layer extending to the layer 7 and the extension amount of the depletion layer extending from the gate oxide film 8 to the surface channel layer 7.

【００４７】具体的には、ｐ型ベース領域５から表面チ
ャネル層７に広がる空乏層の伸び量は、表面チャネル層
７とｐ型ベース領域５とのＰＮ接合のビルトイン電圧に
よって決定され、ゲート酸化膜８から表面チャネル層７
に広がる空乏層の伸び量は、ゲート酸化膜８の電荷及び
ゲート電極９（金属）と表面チャネル層７（半導体）と
の仕事関数差によって決定されるため、これらに基づい
て表面チャネル層７の膜厚を決定している。Specifically, the extension of the depletion layer extending from p-type base region 5 to surface channel layer 7 is determined by the built-in voltage of the PN junction between surface channel layer 7 and p-type base region 5, and the gate oxide From film 8 to surface channel layer 7
The amount of extension of the depletion layer that spreads is determined by the charge of the gate oxide film 8 and the work function difference between the gate electrode 9 (metal) and the surface channel layer 7 (semiconductor). The film thickness is determined.

【００４８】このようなノーマリオフ型の縦型パワーＭ
ＯＳＦＥＴは、故障などによってゲート電極に電圧が印
加できないような状態となっても、電流が流れないよう
にすることができるため、ノーマリオン型のものと比べ
て安全性を確保することができる。Such a normally-off type vertical power M
The OSFET can prevent a current from flowing even when a voltage cannot be applied to the gate electrode due to a failure or the like, so that safety can be ensured as compared with a normally-on type.

【００４９】〔図５（ｂ）に示す工程〕表面チャネル層
７の上の所定領域にＬＴＯ膜２１を配置したのち、これ
をマスクとしてＢ若しくはＡｌ等のｐ型不純物をイオン
注入し、ディープベース層５ａを形成する。[Step shown in FIG. 5B] After arranging the LTO film 21 in a predetermined region on the surface channel layer 7, a p-type impurity such as B or Al is ion-implanted using the LTO film 21 as a mask to form a deep base. The layer 5a is formed.

【００５０】〔図６（ａ）に示す工程〕表面チャネル層
７の上の所定領域にＬＴＯ膜２２を配置したのち、これ
をマスクとしてＮ（窒素）等のｎ型不純物をイオン注入
し、ｎ+ 型ソース領域６を形成する。このときのイオン
注入条件は、７００℃、ドーズ量は１×１０15ｃｍ-2と
している。[Step shown in FIG. 6 (a)] After an LTO film 22 is arranged in a predetermined region on the surface channel layer 7, an n-type impurity such as N (nitrogen) is ion-implanted using the LTO film 22 as a mask. A + type source region 6 is formed. The ion implantation conditions at this time are 700 ° C. and the dose is 1 × 10 15 cm −2 .

【００５１】〔図６（ｂ）に示す工程〕ＬＴＯ膜２２を
除去した後、基板の上にウェット酸化（Ｈ2 ＋Ｏ2 によ
るパイロジェニック法を含む）によりゲート酸化膜８を
形成する。このとき、雰囲気温度は１０８０℃とする。
その後、ゲート酸化膜８の上にポリシリコンからなるゲ
ート電極９をＬＰＣＶＤにより堆積する。このときの成
膜温度は６００℃とする。そして、ゲート電極９及びゲ
ート酸化膜８の不要部分を除去する。[Step shown in FIG. 6B] After the LTO film 22 is removed, a gate oxide film 8 is formed on the substrate by wet oxidation (including a pyrogenic method using H 2 + O 2 ). At this time, the ambient temperature is 1080 ° C.
Thereafter, a gate electrode 9 made of polysilicon is deposited on the gate oxide film 8 by LPCVD. The film formation temperature at this time is 600 ° C. Then, unnecessary portions of the gate electrode 9 and the gate oxide film 8 are removed.

【００５２】この後、図示しないがＬＴＯよりなる絶縁
膜を形成してゲート酸化膜８を覆ったのち、絶縁膜にコ
ンタクトホールを形成し、室温での金属スパッタリング
によりソース電極１０及びドレイン電極１１を配置し、
成膜後に１０００℃のアニールを行う。このようにし
て、図１に示す縦型パワーＭＯＳＦＥＴが完成する。Thereafter, although not shown, an insulating film made of LTO is formed to cover the gate oxide film 8, then a contact hole is formed in the insulating film, and the source electrode 10 and the drain electrode 11 are formed by metal sputtering at room temperature. Place,
After the film formation, annealing at 1000 ° C. is performed. Thus, the vertical power MOSFET shown in FIG. 1 is completed.

【００５３】（第２実施形態）本実施形態では、第１実
施形態に示した縦型パワーＭＯＳＦＥＴの周囲にガード
リングやＥＱＲを配置する場合について説明する。図７
に、ガードリング及びＥＱＲを備えた縦型パワーＭＯＳ
ＦＥＴの断面構成を示す。(Second Embodiment) In this embodiment, a case will be described in which a guard ring and an EQR are arranged around the vertical power MOSFET shown in the first embodiment. FIG.
, Vertical power MOS with guard ring and EQR
1 shows a cross-sectional configuration of an FET.

【００５４】図７に示すように、図１と同様の構成のＭ
ＯＳＦＥＴが備えられている。このＭＯＳＦＥＴから離
間された位置において、ｎ-型エピ層４の表層部には複
数のｐ型層１２が所定間隔おきに配置されている。この
ｐ型層１２はＭＯＳＦＥＴの周囲を囲むようにリング状
に形成されている。これら複数のｐ型層１２がガードリ
ングを構成している。また、ガードリングを構成するｐ
型層１２のリング外側にはｎ-型エピ層４の表層部に形
成されたｎ型層１３及びｎ型層１３の上に形成された電
極１４とからなるＥＱＲが備えられている。As shown in FIG. 7, M has the same configuration as FIG.
An OSFET is provided. At a position separated from the MOSFET, a plurality of p-type layers 12 are arranged at predetermined intervals on the surface of the n − -type epi layer 4. This p-type layer 12 is formed in a ring shape so as to surround the periphery of the MOSFET. These p-type layers 12 constitute a guard ring. In addition, p forming the guard ring
An EQR comprising an n-type layer 13 formed on the surface of the n − -type epi layer 4 and an electrode 14 formed on the n-type layer 13 is provided outside the ring of the mold layer 12.

【００５５】そして、ＭＯＳＦＥＴが形成されたセル領
域、ガードリングが形成されたガードリング領域、及び
ＥＱＲが形成された領域全域において、ｎ+型基板１の
主表面１ａの上には、全面にｎ型層２及びｐ型層３から
なるスーパージャンクションが構成されている。このよ
うに、ガードリングやＥＱＲ等のＭＯＳＦＥＴとは異な
る部分を形成する場合においては、これらガードリング
やＥＱＲが形成される領域にもスーパージャンクション
を形成するようにしている。In the cell region where the MOSFET is formed, the guard ring region where the guard ring is formed, and the entire region where the EQR is formed, the entire surface of the main surface 1a of the n + type substrate 1 is n A super junction composed of the mold layer 2 and the p-type layer 3 is configured. As described above, when a portion different from a MOSFET such as a guard ring or an EQR is formed, a super junction is also formed in a region where the guard ring or the EQR is formed.

【００５６】このように、ｎ+型基板１の全面にスーパ
ージャンクションを構成するｎ型層２とｐ型層３を交互
に配置することで、ＭＯＳＦＥＴ等の形成時においてマ
スクずれ等が発生しても、ＭＯＳＦＥＴが形成される領
域に必ずスーパージャンクションが配置されることにな
る。このため、確実にｐ型ベース領域５及びソース領域
６下をピンチオフさせることができ、確実にＭＯＳＦＥ
Ｔの耐圧が得られるようにできる。As described above, by disposing the n-type layers 2 and the p-type layers 3 constituting the super junction alternately over the entire surface of the n + -type substrate 1, a mask shift or the like occurs at the time of forming a MOSFET or the like. Also, a super junction is always arranged in a region where a MOSFET is formed. Therefore, pinch-off under the p-type base region 5 and the source region 6 can be ensured, and the MOSFE can be surely ensured.
A withstand voltage of T can be obtained.

【００５７】（他の実施形態）上記実施形態では、スー
パージャンクションを構成するｎ型層２とｐ型層３とが
交互に配置されることについて説明したが、ｎ型層２と
ｐ型層３とが交互に配置され、これらによって形成され
るＰＮ接合によってスーパージャンクションがピンチオ
フされるような構成であればどのようなレイアウトであ
ってもよい。(Other Embodiments) In the above embodiment, the description has been given of the case where the n-type layers 2 and the p-type layers 3 constituting the super junction are alternately arranged. Are alternately arranged, and any layout may be used as long as the super junction is pinched off by the PN junction formed by them.

【００５８】例えば、ｎ型層２とｐ型層３とをストライ
プ状に配置してもよく、ｎ+型基板１の主表面１ａの垂
直方向から見てｎ型層２とｐ型層３とが共に六角形状に
なるようにし、一断面を見るとｎ型層２とｐ型層３とが
交互に配置されるようにしてもよい。For example, the n-type layer 2 and the p-type layer 3 may be arranged in a stripe pattern, and the n-type layer 2 and the p-type layer 3 are viewed from the vertical direction of the main surface 1a of the n + -type substrate 1. May be hexagonal, and the n-type layers 2 and the p-type layers 3 may be arranged alternately in one cross section.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の第１実施形態におけるスーパージャン
クションＭＯＳＦＥＴの断面構成を示す図である。FIG. 1 is a diagram showing a cross-sectional configuration of a super junction MOSFET according to a first embodiment of the present invention.

【図２】（ａ）は、図１のＭＯＳＦＥＴの耐圧を示す特
性図であり、（ｂ）は図１のＭＯＳＦＥＴのオン抵抗を
示す特性図である。2A is a characteristic diagram showing the withstand voltage of the MOSFET of FIG. 1, and FIG. 2B is a characteristic diagram showing the on-resistance of the MOSFET of FIG.

【図３】図１に示す縦型パワーＭＯＳＦＥＴの製造工程
を示す図である。FIG. 3 is a view showing a manufacturing process of the vertical power MOSFET shown in FIG. 1;

【図４】図３に続く縦型パワーＭＯＳＦＥＴの製造工程
を示す図である。FIG. 4 is a view illustrating a manufacturing process of the vertical power MOSFET following FIG. 3;

【図５】図４に続く縦型パワーＭＯＳＦＥＴの製造工程
を示す図である。FIG. 5 is a diagram showing a manufacturing step of the vertical power MOSFET following FIG. 4;

【図６】図５に続く縦型パワーＭＯＳＦＥＴの製造工程
を示す図である。FIG. 6 is a view illustrating a manufacturing process of the vertical power MOSFET following FIG. 5;

【図７】本発明の第２実施形態における縦型パワーＭＯ
ＳＦＥＴにガードリング及びＥＱＲを備えた場合の断面
構成を示す図である。FIG. 7 is a vertical power MO according to a second embodiment of the present invention.
FIG. 4 is a diagram illustrating a cross-sectional configuration when an SFET is provided with a guard ring and an EQR.

【図８】従来のスーパージャンクションを備えたＭＯＳ
ＦＥＴの断面構成を示す図である。FIG. 8 shows a conventional MOS having a super junction.
FIG. 3 is a diagram illustrating a cross-sectional configuration of an FET.

【符号の説明】[Explanation of symbols]

１…ｎ+型基板、２…ｎ型層、３…ｐ型層、４…ｎ-型エ
ピ層、５…ｐ型ベース領域、６…ｎ+型ソース領域、７
…表面チャネル層、８…ゲート酸化膜、９…ゲート電
極、１０…ソース電極、１１…ドレイン電極。DESCRIPTION OF SYMBOLS 1 ... n + type substrate, 2 ... n-type layer, 3 ... p-type layer, 4 ... n - type epi layer, 5 ... p-type base region, 6 ... n + type source region, 7
... surface channel layer, 8 ... gate oxide film, 9 ... gate electrode, 10 ... source electrode, 11 ... drain electrode.

Claims (6)

【特許請求の範囲】[Claims] 【請求項１】 主表面（１ａ）及び該主表面と反対面
（１ｂ）である裏面を有し、炭化珪素よりなる第１導電
型の半導体基板（１）と、 前記半導体基板の前記主表面上に形成され、該主表面上
において複数の第１導電型層（２）と複数の第２導電型
層（３）とが交互に配置されて形成された複数のＰＮ接
合からなるスーパージャンクションと、 前記スーパージャンクションの上に形成され、前記半導
体基板よりも高抵抗な炭化珪素よりなる第１導電型の半
導体層（４）と、 前記半導体層の表層部の所定領域に形成され、所定深さ
を有する第２導電型のベース領域（５）と、 前記ベース領域の表層部の所定領域に形成され、該ベー
ス領域の深さよりも浅い第１導電型のソース領域（６）
と、 前記ベース領域のうち、前記半導体層及び前記ソース領
域に挟まれた部分の上に形成されたゲート絶縁膜（８）
と、 前記ゲート絶縁膜の上に形成されたゲート電極（９）
と、 前記ベース領域及び前記ソース領域に接触するように形
成されたソース電極（１０）と、 前記半導体基板の前記裏面に形成されたドレイン電極
（１１）とを備え、 前記スーパージャンクションを構成する前記第１導電型
層及び前記第２導電型層は、前記半導体基板の前記主表
面全面に形成されていることを特徴とする炭化珪素半導
体装置。1. A semiconductor substrate (1) of a first conductivity type having a main surface (1a) and a back surface opposite to the main surface (1b) and made of silicon carbide; and the main surface of the semiconductor substrate. A super junction composed of a plurality of PN junctions formed on the main surface and having a plurality of first conductivity type layers (2) and a plurality of second conductivity type layers (3) alternately arranged on the main surface; A first conductivity type semiconductor layer (4) formed of silicon carbide having a higher resistance than the semiconductor substrate and formed on the super junction; a predetermined depth formed in a predetermined region of a surface layer portion of the semiconductor layer; A second conductivity type base region (5) having a first conductivity type, and a first conductivity type source region (6) formed in a predetermined region of the surface layer of the base region and shallower than the depth of the base region.
A gate insulating film formed on a portion of the base region sandwiched between the semiconductor layer and the source region;
And a gate electrode (9) formed on the gate insulating film.
A source electrode (10) formed to contact the base region and the source region; and a drain electrode (11) formed on the back surface of the semiconductor substrate, wherein the super junction is formed. A silicon carbide semiconductor device, wherein the first conductivity type layer and the second conductivity type layer are formed over the entire main surface of the semiconductor substrate. 【請求項２】 主表面（１ａ）と該主表面の反対面であ
る裏面（１ｂ）を有し、炭化珪素よりなる第１導電型の
半導体基板（１）と、 前記半導体基板の前記主表面側に形成され前記半導体基
板よりも高抵抗な第１導電型の半導体層（４）と、 前記半導体層の表層部の所定領域に形成され、所定深さ
を有する第２導電型のベース領域（５）と、 前記ベース領域の表層部の所定領域に形成され、該ベー
ス領域の深さよりも浅い第１導電型のソース領域（６）
と、 前記ベース領域のうち、前記半導体層及び前記ソース領
域に挟まれた部分の上に形成されたゲート絶縁膜（８）
と、 前記ゲート絶縁膜の上に形成されたゲート電極（９）
と、 前記ベース領域及び前記ソース領域に接触するように形
成されたソース電極（１０）と、 前記半導体基板の前記裏面に形成されたドレイン電極
（１１）と、を有してなるＦＥＴをユニットセルとし、
該ユニットセルが複数形成されるセル領域において、 前記半導体基板と前記半導体層との間には、複数の第１
導電型層（２）と複数の第２導電型層（３）とが交互に
配置されて形成された複数のＰＮ接合からなるスーパー
ジャンクションが備えられており、前記セル領域下部を
覆うように該スーパージャンクションを構成する前記第
１導電型層及び前記第２導電型層が繰り返し連続的につ
ながっていることを特徴とする炭化珪素半導体装置。2. A semiconductor substrate (1) of a first conductivity type having a main surface (1a) and a back surface (1b) opposite to the main surface and made of silicon carbide; and the main surface of the semiconductor substrate. A first conductivity type semiconductor layer (4) formed on the semiconductor substrate side and having a higher resistance than the semiconductor substrate; and a second conductivity type base region (2) formed in a predetermined region of a surface layer portion of the semiconductor layer and having a predetermined depth. 5) a first conductivity type source region (6) formed in a predetermined region of the surface layer of the base region and shallower than the depth of the base region;
A gate insulating film formed on a portion of the base region sandwiched between the semiconductor layer and the source region;
And a gate electrode (9) formed on the gate insulating film.
A source electrode (10) formed to be in contact with the base region and the source region; and a drain electrode (11) formed on the back surface of the semiconductor substrate. age,
In a cell region where a plurality of the unit cells are formed, a plurality of first cells are provided between the semiconductor substrate and the semiconductor layer.
A super junction composed of a plurality of PN junctions formed by alternately arranging conductive type layers (2) and a plurality of second conductive type layers (3) is provided, and covers a lower portion of the cell region. A silicon carbide semiconductor device, wherein the first conductivity type layer and the second conductivity type layer forming a super junction are repeatedly and continuously connected. 【請求項３】 主表面（１ａ）と該主表面の反対面であ
る裏面（１ｂ）を有し、炭化珪素よりなる第１導電型の
半導体基板（１）と、 前記半導体基板の前記主表面側に形成され前記半導体基
板よりも高抵抗な第１導電型の半導体層（４）と、 前記半導体層の表層部の所定領域に形成され、所定深さ
を有する第２導電型のベース領域（５）と、 前記ベース領域の表層部の所定領域に形成され、該ベー
ス領域の深さよりも浅い第１導電型のソース領域（６）
と、 前記ベース領域のうち、前記半導体層及び前記ソース領
域に挟まれた部分の上に形成されたゲート絶縁膜（８）
と、 前記ゲート絶縁膜の上に形成されたゲート電極（９）
と、 前記ベース領域及び前記ソース領域に接触するように形
成されたソース電極（１０）と、 前記半導体基板の前記裏面に形成されたドレイン電極
（１１）と、を有してなるＦＥＴが形成されるセル領域
と、 該セル領域から所定間隔離間して該セル領域を囲むよう
に、前記半導体層の表層部に形成された複数の第２導電
型のウェル領域からなるガードリング領域と、を備え、 前記セル領域及び前記ガードリング領域の全域におい
て、前記半導体基板と前記半導体層との間には、複数の
第１導電型（２）と複数の第２導電型層（３）とが交互
に配置されて形成された複数のＰＮ接合からなるスーパ
ージャンクションが備えられており、該スーパージャン
クションを構成する前記第１導電型層及び前記第２導電
型層が繰り返し連続的につながっていることを特徴とす
る炭化珪素半導体装置。3. A semiconductor substrate (1) of a first conductivity type having a main surface (1a) and a back surface (1b) opposite to the main surface and made of silicon carbide; and the main surface of the semiconductor substrate. A first conductivity type semiconductor layer (4) formed on the semiconductor substrate side and having a higher resistance than the semiconductor substrate; and a second conductivity type base region (2) formed in a predetermined region of a surface layer portion of the semiconductor layer and having a predetermined depth. 5) a first conductivity type source region (6) formed in a predetermined region of the surface layer of the base region and shallower than the depth of the base region;
A gate insulating film formed on a portion of the base region sandwiched between the semiconductor layer and the source region;
And a gate electrode (9) formed on the gate insulating film.
And a source electrode (10) formed so as to contact the base region and the source region, and a drain electrode (11) formed on the back surface of the semiconductor substrate. And a guard ring region formed of a plurality of second conductivity type well regions formed in a surface portion of the semiconductor layer so as to surround the cell region at a predetermined distance from the cell region. A plurality of first conductivity type (2) and a plurality of second conductivity type layers (3) are alternately provided between the semiconductor substrate and the semiconductor layer in the entire area of the cell region and the guard ring region. A super junction comprising a plurality of PN junctions arranged and formed is provided, and the first conductivity type layer and the second conductivity type layer forming the super junction are repeatedly and continuously connected. A silicon carbide semiconductor device, characterized in that: 【請求項４】 主表面（１ａ）と該主表面の反対面であ
る裏面（１ｂ）を有した炭化珪素よりなる第１導電型の
半導体基板（１）を用意する工程と、 前記半導体基板の前記主表面上に第１導電型層（２）及
び第２導電型層（３）を交互に配置し、複数のＰＮ接合
からなるスーパージャンクションを形成する工程と、 前記スーパージャンクション上に前記半導体基板よりも
高抵抗な第１導電型の半導体層（４）を形成する工程
と、 前記半導体層の表層部の所定領域に、所定深さを有する
第２導電型のベース領域（５）を形成する工程と、 前記ベース領域の表層部の所定領域に、該ベース領域の
深さよりも浅い第１導電型のソース領域（６）を形成す
る工程と、 前記ベース領域のうち、前記半導体層及び前記ソース領
域に挟まれた部分の上にゲート絶縁膜（８）を形成する
工程と、 前記ゲート絶縁膜の上にゲート電極（９）を形成する工
程と、 前記ベース領域及び前記ソース領域に接触するようにソ
ース電極（１０）を形成する工程と、 前記半導体基板の前記裏面にドレイン電極（１１）を形
成する工程とを有し、 前記スーパージャンクションを形成する工程では、該ス
ーパージャンクションを構成する前記第１導電型層及び
前記第２導電型層が前記半導体基板の前記主表面全面に
形成されるようにすることを特徴とする炭化珪素半導体
装置の製造方法。4. A step of preparing a semiconductor substrate (1) of a first conductivity type made of silicon carbide having a main surface (1a) and a back surface (1b) opposite to the main surface; Forming a super junction composed of a plurality of PN junctions by alternately disposing first conductivity type layers (2) and second conductivity type layers (3) on the main surface; and forming the semiconductor substrate on the super junction. Forming a first conductivity type semiconductor layer (4) having a higher resistance than that; and forming a second conductivity type base region (5) having a predetermined depth in a predetermined region of a surface portion of the semiconductor layer. Forming a first conductivity type source region (6) shallower than a depth of the base region in a predetermined region of a surface portion of the base region; and forming the semiconductor layer and the source in the base region. Click on the area between the Forming a gate electrode (9) on the gate insulating film; forming a source electrode (10) in contact with the base region and the source region. And a step of forming a drain electrode (11) on the back surface of the semiconductor substrate. In the step of forming the super junction, the first conductivity type layer and the second conductive layer forming the super junction are formed. A method for manufacturing a silicon carbide semiconductor device, wherein a mold layer is formed over the entire main surface of the semiconductor substrate. 【請求項５】 前記スーパージャンクションを形成する
工程は、前記半導体基板の前記主表面上全面に前記第１
導電型層を形成する工程と、 前記第１導電型層に第２導電型不純物のイオン注入を行
ったあと、該第２導電型不純物を活性化させ、前記第２
導電型層を形成する工程と、を有していることを特徴と
する請求項４に記載の炭化珪素半導体装置の製造方法。5. The step of forming a super junction comprises forming the first junction on the entire surface of the main surface of the semiconductor substrate.
Forming a conductive type layer; and ion-implanting a second conductive type impurity into the first conductive type layer, and then activating the second conductive type impurity to form the second conductive type impurity.
The method of manufacturing a silicon carbide semiconductor device according to claim 4, further comprising: forming a conductive type layer. 【請求項６】 前記第２導電型層を形成する工程では、
前記第１導電型層のうち前記第２導電型不純物をイオン
注入する領域に不活性なイオン種をイオン注入する工程
を有し、 該不活性なイオン種を注入したのち、前記第２導電型不
純物を活性化させることを特徴とする請求項５に記載の
炭化珪素半導体装置の製造方法。6. The step of forming the second conductivity type layer,
A step of ion-injecting an inert ion species into a region of the first conductivity type layer into which the second conductivity-type impurity is ion-implanted; The method of manufacturing a silicon carbide semiconductor device according to claim 5, wherein the impurity is activated.
JP32693399A 1999-11-17 1999-11-17 Silicon carbide semiconductor device Expired - Fee Related JP4450122B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP32693399A JP4450122B2 (en) 1999-11-17 1999-11-17 Silicon carbide semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32693399A JP4450122B2 (en) 1999-11-17 1999-11-17 Silicon carbide semiconductor device

Publications (2)

Publication Number Publication Date
JP2001144292A true JP2001144292A (en) 2001-05-25
JP4450122B2 JP4450122B2 (en) 2010-04-14

Family

ID=18193400

Family Applications (1)

Application Number Title Priority Date Filing Date
JP32693399A Expired - Fee Related JP4450122B2 (en) 1999-11-17 1999-11-17 Silicon carbide semiconductor device

Country Status (1)

Country Link
JP (1) JP4450122B2 (en)

Cited By (56)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001196602A (en) * 2000-01-12 2001-07-19 Hitachi Ltd Electrostatic induction transistor
JP2003069040A (en) * 2001-08-29 2003-03-07 Denso Corp Silicon carbide semiconductor device and manufacturing method thereof
JP2003115589A (en) * 2001-10-03 2003-04-18 Fuji Electric Co Ltd Semiconductor device and manufacturing method
JP2003209123A (en) * 2002-01-11 2003-07-25 Sumitomo Electric Ind Ltd Vertical jfet (junction field-effect transistor) and method of manufacturing the same
WO2003065459A1 (en) * 2002-01-28 2003-08-07 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
JP2003273355A (en) * 2002-03-18 2003-09-26 Toshiba Corp Semiconductor element and method for manufacturing the same
JP2003277193A (en) * 2002-03-22 2003-10-02 Toyota Central Res & Dev Lab Inc SiC WAFER WITH EPITAXIAL FILM, METHOD FOR PRODUCING THE SAME, AND SiC ELECTRONIC DEVICE
US6639260B2 (en) * 2000-12-18 2003-10-28 Denso Corporation Semiconductor device having a vertical semiconductor element
JP2003321298A (en) * 2002-04-30 2003-11-11 Toyota Central Res & Dev Lab Inc SiC SINGLE CRYSTAL AND METHOD FOR PRODUCING THE SAME, SiC WAFER WITH EPITAXIAL FILM AND METHOD FOR PRODUCING THE SAME, AND SiC ELECTRONIC DEVICE
WO2004010489A1 (en) * 2002-07-24 2004-01-29 Sumitomo Electric Industries, Ltd. Vertical junction field effect transistor and method for fabricating the same
JP2004079631A (en) * 2002-08-12 2004-03-11 Sumitomo Electric Ind Ltd Vertical junction field effect transistor and its manufacturing method
US6710418B1 (en) 2002-10-11 2004-03-23 Fairchild Semiconductor Corporation Schottky rectifier with insulation-filled trenches and method of forming the same
US6710403B2 (en) 2002-07-30 2004-03-23 Fairchild Semiconductor Corporation Dual trench power MOSFET
US6713813B2 (en) 2001-01-30 2004-03-30 Fairchild Semiconductor Corporation Field effect transistor having a lateral depletion structure
JP2004147472A (en) * 2002-10-28 2004-05-20 Matsushita Electric Ind Co Ltd Direct current-to-alternating current converter for photovoltaic power generation
US6803626B2 (en) 2002-07-18 2004-10-12 Fairchild Semiconductor Corporation Vertical charge control semiconductor device
US6818513B2 (en) 2001-01-30 2004-11-16 Fairchild Semiconductor Corporation Method of forming a field effect transistor having a lateral depletion structure
US6940110B2 (en) 2002-11-29 2005-09-06 Matsushita Electric Industrial Co., Ltd. SiC-MISFET and method for fabricating the same
JP2007273856A (en) * 2006-03-31 2007-10-18 Toyota Central Res & Dev Lab Inc Semiconductor device
JP2009032919A (en) * 2007-07-27 2009-02-12 Sumitomo Electric Ind Ltd Oxide film field-effect transistor and manufacturing method therefor
JP2009032921A (en) * 2007-07-27 2009-02-12 Sumitomo Electric Ind Ltd Oxide film field-effect transistor and manufacturing method therefor
JP2009194164A (en) * 2008-02-14 2009-08-27 Sumitomo Electric Ind Ltd Insulation gate type field-effect transistor and manufacturing method therefor
US7652326B2 (en) 2003-05-20 2010-01-26 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
US7655981B2 (en) 2003-11-28 2010-02-02 Fairchild Korea Semiconductor Ltd. Superjunction semiconductor device
US7713822B2 (en) 2006-03-24 2010-05-11 Fairchild Semiconductor Corporation Method of forming high density trench FET with integrated Schottky diode
US7732876B2 (en) 2004-08-03 2010-06-08 Fairchild Semiconductor Corporation Power transistor with trench sinker for contacting the backside
US7745289B2 (en) 2000-08-16 2010-06-29 Fairchild Semiconductor Corporation Method of forming a FET having ultra-low on-resistance and low gate charge
US7772668B2 (en) 2007-12-26 2010-08-10 Fairchild Semiconductor Corporation Shielded gate trench FET with multiple channels
US7799636B2 (en) 2003-05-20 2010-09-21 Fairchild Semiconductor Corporation Power device with trenches having wider upper portion than lower portion
US7859047B2 (en) 2006-06-19 2010-12-28 Fairchild Semiconductor Corporation Shielded gate trench FET with the shield and gate electrodes connected together in non-active region
US7936008B2 (en) 2003-12-30 2011-05-03 Fairchild Semiconductor Corporation Structure and method for forming accumulation-mode field effect transistor with improved current capability
US8084327B2 (en) 2005-04-06 2011-12-27 Fairchild Semiconductor Corporation Method for forming trench gate field effect transistor with recessed mesas using spacers
US8198677B2 (en) 2002-10-03 2012-06-12 Fairchild Semiconductor Corporation Trench-gate LDMOS structures
US8319290B2 (en) 2010-06-18 2012-11-27 Fairchild Semiconductor Corporation Trench MOS barrier schottky rectifier with a planar surface using CMP techniques
KR101360070B1 (en) 2012-12-27 2014-02-12 현대자동차 주식회사 Semiconductor device and method manufacturing the same
US8673700B2 (en) 2011-04-27 2014-03-18 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
US8772868B2 (en) 2011-04-27 2014-07-08 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
US8786010B2 (en) 2011-04-27 2014-07-22 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
US8836028B2 (en) 2011-04-27 2014-09-16 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
US8928077B2 (en) 2007-09-21 2015-01-06 Fairchild Semiconductor Corporation Superjunction structures for power devices
US9029872B2 (en) 2012-12-27 2015-05-12 Hyundai Motor Company Semiconductor device and method for fabricating the same
DE102015216091A1 (en) 2014-09-24 2016-03-24 Sumitomo Electric Industries, Ltd. A method of manufacturing a silicon carbide semiconductor device and a silicon carbide semiconductor device
JP2016129192A (en) * 2015-01-09 2016-07-14 株式会社デンソー Semiconductor device
US9431481B2 (en) 2008-09-19 2016-08-30 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
EP2947690A4 (en) * 2013-01-15 2016-09-14 Sumitomo Electric Industries Silicon carbide semiconductor device and production method therefor
WO2016210261A1 (en) * 2015-06-26 2016-12-29 General Electric Company Active area designs for silicon carbide super-junction power devices and corresponding methods
CN106887451A (en) * 2015-12-15 2017-06-23 深圳尚阳通科技有限公司 Superjunction devices and its manufacture method
US9837489B2 (en) 2015-09-11 2017-12-05 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device
JP2017228773A (en) * 2016-06-08 2017-12-28 インフィネオン テクノロジーズ アーゲーＩｎｆｉｎｅｏｎ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ａｇ Superjunction structure in power semiconductor device
CN107658215A (en) * 2017-09-26 2018-02-02 中国科学院微电子研究所 A kind of silicon carbide device and preparation method thereof
CN111200010A (en) * 2018-11-20 2020-05-26 深圳尚阳通科技有限公司 Super junction device and manufacturing method thereof
CN111344866A (en) * 2017-09-14 2020-06-26 株式会社电装 Semiconductor device and method for manufacturing the same
CN111430449A (en) * 2020-04-01 2020-07-17 张清纯 MOSFET device and preparation process thereof
CN112913032A (en) * 2018-10-25 2021-06-04 三菱电机株式会社 Semiconductor device, power conversion device, and method for manufacturing semiconductor device
JP2022508324A (en) * 2018-12-07 2022-01-19 ヒタチ・エナジー・スウィツァーランド・アクチェンゲゼルシャフト Vertical Silicon Carbide Power MOSFETs and IGBTs and Their Manufacturing Methods
CN114050186A (en) * 2021-10-03 2022-02-15 北京工业大学 Irradiation reinforced SiC super-junction MOS structure

Cited By (102)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001196602A (en) * 2000-01-12 2001-07-19 Hitachi Ltd Electrostatic induction transistor
US7745289B2 (en) 2000-08-16 2010-06-29 Fairchild Semiconductor Corporation Method of forming a FET having ultra-low on-resistance and low gate charge
US8101484B2 (en) 2000-08-16 2012-01-24 Fairchild Semiconductor Corporation Method of forming a FET having ultra-low on-resistance and low gate charge
US8710584B2 (en) 2000-08-16 2014-04-29 Fairchild Semiconductor Corporation FET device having ultra-low on-resistance and low gate charge
US6982459B2 (en) 2000-12-18 2006-01-03 Denso Corporation Semiconductor device having a vertical type semiconductor element
US6639260B2 (en) * 2000-12-18 2003-10-28 Denso Corporation Semiconductor device having a vertical semiconductor element
US6818513B2 (en) 2001-01-30 2004-11-16 Fairchild Semiconductor Corporation Method of forming a field effect transistor having a lateral depletion structure
US6713813B2 (en) 2001-01-30 2004-03-30 Fairchild Semiconductor Corporation Field effect transistor having a lateral depletion structure
US8829641B2 (en) 2001-01-30 2014-09-09 Fairchild Semiconductor Corporation Method of forming a dual-trench field effect transistor
US9368587B2 (en) 2001-01-30 2016-06-14 Fairchild Semiconductor Corporation Accumulation-mode field effect transistor with improved current capability
JP2003069040A (en) * 2001-08-29 2003-03-07 Denso Corp Silicon carbide semiconductor device and manufacturing method thereof
JP2003115589A (en) * 2001-10-03 2003-04-18 Fuji Electric Co Ltd Semiconductor device and manufacturing method
JP2003209123A (en) * 2002-01-11 2003-07-25 Sumitomo Electric Ind Ltd Vertical jfet (junction field-effect transistor) and method of manufacturing the same
WO2003065459A1 (en) * 2002-01-28 2003-08-07 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US6949798B2 (en) 2002-01-28 2005-09-27 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
JP2003273355A (en) * 2002-03-18 2003-09-26 Toshiba Corp Semiconductor element and method for manufacturing the same
JP2003277193A (en) * 2002-03-22 2003-10-02 Toyota Central Res & Dev Lab Inc SiC WAFER WITH EPITAXIAL FILM, METHOD FOR PRODUCING THE SAME, AND SiC ELECTRONIC DEVICE
JP2003321298A (en) * 2002-04-30 2003-11-11 Toyota Central Res & Dev Lab Inc SiC SINGLE CRYSTAL AND METHOD FOR PRODUCING THE SAME, SiC WAFER WITH EPITAXIAL FILM AND METHOD FOR PRODUCING THE SAME, AND SiC ELECTRONIC DEVICE
US6803626B2 (en) 2002-07-18 2004-10-12 Fairchild Semiconductor Corporation Vertical charge control semiconductor device
US7977744B2 (en) 2002-07-18 2011-07-12 Fairchild Semiconductor Corporation Field effect transistor with trench filled with insulating material and strips of semi-insulating material along trench sidewalls
JP2004063507A (en) * 2002-07-24 2004-02-26 Sumitomo Electric Ind Ltd Vertical junction field-effect transistor and method of manufacturing the same
US7750377B2 (en) 2002-07-24 2010-07-06 Sumitomo Electric Industries, Ltd. Vertical junction field effect transistors, and methods of producing the vertical junction field effect transistors
US7282760B2 (en) 2002-07-24 2007-10-16 Sumitomo Electric Industries, Ltd. Vertical junction field effect transistors, and methods of producing the vertical junction field effect transistors
CN100349270C (en) * 2002-07-24 2007-11-14 住友电气工业株式会社 Vertical junction field-effect transistor and method of manufacturing the same
WO2004010489A1 (en) * 2002-07-24 2004-01-29 Sumitomo Electric Industries, Ltd. Vertical junction field effect transistor and method for fabricating the same
US6710403B2 (en) 2002-07-30 2004-03-23 Fairchild Semiconductor Corporation Dual trench power MOSFET
JP2004079631A (en) * 2002-08-12 2004-03-11 Sumitomo Electric Ind Ltd Vertical junction field effect transistor and its manufacturing method
US8198677B2 (en) 2002-10-03 2012-06-12 Fairchild Semiconductor Corporation Trench-gate LDMOS structures
US6710418B1 (en) 2002-10-11 2004-03-23 Fairchild Semiconductor Corporation Schottky rectifier with insulation-filled trenches and method of forming the same
JP2004147472A (en) * 2002-10-28 2004-05-20 Matsushita Electric Ind Co Ltd Direct current-to-alternating current converter for photovoltaic power generation
US6940110B2 (en) 2002-11-29 2005-09-06 Matsushita Electric Industrial Co., Ltd. SiC-MISFET and method for fabricating the same
CN100459153C (en) * 2002-11-29 2009-02-04 松下电器产业株式会社 SiC-MISFET and method for fabricating the same
US7652326B2 (en) 2003-05-20 2010-01-26 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
US8936985B2 (en) 2003-05-20 2015-01-20 Fairchild Semiconductor Corporation Methods related to power semiconductor devices with thick bottom oxide layers
US8889511B2 (en) 2003-05-20 2014-11-18 Fairchild Semiconductor Corporation Methods of manufacturing power semiconductor devices with trenched shielded split gate transistor
US7799636B2 (en) 2003-05-20 2010-09-21 Fairchild Semiconductor Corporation Power device with trenches having wider upper portion than lower portion
US7855415B2 (en) 2003-05-20 2010-12-21 Fairchild Semiconductor Corporation Power semiconductor devices having termination structures and methods of manufacture
US8716783B2 (en) 2003-05-20 2014-05-06 Fairchild Semiconductor Corporation Power device with self-aligned source regions
US8350317B2 (en) 2003-05-20 2013-01-08 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
US8143123B2 (en) 2003-05-20 2012-03-27 Fairchild Semiconductor Corporation Methods of forming inter-poly dielectric (IPD) layers in power semiconductor devices
US7982265B2 (en) 2003-05-20 2011-07-19 Fairchild Semiconductor Corporation Trenched shield gate power semiconductor devices and methods of manufacture
US8013387B2 (en) 2003-05-20 2011-09-06 Fairchild Semiconductor Corporation Power semiconductor devices with shield and gate contacts and methods of manufacture
US8013391B2 (en) 2003-05-20 2011-09-06 Fairchild Semiconductor Corporation Power semiconductor devices with trenched shielded split gate transistor and methods of manufacture
US8143124B2 (en) 2003-05-20 2012-03-27 Fairchild Semiconductor Corporation Methods of making power semiconductor devices with thick bottom oxide layer
US8034682B2 (en) 2003-05-20 2011-10-11 Fairchild Semiconductor Corporation Power device with trenches having wider upper portion than lower portion
US8786045B2 (en) 2003-05-20 2014-07-22 Fairchild Semiconductor Corporation Power semiconductor devices having termination structures
US8129245B2 (en) 2003-05-20 2012-03-06 Fairchild Semiconductor Corporation Methods of manufacturing power semiconductor devices with shield and gate contacts
US7655981B2 (en) 2003-11-28 2010-02-02 Fairchild Korea Semiconductor Ltd. Superjunction semiconductor device
US7936008B2 (en) 2003-12-30 2011-05-03 Fairchild Semiconductor Corporation Structure and method for forming accumulation-mode field effect transistor with improved current capability
US8518777B2 (en) 2003-12-30 2013-08-27 Fairchild Semiconductor Corporation Method for forming accumulation-mode field effect transistor with improved current capability
US8026558B2 (en) 2004-08-03 2011-09-27 Fairchild Semiconductor Corporation Semiconductor power device having a top-side drain using a sinker trench
US8148233B2 (en) 2004-08-03 2012-04-03 Fairchild Semiconductor Corporation Semiconductor power device having a top-side drain using a sinker trench
US7732876B2 (en) 2004-08-03 2010-06-08 Fairchild Semiconductor Corporation Power transistor with trench sinker for contacting the backside
US8680611B2 (en) 2005-04-06 2014-03-25 Fairchild Semiconductor Corporation Field effect transistor and schottky diode structures
US8084327B2 (en) 2005-04-06 2011-12-27 Fairchild Semiconductor Corporation Method for forming trench gate field effect transistor with recessed mesas using spacers
US7713822B2 (en) 2006-03-24 2010-05-11 Fairchild Semiconductor Corporation Method of forming high density trench FET with integrated Schottky diode
JP2007273856A (en) * 2006-03-31 2007-10-18 Toyota Central Res & Dev Lab Inc Semiconductor device
US7859047B2 (en) 2006-06-19 2010-12-28 Fairchild Semiconductor Corporation Shielded gate trench FET with the shield and gate electrodes connected together in non-active region
JP2009032919A (en) * 2007-07-27 2009-02-12 Sumitomo Electric Ind Ltd Oxide film field-effect transistor and manufacturing method therefor
JP2009032921A (en) * 2007-07-27 2009-02-12 Sumitomo Electric Ind Ltd Oxide film field-effect transistor and manufacturing method therefor
US9595596B2 (en) 2007-09-21 2017-03-14 Fairchild Semiconductor Corporation Superjunction structures for power devices
US8928077B2 (en) 2007-09-21 2015-01-06 Fairchild Semiconductor Corporation Superjunction structures for power devices
US7772668B2 (en) 2007-12-26 2010-08-10 Fairchild Semiconductor Corporation Shielded gate trench FET with multiple channels
US9224853B2 (en) 2007-12-26 2015-12-29 Fairchild Semiconductor Corporation Shielded gate trench FET with multiple channels
JP2009194164A (en) * 2008-02-14 2009-08-27 Sumitomo Electric Ind Ltd Insulation gate type field-effect transistor and manufacturing method therefor
US9431481B2 (en) 2008-09-19 2016-08-30 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
US8319290B2 (en) 2010-06-18 2012-11-27 Fairchild Semiconductor Corporation Trench MOS barrier schottky rectifier with a planar surface using CMP techniques
US8432000B2 (en) 2010-06-18 2013-04-30 Fairchild Semiconductor Corporation Trench MOS barrier schottky rectifier with a planar surface using CMP techniques
US8836028B2 (en) 2011-04-27 2014-09-16 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
US8673700B2 (en) 2011-04-27 2014-03-18 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
US8786010B2 (en) 2011-04-27 2014-07-22 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
US8772868B2 (en) 2011-04-27 2014-07-08 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
US9029872B2 (en) 2012-12-27 2015-05-12 Hyundai Motor Company Semiconductor device and method for fabricating the same
KR101360070B1 (en) 2012-12-27 2014-02-12 현대자동차 주식회사 Semiconductor device and method manufacturing the same
US10211284B2 (en) 2013-01-15 2019-02-19 Sumitomo Electric Industries, Ltd. Silicon carbide semiconductor device and method for manufacturing same
EP2947690A4 (en) * 2013-01-15 2016-09-14 Sumitomo Electric Industries Silicon carbide semiconductor device and production method therefor
US10217813B2 (en) 2014-09-24 2019-02-26 Sumitomo Electric Industries, Ltd. Method for manufacturing silicon carbide semiconductor device and silicon carbide semiconductor device
DE102015216091A1 (en) 2014-09-24 2016-03-24 Sumitomo Electric Industries, Ltd. A method of manufacturing a silicon carbide semiconductor device and a silicon carbide semiconductor device
US9881996B2 (en) 2014-09-24 2018-01-30 Sumitomo Electric Industries, Ltd. Method for manufacturing silicon carbide semiconductor device and silicon carbide semiconductor device
JP2016129192A (en) * 2015-01-09 2016-07-14 株式会社デンソー Semiconductor device
US9735237B2 (en) 2015-06-26 2017-08-15 General Electric Company Active area designs for silicon carbide super-junction power devices
CN107810558A (en) * 2015-06-26 2018-03-16 通用电气公司 Designed for the active area of carborundum superjunction power device
WO2016210261A1 (en) * 2015-06-26 2016-12-29 General Electric Company Active area designs for silicon carbide super-junction power devices and corresponding methods
US9837489B2 (en) 2015-09-11 2017-12-05 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device
CN106887451A (en) * 2015-12-15 2017-06-23 深圳尚阳通科技有限公司 Superjunction devices and its manufacture method
CN106887451B (en) * 2015-12-15 2020-04-07 深圳尚阳通科技有限公司 Super junction device and manufacturing method thereof
US10615040B2 (en) 2016-06-08 2020-04-07 Infineon Technologies Ag Superjunction structure in a power semiconductor device
JP2017228773A (en) * 2016-06-08 2017-12-28 インフィネオン テクノロジーズ アーゲーＩｎｆｉｎｅｏｎ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ａｇ Superjunction structure in power semiconductor device
CN111344866B (en) * 2017-09-14 2023-06-16 株式会社电装 Semiconductor device and method for manufacturing the same
CN111344866A (en) * 2017-09-14 2020-06-26 株式会社电装 Semiconductor device and method for manufacturing the same
CN107658215A (en) * 2017-09-26 2018-02-02 中国科学院微电子研究所 A kind of silicon carbide device and preparation method thereof
CN112913032B (en) * 2018-10-25 2024-05-03 三菱电机株式会社 Semiconductor device and power conversion device
CN112913032A (en) * 2018-10-25 2021-06-04 三菱电机株式会社 Semiconductor device, power conversion device, and method for manufacturing semiconductor device
CN111200010A (en) * 2018-11-20 2020-05-26 深圳尚阳通科技有限公司 Super junction device and manufacturing method thereof
CN111200010B (en) * 2018-11-20 2023-09-29 深圳尚阳通科技股份有限公司 Superjunction device and method of manufacturing the same
JP2022508324A (en) * 2018-12-07 2022-01-19 ヒタチ・エナジー・スウィツァーランド・アクチェンゲゼルシャフト Vertical Silicon Carbide Power MOSFETs and IGBTs and Their Manufacturing Methods
JP7100769B2 (en) 2018-12-07 2022-07-13 ヒタチ・エナジー・スウィツァーランド・アクチェンゲゼルシャフト Vertical Silicon Carbide Power MOSFETs and IGBTs and Their Manufacturing Methods
US11967616B2 (en) 2018-12-07 2024-04-23 Hitachi Energy Ltd Vertical silicon carbide power MOSFET and IGBT and a method of manufacturing the same
CN111430449A (en) * 2020-04-01 2020-07-17 张清纯 MOSFET device and preparation process thereof
CN111430449B (en) * 2020-04-01 2023-06-02 清纯半导体(宁波)有限公司 MOSFET device and preparation process thereof
CN114050186B (en) * 2021-10-03 2023-09-19 北京工业大学 Irradiation reinforced SiC super junction MOS structure
CN114050186A (en) * 2021-10-03 2022-02-15 北京工业大学 Irradiation reinforced SiC super-junction MOS structure

Also Published As

Publication number Publication date
JP4450122B2 (en) 2010-04-14

Similar Documents

Publication Publication Date Title
JP4450122B2 (en) Silicon carbide semiconductor device
US6551865B2 (en) Silicon carbide semiconductor device and method of fabricating the same
KR101168782B1 (en) Silicon carbide devices and fabricating methods therefor
JP4123636B2 (en) Silicon carbide semiconductor device and manufacturing method thereof
JP3666280B2 (en) Silicon carbide vertical FET and method of manufacturing the same
JP5586887B2 (en) Semiconductor device and manufacturing method thereof
JP4595144B2 (en) Silicon carbide semiconductor device and manufacturing method thereof
JP2001077363A (en) Silicon carbide semiconductor device and its manufacturing method
US20120153303A1 (en) Semiconductor element and method for manufacturing same
JP2000106371A (en) Fabrication of silicon carbide semiconductor device
JP2000049167A (en) Silicon carbide semiconductor device and manufacture thereof
JP2018110164A (en) Semiconductor device
JP4568929B2 (en) Silicon carbide semiconductor device and manufacturing method thereof
JP4538870B2 (en) Silicon carbide semiconductor device and manufacturing method thereof
JP4568930B2 (en) Method for manufacturing silicon carbide semiconductor device
JP3800047B2 (en) Field effect transistor
WO2004032244A1 (en) Semiconductor device and process for fabricating the same
US8928045B2 (en) Semiconductor device
JP4956776B2 (en) Manufacturing method of semiconductor device
JP3994703B2 (en) Silicon carbide semiconductor device and manufacturing method thereof
JP2003069042A (en) Silicon carbide semiconductor device and manufacturing method thereof
JP3496509B2 (en) Method for manufacturing silicon carbide semiconductor device
JP3785794B2 (en) Silicon carbide semiconductor device and manufacturing method thereof
JP2006086549A (en) Field effect transistor and its manufacturing method
JP3997886B2 (en) Method for manufacturing silicon carbide semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20051216

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20081008

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20091006

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20091204

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20100106

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

R151 Written notification of patent or utility model registration

Ref document number: 4450122

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R151

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20100119

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130205

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140205

Year of fee payment: 4

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees