JP4442426B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP4442426B2
JP4442426B2 JP2005000466A JP2005000466A JP4442426B2 JP 4442426 B2 JP4442426 B2 JP 4442426B2 JP 2005000466 A JP2005000466 A JP 2005000466A JP 2005000466 A JP2005000466 A JP 2005000466A JP 4442426 B2 JP4442426 B2 JP 4442426B2
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semiconductor chip
conductive pattern
wiring board
semiconductor device
semiconductor
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JP2006190747A (en
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真吾 堀井
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Seiko Epson Corp
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Seiko Epson Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device exhibiting excellent packaging properties, and to provide its manufacturing method. <P>SOLUTION: The semiconductor device comprises a wiring board 10, a first semiconductor chip 20 mounted on the first surface 14 of the wiring board 10, a first conductive pattern 30 formed directly on the first surface 14, a second semiconductor chip 40 mounted on the second surface 16 of the wiring board 10 and smaller than the first semiconductor chip 20, and a second conductive pattern 50 formed directly on the second surface 16. The planar area of a portion formed outside the first semiconductor chip 20 in the first conductive pattern 30 is larger than the planar area of a portion formed outside the second semiconductor chip 40 in the second conductive pattern 50. <P>COPYRIGHT: (C)2006,JPO&amp;NCIPI

Description

本発明は、半導体装置及びその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof.

１つの配線基板の両面に半導体チップが搭載された半導体装置が知られている。当該半導体装置を製造する際及び当該半導体装置を回路基板等に実装する際に平坦性を確保することが可能になれば、実装性に優れた半導体装置を提供することができる。   A semiconductor device in which semiconductor chips are mounted on both surfaces of one wiring board is known. If flatness can be ensured when the semiconductor device is manufactured and when the semiconductor device is mounted on a circuit board or the like, a semiconductor device with excellent mountability can be provided.

本発明の目的は、実装性に優れた半導体装置及びその製造方法を提供することにある。
特開平１０−２８４５４４号公報 An object of the present invention is to provide a semiconductor device excellent in mountability and a manufacturing method thereof.
Japanese Patent Laid-Open No. 10-284544

（１）本発明に係る半導体装置は、配線基板と、
前記配線基板の第１の面に搭載された第１の半導体チップと、
前記第１の面に直接形成された第１の導電パターンと、
前記配線基板の第２の面に搭載された、前記第１の半導体チップよりも小さい第２の半導体チップと、
前記第２の面に直接形成された第２の導電パターンと、
を有し、
前記第１の導電パターンは、前記配線基板よりも線膨張係数が大きく、
前記第１の導電パターンにおける前記第１の半導体チップよりも外側に配置された部分の平面面積は、前記第２の導電パターンにおける前記第２の半導体チップよりも外側に配置された部分の平面面積よりも大きい。本発明によれば、配線基板の第１及び第２の面の膨張・収縮量の差が小さい、実装性に優れた半導体装置を提供することができる。
（２）この半導体装置において、
前記第１及び第２の導電パターンは、同じ材料で形成されていてもよい。
（３）この半導体装置において、
前記第１及び第２の導電パターンは、同じ厚みに形成されていてもよい。
（４）この半導体装置において、
前記配線基板の前記第２の面には外部端子が形成されてなり、
前記第１の導電パターンは、前記外部端子とオーバーラップするように形成されていてもよい。
（５）本発明に係る半導体装置の製造方法は、配線基板を用意すること、
前記配線基板の第１の面に第１の半導体チップを搭載すること、及び、
前記配線基板の第２の面に、前記第１の半導体チップよりも小さい第２の半導体チップを搭載することを含み、
前記配線基板は、前記第１の面に直接形成された第１の導電パターンと、前記第２の面に直接形成された第２の導電パターンとを有し、
前記第１の導電パターンは、前記配線基板よりも線膨張係数が大きく、
前記第１の導電パターンにおける前記第１の半導体チップを搭載するための領域よりも外側に配置された部分の平面面積は、前記第２の導電パターンにおける前記第２の半導体チップを搭載するための領域よりも外側に配置された部分の平面面積よりも大きい。本発明によれば、配線基板の第１及び第２の面の膨張・収縮量の差が小さくなるため、実装性に優れた半導体装置を製造することができる。
（６）この半導体装置の製造方法において、
前記第１及び第２の導電パターンは、同じ材料で形成されていてもよい。
（７）この半導体装置の製造方法において、
前記第１及び第２の導電パターンは、同じ厚みに形成されていてもよい。
（８）この半導体装置の製造方法において、
前記配線基板の前記第２の面に外部端子を形成することをさらに含み、
前記第１の導電パターンは、前記外部端子を形成するための領域とオーバーラップするように形成されていてもよい。 (1) A semiconductor device according to the present invention includes a wiring board,
A first semiconductor chip mounted on a first surface of the wiring board;
A first conductive pattern formed directly on the first surface;
A second semiconductor chip mounted on the second surface of the wiring board and smaller than the first semiconductor chip;
A second conductive pattern formed directly on the second surface;
Have
The first conductive pattern has a larger coefficient of linear expansion than the wiring board,
The planar area of the portion arranged outside the first semiconductor chip in the first conductive pattern is the planar area of the portion arranged outside the second semiconductor chip in the second conductive pattern. Bigger than. ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device excellent in the mountability which the difference of the expansion / contraction amount of the 1st and 2nd surface of a wiring board is small can be provided.
(2) In this semiconductor device,
The first and second conductive patterns may be formed of the same material.
(3) In this semiconductor device,
The first and second conductive patterns may be formed with the same thickness.
(4) In this semiconductor device,
External terminals are formed on the second surface of the wiring board,
The first conductive pattern may be formed so as to overlap the external terminal.
(5) A method for manufacturing a semiconductor device according to the present invention comprises preparing a wiring board;
Mounting a first semiconductor chip on a first surface of the wiring board; and
Mounting a second semiconductor chip smaller than the first semiconductor chip on the second surface of the wiring board;
The wiring board has a first conductive pattern directly formed on the first surface and a second conductive pattern directly formed on the second surface;
The first conductive pattern has a larger coefficient of linear expansion than the wiring board,
The planar area of the portion arranged outside the region for mounting the first semiconductor chip in the first conductive pattern is for mounting the second semiconductor chip in the second conductive pattern. It is larger than the plane area of the portion arranged outside the region. According to the present invention, a difference in expansion / contraction amount between the first and second surfaces of the wiring board is reduced, so that a semiconductor device excellent in mountability can be manufactured.
(6) In this method of manufacturing a semiconductor device,
The first and second conductive patterns may be formed of the same material.
(7) In this method of manufacturing a semiconductor device,
The first and second conductive patterns may be formed with the same thickness.
(8) In this method of manufacturing a semiconductor device,
Forming an external terminal on the second surface of the wiring board;
The first conductive pattern may be formed so as to overlap with a region for forming the external terminal.

以下、本発明を適用した実施の形態について図面を参照して説明する。ただし、本発明は以下の実施の形態に限定されるものではない。   Embodiments to which the present invention is applied will be described below with reference to the drawings. However, the present invention is not limited to the following embodiments.

図１は、本発明を適用した実施の形態に係る半導体装置について説明するための図である。なお、図１は、半導体装置１の断面図である。   FIG. 1 is a diagram for explaining a semiconductor device according to an embodiment to which the present invention is applied. FIG. 1 is a cross-sectional view of the semiconductor device 1.

本実施の形態に係る半導体装置は、配線基板１０を有する。配線基板１０の材料や構造は特に限定されず、既に公知となっているいずれかの基板を利用してもよい。配線基板１０は、フレキシブル基板であってもよく、リジッド基板であってもよい。あるいは、配線基板１０は、テープ基板であってもよい。配線基板１０は、積層型の基板であってもよく、あるいは、単層の基板であってもよい。また、配線基板１０の外形も特に限定されるものではない。配線基板１０は、配線パターン１２を有していてもよい。配線パターン１２は、配線基板１０の表面、あるいは、配線基板１０の層間に形成されていてもよい。配線パターン１２の構造や材料は特に限定されず、既に公知となっているいずれかの配線を利用してもよい。例えば、配線パターン１２は、銅（Ｃｕ）、クローム（Ｃｒ）、チタン（Ｔｉ）、ニッケル（Ｎｉ）、チタンタングステン（Ｔｉ−Ｗ）、金（Ａｕ）、アルミニウム（Ａｌ）、ニッケルバナジウム（ＮｉＶ）、タングステン（Ｗ）のうちのいずれかを積層して、あるいはいずれかの一層で形成されていてもよい。配線パターン１２は、配線基板１０の表面（第１及び第２の面１４，１６）に設けられたランド１３を有していてもよい。ランド１３は、電子部品の電極（例えば半導体チップの電極）との電気的な接続に利用される部分であってもよい。また、配線パターン１２は、外部端子を搭載するためのランド１５をさらに含んでいてもよい。配線基板１０は、第１の面１４と、第１の面１４と反対側の第２の面１６とを有する。このとき、後述する第１の半導体チップ２０が搭載される面を第１の面１４と、第２の半導体チップ４０が搭載される面を第２の面１６と、それぞれ称してもよい。そして、ランド１５は、第２の面１４に設けられていてもよい。配線基板１０は、図示しない保護膜をさらに有してもよい。なお、保護膜は、配線パターン１２の一部を覆うように形成されていてもよい。   The semiconductor device according to the present embodiment has a wiring board 10. The material and structure of the wiring substrate 10 are not particularly limited, and any substrate that is already known may be used. The wiring board 10 may be a flexible board or a rigid board. Alternatively, the wiring substrate 10 may be a tape substrate. The wiring substrate 10 may be a laminated substrate or a single layer substrate. Further, the outer shape of the wiring board 10 is not particularly limited. The wiring board 10 may have a wiring pattern 12. The wiring pattern 12 may be formed on the surface of the wiring substrate 10 or between the layers of the wiring substrate 10. The structure and material of the wiring pattern 12 are not particularly limited, and any known wiring may be used. For example, the wiring pattern 12 includes copper (Cu), chromium (Cr), titanium (Ti), nickel (Ni), titanium tungsten (Ti-W), gold (Au), aluminum (Al), nickel vanadium (NiV). , Any one of tungsten (W) may be laminated or formed in any one layer. The wiring pattern 12 may have lands 13 provided on the surface (first and second surfaces 14, 16) of the wiring substrate 10. The land 13 may be a portion used for electrical connection with an electrode of an electronic component (for example, an electrode of a semiconductor chip). The wiring pattern 12 may further include a land 15 for mounting an external terminal. The wiring board 10 has a first surface 14 and a second surface 16 opposite to the first surface 14. At this time, a surface on which a first semiconductor chip 20 to be described later is mounted may be referred to as a first surface 14, and a surface on which the second semiconductor chip 40 is mounted may be referred to as a second surface 16. The land 15 may be provided on the second surface 14. The wiring board 10 may further include a protective film (not shown). The protective film may be formed so as to cover a part of the wiring pattern 12.

本実施の形態に係る半導体装置は、第１の半導体チップ２０を有する。第１の半導体チップ２０は、例えばシリコンチップであってもよい。第１の半導体チップ２０は、集積回路２２を有していてもよい。集積回路２２の構成は特に限定されないが、例えば、トランジスタ等の能動素子や、抵抗、コイル、コンデンサ等の受動素子を含んでいてもよい。また、第１の半導体チップ２０は、複数の電極２４を有していてもよい。電極２４は、第１の半導体チップ２０の内部と電気的に接続されていてもよい。電極２４は、集積回路２２と電気的に接続されていてもよい。あるいは、集積回路２２に電気的に接続されていない電極を含めて、電極２４と称してもよい。電極２４は、薄く平らに形成されたパッドと、該パッド上に形成されたバンプとを含んでいてもよい。このとき、パッド及びバンプの材料は特に限定されないが、例えば、パッドとしてアルミニウムや銅を、バンプとして金を、それぞれ利用してもよい。   The semiconductor device according to the present embodiment has a first semiconductor chip 20. The first semiconductor chip 20 may be a silicon chip, for example. The first semiconductor chip 20 may have an integrated circuit 22. The configuration of the integrated circuit 22 is not particularly limited, and may include, for example, an active element such as a transistor or a passive element such as a resistor, a coil, or a capacitor. Further, the first semiconductor chip 20 may have a plurality of electrodes 24. The electrode 24 may be electrically connected to the inside of the first semiconductor chip 20. The electrode 24 may be electrically connected to the integrated circuit 22. Alternatively, an electrode that is not electrically connected to the integrated circuit 22 may be referred to as an electrode 24. The electrode 24 may include a thin flat pad and a bump formed on the pad. At this time, the material of the pad and the bump is not particularly limited. For example, aluminum or copper may be used as the pad and gold may be used as the bump.

第１の半導体チップ２０は、図１に示すように、配線基板１０に搭載されてなる。このとき、配線基板１０における第１の半導体チップ２０が搭載された面を、第１の面１４と称してもよい。すなわち、第１の半導体チップ２０は、配線基板１０の第１の面１４に搭載されていてもよい。第１の半導体チップ２０は、図１に示すように、電極２４が配線パターン１２（ランド１３）と対向するように、配線基板１０に搭載されていてもよい。このとき、電極２４とランド１３とが対向して電気的に接続されていてもよい。電極２４とランド１３とは、図１に示すように、接触して電気的に接続されていてもよい。このとき、電極２４とランド１３とは固着されていてもよい。例えば、電極２４とランド１３とは、共晶合金を介して接合（共晶合金接合）されていてもよい。ただし、これとは別に、電極２４とランド１３とは、導電粒子（図示せず）を介して電気的に接続されていてもよい。   As shown in FIG. 1, the first semiconductor chip 20 is mounted on the wiring board 10. At this time, a surface of the wiring substrate 10 on which the first semiconductor chip 20 is mounted may be referred to as a first surface 14. That is, the first semiconductor chip 20 may be mounted on the first surface 14 of the wiring substrate 10. As shown in FIG. 1, the first semiconductor chip 20 may be mounted on the wiring board 10 so that the electrode 24 faces the wiring pattern 12 (land 13). At this time, the electrode 24 and the land 13 may be opposed and electrically connected. The electrode 24 and the land 13 may be in contact and electrically connected as shown in FIG. At this time, the electrode 24 and the land 13 may be fixed. For example, the electrode 24 and the land 13 may be bonded via a eutectic alloy (eutectic alloy bonding). However, apart from this, the electrode 24 and the land 13 may be electrically connected via conductive particles (not shown).

本実施の形態に係る半導体装置は、配線基板１０の第１の面１４に形成された第１の導電パターン３０を含む。第１の導電パターン３０は、第１の面１４に直接形成されてなる。すなわち、第１の導電パターン３０は、接着剤を介することなく、第１の面１４に形成されてなる。第１の導電パターン３０は、配線パターン１２の一部であってもよい。第１の導電パターン３０は、半導体チップ（第１及び第２の半導体チップ２０，４０）と電気的に接続されていてもよい。ただし、第１の導電パターン３０は、半導体チップと電気的に接続されていないパターン（いわゆるダミーパターン）であってもよい。なお、第１の導電パターン３０の平面形状は特に限定されず、パターニングされていてもよく、あるいは、第１の面１４に箔状に拡がっていてもよい。そして、第１の導電パターン３０は、配線基板１０よりも線膨張係数が大きい。第１の導電パターン３０の材料や、配線基板１０の材料を調整することで、両者の線膨張係数を制御してもよい。なお、第１の導電パターン３０は、後述する外部端子６０とオーバーラップする領域に至るように形成されていてもよい。すなわち、第１の導電パターン３０は、ランド１５とオーバーラップする領域に至るように形成されていてもよい。   The semiconductor device according to the present embodiment includes a first conductive pattern 30 formed on the first surface 14 of the wiring substrate 10. The first conductive pattern 30 is formed directly on the first surface 14. That is, the first conductive pattern 30 is formed on the first surface 14 without using an adhesive. The first conductive pattern 30 may be a part of the wiring pattern 12. The first conductive pattern 30 may be electrically connected to a semiconductor chip (first and second semiconductor chips 20 and 40). However, the first conductive pattern 30 may be a pattern that is not electrically connected to the semiconductor chip (so-called dummy pattern). Note that the planar shape of the first conductive pattern 30 is not particularly limited, and may be patterned, or may be spread on the first surface 14 in a foil shape. The first conductive pattern 30 has a larger linear expansion coefficient than the wiring board 10. By adjusting the material of the first conductive pattern 30 and the material of the wiring substrate 10, the linear expansion coefficient of both may be controlled. The first conductive pattern 30 may be formed so as to reach a region overlapping with an external terminal 60 described later. That is, the first conductive pattern 30 may be formed so as to reach a region overlapping the land 15.

本実施の形態に係る半導体装置は、図１に示すように、配線基板１０の第１の面１４に形成されて、配線基板１０と第１の半導体チップ２０とを接着する第１の樹脂部３５を有していてもよい。第１の樹脂部３５の材料は特に限定されず、既に公知となっているいずれかの材料を利用してもよい。   As shown in FIG. 1, the semiconductor device according to the present embodiment is formed on the first surface 14 of the wiring substrate 10, and a first resin portion that bonds the wiring substrate 10 and the first semiconductor chip 20. 35 may be included. The material of the first resin portion 35 is not particularly limited, and any known material may be used.

本実施の形態に係る半導体装置は、配線基板１０の第２の面１６に搭載された、第１の半導体チップ２０よりも小さい第２の半導体チップ４０を有する。第２の半導体チップ４０の構成は、第１の半導体チップ２０の説明で挙げたいずれかの内容を適用してもよい。第２の半導体チップ４０は、集積回路４２を有していてもよい。また、第２の半導体チップ４０は、電極４４を有していてもよい。第２の半導体チップ４０は、電極４４が配線パターン１２（ランド１３）と対向するように、配線基板１０に搭載されていてもよい。このとき、電極４４とランド１３とは固着されていてもよい。そして、電極４４とランド１３とは電気的に接続されていてもよい。なお、第２の半導体チップ４０は、第１の半導体チップ２０とオーバーラップするように配置されていてもよい。このとき、第１及び第２の半導体チップ２０，４０は、中心が配線基板１０の厚み方向に一致するように配置されていてもよい。言い換えると、第１及び第２の半導体チップ２０，４０は、第１の半導体チップ２０の中心と第２の半導体チップ４０の中心とが配線基板１０の平面垂直方向に一致するように搭載されていてもよい。   The semiconductor device according to the present embodiment has a second semiconductor chip 40 that is smaller than the first semiconductor chip 20 and is mounted on the second surface 16 of the wiring substrate 10. As the configuration of the second semiconductor chip 40, any of the contents mentioned in the description of the first semiconductor chip 20 may be applied. The second semiconductor chip 40 may have an integrated circuit 42. Further, the second semiconductor chip 40 may have an electrode 44. The second semiconductor chip 40 may be mounted on the wiring board 10 so that the electrode 44 faces the wiring pattern 12 (land 13). At this time, the electrode 44 and the land 13 may be fixed. The electrode 44 and the land 13 may be electrically connected. The second semiconductor chip 40 may be disposed so as to overlap the first semiconductor chip 20. At this time, the first and second semiconductor chips 20 and 40 may be arranged so that the centers thereof coincide with the thickness direction of the wiring board 10. In other words, the first and second semiconductor chips 20 and 40 are mounted such that the center of the first semiconductor chip 20 and the center of the second semiconductor chip 40 coincide with the plane vertical direction of the wiring substrate 10. May be.

本実施の形態に係る半導体装置は、配線基板１０の第２の面１６に形成された第２の導電パターン５０を含む。第２の導電パターン５０は、第２の面１６に直接形成されてなる。すなわち、第２の導電パターン５０は、接着剤を介することなく、第２の面１６に形成されてなる。第２の導電パターン５０は、配線パターン１２の一部であってもよい。このとき、ランド１５は、第２の導電パターン５０の一部であってもよい。ただし、第２の導電パターン５０は、ランドとして機能しない部分を有していてもよい。また、配線パターン１２からランドとして機能する部分を除いた導電パターンのみを、第２の導電パターン５０と称してもよい。第２の導電パターン５０は、半導体チップ（第１及び第２の半導体チップ２０，４０）と電気的に接続されていてもよい。ただし、第２の導電パターン５０は、配線パターン１２及び半導体チップと電気的に接続されていないパターン（いわゆるダミーパターン）であってもよい。なお、第２の導電パターン５０は、配線基板１０よりも線膨張係数が大きくてもよい。第２の導電パターン５０は、第１の導電パターン３０と同じ線膨張係数をなしていてもよい。あるいは、第２の導電パターン５０の線膨張係数は、第１の導電パターン３０の線膨張係数よりも小さくてもよい。   The semiconductor device according to the present embodiment includes a second conductive pattern 50 formed on the second surface 16 of the wiring substrate 10. The second conductive pattern 50 is formed directly on the second surface 16. That is, the second conductive pattern 50 is formed on the second surface 16 without using an adhesive. The second conductive pattern 50 may be a part of the wiring pattern 12. At this time, the land 15 may be a part of the second conductive pattern 50. However, the second conductive pattern 50 may have a portion that does not function as a land. In addition, only the conductive pattern excluding the portion functioning as a land from the wiring pattern 12 may be referred to as the second conductive pattern 50. The second conductive pattern 50 may be electrically connected to the semiconductor chip (first and second semiconductor chips 20 and 40). However, the second conductive pattern 50 may be a pattern (so-called dummy pattern) that is not electrically connected to the wiring pattern 12 and the semiconductor chip. The second conductive pattern 50 may have a linear expansion coefficient larger than that of the wiring board 10. The second conductive pattern 50 may have the same linear expansion coefficient as that of the first conductive pattern 30. Alternatively, the linear expansion coefficient of the second conductive pattern 50 may be smaller than the linear expansion coefficient of the first conductive pattern 30.

本実施の形態に係る半導体装置は、図１に示すように、配線基板１０の第２の面１６に形成されて、配線基板１０と第２の半導体チップ４０とを接着する第２の樹脂部５５を有していてもよい。第２の樹脂部５５の材料は特に限定されず、例えば、配線基板１０又は第１の樹脂部３５と同じ材料を利用してもよい。   As shown in FIG. 1, the semiconductor device according to the present embodiment is formed on the second surface 16 of the wiring substrate 10, and a second resin portion that bonds the wiring substrate 10 and the second semiconductor chip 40. 55 may be included. The material of the 2nd resin part 55 is not specifically limited, For example, you may utilize the same material as the wiring board 10 or the 1st resin part 35. FIG.

本実施の形態に係る半導体装置では、第１の導電パターン３０における第１の半導体チップ２０よりも外側に配置された部分の平面面積は、第２の導電パターン５０における第２の半導体チップ４０よりも外側に配置された部分の平面面積よりも大きくなっている。なお、第１及び第２の導電パターン３０，５０は、同じ材料で形成されていてもよい。また、第１及び第２の導電パターン３０，５０は、同じ厚みをなしていてもよい。   In the semiconductor device according to the present embodiment, the planar area of the portion disposed outside the first semiconductor chip 20 in the first conductive pattern 30 is larger than that in the second semiconductor chip 40 in the second conductive pattern 50. Is larger than the plane area of the portion arranged outside. Note that the first and second conductive patterns 30 and 50 may be formed of the same material. The first and second conductive patterns 30 and 50 may have the same thickness.

本実施の形態に係る半導体装置は、図１に示すように、外部端子６０を有していてもよい。外部端子６０は、配線基板１０の第２の面１６に設けられていてもよい。すなわち、配線基板１０の第２の面１６には、外部端子６０が形成されていてもよい。外部端子６０が配置される領域は特に限定されない。外部端子６０は、例えば、第１の半導体チップ２０とオーバーラップする領域内のみに配置されていてもよい（Fan−Inタイプ）。あるいは、外部端子６０は、第１の半導体チップ２０とオーバーラップする領域よりも外側のみに配置されていてもよい（Fan−Outタイプ）。あるいは、外部端子６０は、第１の半導体チップ２０とオーバーラップする領域の内側及び外側に設けられていてもよい（Fan−In／Outタイプ）。なお、外部端子６０は、配線パターン１２のランド１５上に設けられていてもよい。   The semiconductor device according to the present embodiment may have an external terminal 60 as shown in FIG. The external terminal 60 may be provided on the second surface 16 of the wiring board 10. That is, the external terminal 60 may be formed on the second surface 16 of the wiring board 10. The region where the external terminal 60 is disposed is not particularly limited. The external terminal 60 may be disposed only in a region overlapping with the first semiconductor chip 20 (Fan-In type), for example. Alternatively, the external terminal 60 may be disposed only outside the region overlapping with the first semiconductor chip 20 (Fan-Out type). Alternatively, the external terminal 60 may be provided inside and outside the region overlapping with the first semiconductor chip 20 (Fan-In / Out type). The external terminal 60 may be provided on the land 15 of the wiring pattern 12.

本実施の形態に係る半導体装置１は、以上のように構成されていてもよい。先に説明したように、半導体装置１では、１つの配線基板（配線基板１０）の両面に、大きさの異なる半導体チップ（第１及び第２の半導体チップ２０，４０）が搭載されてなる。半導体装置は、通常、温度サイクル試験や、回路基板に実装される際、あるいは、実装後の環境の変化により、加熱・冷却されることがある。この加熱・冷却の影響を受けて、配線基板は膨張・収縮することがあった。ところで、半導体チップは、配線基板に較べて線膨張係数が低いことが多く、加熱・冷却された場合でも、配線基板に較べて大きさが変化しにくい。そのため、配線基板に半導体チップが搭載されている場合、配線基板の表面における半導体チップとオーバーラップする領域は、半導体チップに規制されるため大きさが変化しにくくなる。そして、１つの配線基板の両面のそれぞれに異なる大きさの半導体チップが搭載されている場合（図１参照）には、１つの配線基板の両面のそれぞれで膨張・収縮が規制される領域の面積が異なるため、配線基板の両面で、膨張・収縮による大きさの変化量が異なることがあった。具体的には、大きい半導体チップが搭載された面（第１の半導体チップ２０が搭載された第１の面１４）よりも、小さい半導体チップが搭載された面（第２の半導体チップ４０が搭載された第２の面１６）の方が、加熱・冷却による膨張・収縮量が大きくなることがあった。そして、膨張・収縮量の違いが原因となって、配線基板に反りが生じることがあった。ところで、半導体装置１では、先に説明したように、第１の導電パターン３０における第１の半導体チップ２０の外側に配置された部分の平面面積は、第２の導電パターン５０における第２の半導体チップ４０の外側に配置された部分の平面面積よりも大きくなっている。また、第１の導電パターン３０は、配線基板１０よりも線膨張係数が大きい。すなわち、第１の導電パターン３０は、配線基板１０よりも、大きく膨張・収縮する。そして、第１の導電パターン３０は、第１の面１４に直接形成されてなる。このことから、半導体装置１によれば、第１の導電パターン３０の膨張・収縮の影響を受けて、配線基板１０の第１の面１４の膨張・収縮量が大きくなる。すなわち、半導体装置１によれば、第１及び第２の面１４，１６の、膨張・収縮量の差を小さくすることができる。そのため、半導体装置の反りが発生しにくい、実装性に優れた半導体装置を提供することができる。また、第１の導電パターン３０は、外部端子６０とオーバーラップするように形成されていてもよい。これによると、外部端子６０が形成された領域で配線基板１０を平坦にすることができるため、実装性に優れた半導体装置を提供することができる。そして、図２には、半導体装置１が実装された回路基板１０００を示す。また、半導体装置１を有する電子機器として、図３にはノート型パーソナルコンピュータ２０００を、図４には携帯電話３０００を、それぞれ示す。   The semiconductor device 1 according to the present embodiment may be configured as described above. As described above, in the semiconductor device 1, semiconductor chips (first and second semiconductor chips 20 and 40) having different sizes are mounted on both surfaces of one wiring board (wiring board 10). A semiconductor device is usually heated and cooled by a temperature cycle test, when mounted on a circuit board, or by a change in environment after mounting. Under the influence of this heating and cooling, the wiring board may expand and contract. By the way, the semiconductor chip often has a lower coefficient of linear expansion than the wiring board, and even when heated and cooled, the size of the semiconductor chip is less likely to change compared to the wiring board. For this reason, when a semiconductor chip is mounted on the wiring board, the area overlapping the semiconductor chip on the surface of the wiring board is restricted by the semiconductor chip, so that the size hardly changes. When semiconductor chips of different sizes are mounted on both surfaces of one wiring board (see FIG. 1), the area of the region where expansion / contraction is restricted on both surfaces of one wiring board Therefore, the amount of change in size due to expansion / contraction may be different on both sides of the wiring board. Specifically, the surface (the second semiconductor chip 40 is mounted) on which the smaller semiconductor chip is mounted than the surface (the first surface 14 on which the first semiconductor chip 20 is mounted) on which the large semiconductor chip is mounted. The formed second surface 16) may have a larger amount of expansion / contraction due to heating / cooling. Then, the wiring board may be warped due to the difference in expansion and contraction. By the way, in the semiconductor device 1, as described above, the planar area of the portion of the first conductive pattern 30 disposed outside the first semiconductor chip 20 is the second semiconductor in the second conductive pattern 50. It is larger than the plane area of the portion arranged outside the chip 40. Further, the first conductive pattern 30 has a larger linear expansion coefficient than the wiring substrate 10. That is, the first conductive pattern 30 expands and contracts more than the wiring substrate 10. The first conductive pattern 30 is formed directly on the first surface 14. Therefore, according to the semiconductor device 1, the amount of expansion / contraction of the first surface 14 of the wiring substrate 10 increases due to the influence of expansion / contraction of the first conductive pattern 30. That is, according to the semiconductor device 1, the difference between the expansion and contraction amounts of the first and second surfaces 14 and 16 can be reduced. Therefore, it is possible to provide a semiconductor device that is less likely to warp the semiconductor device and has excellent mountability. The first conductive pattern 30 may be formed so as to overlap the external terminal 60. According to this, since the wiring substrate 10 can be flattened in the region where the external terminal 60 is formed, a semiconductor device having excellent mountability can be provided. FIG. 2 shows a circuit board 1000 on which the semiconductor device 1 is mounted. As an electronic device having the semiconductor device 1, FIG. 3 shows a notebook personal computer 2000 and FIG. 4 shows a mobile phone 3000.

以下、本発明を適用した実施の形態に係る半導体装置の製造方法について説明する。図５〜図９は、本発明を適用した実施の形態に係る半導体装置の製造方法について説明するための図である。   A method for manufacturing a semiconductor device according to an embodiment to which the present invention is applied will be described below. 5 to 9 are diagrams for explaining a method of manufacturing a semiconductor device according to an embodiment to which the present invention is applied.

本実施の形態に係る半導体装置の製造方法は、図５に示す、配線基板１０を用意することを含む。なお、図５は、配線基板１０の断面図である。配線基板１０は、既に説明したいずれかの構成をなしていてもよい。すなわち、配線基板１０は、第１の面１４に直接形成された第１の導電パターン３０と、第２の面１６に直接形成された第２の導電パターン５０とを有する。第１の導電パターン３０は、配線基板１０よりも線膨張係数が大きい。そして、第１の導電パターン３０における第１の半導体チップ２０を搭載するための領域よりも外側に配置された部分の平面面積は、第２の導電パターン５０における第２の半導体チップ４０を搭載するための領域よりも外側に配置された部分の平面面積よりも大きい。なお、第１の導電パターン３０は、外部端子６０を形成するための領域（ランド１５）とオーバーラップするように形成されていてもよい。   The method for manufacturing a semiconductor device according to the present embodiment includes preparing a wiring board 10 shown in FIG. FIG. 5 is a cross-sectional view of the wiring board 10. The wiring board 10 may have any of the configurations already described. That is, the wiring substrate 10 has a first conductive pattern 30 directly formed on the first surface 14 and a second conductive pattern 50 formed directly on the second surface 16. The first conductive pattern 30 has a larger coefficient of linear expansion than the wiring board 10. The planar area of the portion disposed outside the region for mounting the first semiconductor chip 20 in the first conductive pattern 30 mounts the second semiconductor chip 40 in the second conductive pattern 50. It is larger than the plane area of the part arrange | positioned outside the area | region for. The first conductive pattern 30 may be formed so as to overlap with a region (land 15) for forming the external terminal 60.

本実施の形態に係る半導体装置の製造方法は、配線基板１０に、第１の半導体チップ２０を搭載することを含む。以下、本工程について説明する。はじめに、配線基板１０の第１の面１４に、樹脂材料３６を設けてもよい（図６（Ａ）参照）。樹脂材料３６は、ペースト状で設けてもよくフィルム状で設けてもよい。樹脂材料３６は、内部に導電粒子が分散された異方性導電材料であってもよい。あるいは、樹脂材料３６は、絶縁性の材料であってもよい。そして、図６（Ａ）に示すように、配線基板１０上に第１の半導体チップ２０を配置してもよい。その後、図６（Ｂ）に示すように、配線基板１０に第１の半導体チップ２０を搭載してもよい。第１の半導体チップ２０を、樹脂材料３６を押し広げながら配線基板１０に向かって押圧して、配線基板１０に搭載してもよい。このとき、電極２４と配線パターン１２（ランド１３）とを対向させて電気的に接続してもよい。また、第１の半導体チップ２０を搭載する工程は、配線基板１０及び第１の半導体チップ２０の少なくとも一方を加熱しながら行ってもよい。なお、本工程によって、電極２４とランド１３とを固着してもよい。例えば、電極２４とランド１３との間に共晶合金層を形成することによって、両者を接合（共晶合金接合）してもよい。   The method for manufacturing a semiconductor device according to the present embodiment includes mounting the first semiconductor chip 20 on the wiring substrate 10. Hereinafter, this step will be described. First, the resin material 36 may be provided on the first surface 14 of the wiring board 10 (see FIG. 6A). The resin material 36 may be provided in a paste form or a film form. The resin material 36 may be an anisotropic conductive material in which conductive particles are dispersed. Alternatively, the resin material 36 may be an insulating material. Then, as shown in FIG. 6A, the first semiconductor chip 20 may be disposed on the wiring substrate 10. Thereafter, as shown in FIG. 6B, the first semiconductor chip 20 may be mounted on the wiring substrate 10. The first semiconductor chip 20 may be mounted on the wiring board 10 by pressing toward the wiring board 10 while spreading the resin material 36. At this time, the electrode 24 and the wiring pattern 12 (land 13) may be opposed to each other and electrically connected. The step of mounting the first semiconductor chip 20 may be performed while heating at least one of the wiring substrate 10 and the first semiconductor chip 20. In addition, you may adhere the electrode 24 and the land 13 by this process. For example, by forming a eutectic alloy layer between the electrode 24 and the land 13, both may be joined (eutectic alloy joining).

本実施の形態に係る半導体装置の製造方法は、図７に示すように、配線基板１０の第１の面１４に、配線基板１０と第１の半導体チップ２０とを接着する第１の樹脂部３５を形成することを含んでいてもよい。第１の樹脂部３５は、樹脂材料３６を硬化させることによって形成してもよい。樹脂材料３６を硬化させる方法は特に限定されず、樹脂材料３６に適したいずれかの方法を選択してもよい。樹脂材料３６は、例えば加熱により硬化させてもよい。   As shown in FIG. 7, the method for manufacturing the semiconductor device according to the present embodiment includes a first resin portion that bonds the wiring substrate 10 and the first semiconductor chip 20 to the first surface 14 of the wiring substrate 10. Forming 35 may be included. The first resin portion 35 may be formed by curing the resin material 36. The method for curing the resin material 36 is not particularly limited, and any method suitable for the resin material 36 may be selected. The resin material 36 may be cured by heating, for example.

本実施の形態に係る半導体装置の製造方法は、配線基板１０の第２の面１６に、第２の半導体チップ４０を搭載することを含む。第２の半導体チップ４０は、第１の半導体チップ２０よりも小さい半導体チップである。第２の半導体チップ４０を搭載する方法は特に限定されない。例えば、第２の面１６に樹脂材料５６を設け（図８（Ａ）参照）、その後、第２の半導体チップ４０を、樹脂材料５６を押し広げながら配線基板１０に向かって押圧して、配線基板１０に第２の半導体チップ４０を搭載してもよい（図８（Ｂ）参照）。このとき、第２の半導体チップ４０の電極４４と配線基板１０のランド１３とを対向させて電気的に接続してもよい。なお、配線基板１０及び第２の半導体チップ４０の少なくとも一方を加熱しながら、第２の半導体チップ４０を搭載してもよい。本工程によって、電極４４とランド１３とを固着してもよい。   The method for manufacturing a semiconductor device according to the present embodiment includes mounting the second semiconductor chip 40 on the second surface 16 of the wiring substrate 10. The second semiconductor chip 40 is a semiconductor chip that is smaller than the first semiconductor chip 20. The method for mounting the second semiconductor chip 40 is not particularly limited. For example, a resin material 56 is provided on the second surface 16 (see FIG. 8A), and then the second semiconductor chip 40 is pressed toward the wiring substrate 10 while spreading the resin material 56, thereby wiring. The second semiconductor chip 40 may be mounted on the substrate 10 (see FIG. 8B). At this time, the electrode 44 of the second semiconductor chip 40 and the land 13 of the wiring board 10 may be opposed to each other and electrically connected. The second semiconductor chip 40 may be mounted while heating at least one of the wiring substrate 10 and the second semiconductor chip 40. The electrode 44 and the land 13 may be fixed by this step.

本実施の形態に係る半導体装置の製造方法は、図９に示すように、配線基板１０の第２の面１６に、配線基板１０と第２の半導体チップ４０とを接着する第２の樹脂部５５を形成することを含んでいてもよい。第２の樹脂部５５は、樹脂材料５６を硬化させることによって形成してもよい。   As shown in FIG. 9, the method for manufacturing a semiconductor device according to the present embodiment has a second resin portion that bonds the wiring substrate 10 and the second semiconductor chip 40 to the second surface 16 of the wiring substrate 10. Forming 55 may be included. The second resin portion 55 may be formed by curing the resin material 56.

なお、配線基板１０に第１及び第２の半導体チップ２０，４０を搭載する方法は上述の内容に限られるものではない。例えば、第１及び第２の半導体チップ２０，４０は、同時に搭載してもよい。また、第１及び第２の半導体チップ２０，４０を別々に搭載する場合には、第１及び第２の半導体チップ２０，４０のいずれを先に搭載してもよい。また、樹脂材料３６，５６についても、第１及び第２の半導体チップ２０，４０を搭載した後に設けてもよい。あるいは、第１及び第２の樹脂部３５，５５を有しない半導体装置を製造してもよい。   Note that the method of mounting the first and second semiconductor chips 20 and 40 on the wiring board 10 is not limited to the above-described contents. For example, the first and second semiconductor chips 20 and 40 may be mounted simultaneously. Further, when the first and second semiconductor chips 20 and 40 are separately mounted, any of the first and second semiconductor chips 20 and 40 may be mounted first. Also, the resin materials 36 and 56 may be provided after the first and second semiconductor chips 20 and 40 are mounted. Alternatively, a semiconductor device that does not include the first and second resin portions 35 and 55 may be manufactured.

本実施の形態に係る半導体装置の製造方法は、配線基板１０の第２の面１６に外部端子６０を形成することを含んでいてもよい。以上の工程によって、半導体装置１を製造してもよい（図１参照）。一般的に、半導体装置を製造する際には、配線基板に熱が加えられる。具体的には、配線基板１０に第１及び第２の半導体チップ２０，４０を搭載する工程や、樹脂材料３６，５６を硬化させる工程は、加熱された環境で行われることがある。すなわち、半導体装置を製造する工程で、配線基板は加熱・冷却されることがある。そのため、半導体装置を製造する工程で、配線基板１０が膨張・収縮することがあった。そして、配線基板のそれぞれの面に大きさの異なる半導体チップを搭載する場合、配線基板の両面で、膨張・収縮量が異なることがあった。具体的には、大きい半導体チップが搭載された面（第１の半導体チップ２０が搭載された第１の面１４）よりも、小さい半導体チップが搭載された面（第２の半導体チップ４０が搭載された第２の面１６）の方が、加熱・冷却による膨張・収縮量が大きくなることがあった。そして、膨張・収縮量の違いが原因となって、半導体装置を製造する工程中に、配線基板１０に反りが生じることがあった。ところで、本実施の形態に係る半導体装置の製造方法では、先に説明したように、第１の導電パターン３０における第１の半導体チップ２０を搭載するための領域の外側に配置された部分の平面面積は、第２の導電パターン５０における第２の半導体チップ４０を搭載するための領域の外側に配置された部分の平面面積よりも大きい。そして、第１の導電パターン３０は、配線基板１０よりも線膨張係数が大きく、かつ、第１の面１４に直接形成されてなる。そのため、第１の面１４の膨張・収縮量を大きくすることができ、配線基板１０の第１及び第２の面１４，１６の膨張・収縮量の差を小さくすることができる。そのため、配線基板１０が平坦な、実装性に優れた半導体装置を製造することができる。   The manufacturing method of the semiconductor device according to the present embodiment may include forming the external terminal 60 on the second surface 16 of the wiring substrate 10. The semiconductor device 1 may be manufactured through the above steps (see FIG. 1). Generally, when a semiconductor device is manufactured, heat is applied to the wiring board. Specifically, the process of mounting the first and second semiconductor chips 20 and 40 on the wiring substrate 10 and the process of curing the resin materials 36 and 56 may be performed in a heated environment. That is, the wiring board may be heated and cooled in the process of manufacturing the semiconductor device. Therefore, the wiring board 10 may expand and contract in the process of manufacturing the semiconductor device. When semiconductor chips having different sizes are mounted on the respective surfaces of the wiring board, the amount of expansion / contraction may be different on both surfaces of the wiring board. Specifically, the surface (the second semiconductor chip 40 is mounted) on which the smaller semiconductor chip is mounted than the surface (the first surface 14 on which the first semiconductor chip 20 is mounted) on which the large semiconductor chip is mounted. The formed second surface 16) may have a larger amount of expansion / contraction due to heating / cooling. Then, due to the difference in expansion / contraction amount, the wiring substrate 10 may be warped during the process of manufacturing the semiconductor device. By the way, in the method of manufacturing a semiconductor device according to the present embodiment, as described above, the plane of the portion disposed outside the region for mounting the first semiconductor chip 20 in the first conductive pattern 30. The area is larger than the planar area of the portion of the second conductive pattern 50 disposed outside the region for mounting the second semiconductor chip 40. The first conductive pattern 30 has a linear expansion coefficient larger than that of the wiring substrate 10 and is directly formed on the first surface 14. Therefore, the amount of expansion / contraction of the first surface 14 can be increased, and the difference between the amount of expansion / contraction of the first and second surfaces 14, 16 of the wiring board 10 can be reduced. Therefore, it is possible to manufacture a semiconductor device having a flat wiring substrate 10 and excellent mountability.

なお、本発明は、上述した実施の形態に限定されるものではなく、種々の変形が可能である。例えば、本発明は、実施の形態で説明した構成と実質的に同一の構成（例えば、機能、方法及び結果が同一の構成、あるいは目的及び効果が同一の構成）を含む。また、本発明は、実施の形態で説明した構成の本質的でない部分を置き換えた構成を含む。また、本発明は、実施の形態で説明した構成と同一の作用効果を奏する構成又は同一の目的を達成することができる構成を含む。また、本発明は、実施の形態で説明した構成に公知技術を付加した構成を含む。   In addition, this invention is not limited to embodiment mentioned above, A various deformation | transformation is possible. For example, the present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same objects and effects). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that achieves the same effect as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

図１は、本発明を適用した実施の形態に係る半導体装置について説明するための図である。FIG. 1 is a diagram for explaining a semiconductor device according to an embodiment to which the present invention is applied. 図２は、本発明を適用した実施の形態に係る半導体装置が実装された回路基板を示す図である。FIG. 2 is a diagram showing a circuit board on which a semiconductor device according to an embodiment to which the present invention is applied is mounted. 図３は、本発明を適用した実施の形態に係る半導体装置を有する電子機器を示す図である。FIG. 3 is a diagram showing an electronic apparatus having a semiconductor device according to an embodiment to which the present invention is applied. 図４は、本発明を適用した実施の形態に係る半導体装置を有する電子機器を示す図である。FIG. 4 is a diagram showing an electronic apparatus having a semiconductor device according to an embodiment to which the present invention is applied. 図５は、本発明を適用した実施の形態に係る半導体装置の製造方法について説明するための図である。FIG. 5 is a diagram for explaining a method of manufacturing a semiconductor device according to an embodiment to which the present invention is applied. 図６（Ａ）及び図６（Ｂ）は、本発明を適用した実施の形態に係る半導体装置の製造方法について説明するための図である。6A and 6B are views for explaining a method for manufacturing a semiconductor device according to an embodiment to which the present invention is applied. 図７は、本発明を適用した実施の形態に係る半導体装置の製造方法について説明するための図である。FIG. 7 is a diagram for explaining a method of manufacturing a semiconductor device according to an embodiment to which the present invention is applied. 図８（Ａ）及び図８（Ｂ）は、本発明を適用した実施の形態に係る半導体装置の製造方法について説明するための図である。8A and 8B are views for explaining a method for manufacturing a semiconductor device according to an embodiment to which the present invention is applied. 図９は、本発明を適用した実施の形態に係る半導体装置の製造方法について説明するための図である。FIG. 9 is a diagram for explaining a method of manufacturing a semiconductor device according to an embodiment to which the present invention is applied.

符号の説明Explanation of symbols

１０…配線基板、 １２…配線パターン、 １３…ランド、 １５…ランド、 ２０…第１の半導体チップ、 ２２…集積回路、 ２４…電極、 ３０…第１の導電パターン、 ３５…第１の樹脂部、 ３６…樹脂材料、 ４０…第２の半導体チップ、 ４２…集積回路、 ４４…電極、 ５０…第２の導電パターン、 ５５…第２の樹脂部、 ５６…樹脂材料、 ６０…外部端子   DESCRIPTION OF SYMBOLS 10 ... Wiring board, 12 ... Wiring pattern, 13 ... Land, 15 ... Land, 20 ... 1st semiconductor chip, 22 ... Integrated circuit, 24 ... Electrode, 30 ... 1st electroconductive pattern, 35 ... 1st resin part 36 ... Resin material, 40 ... Second semiconductor chip, 42 ... Integrated circuit, 44 ... Electrode, 50 ... Second conductive pattern, 55 ... Second resin part, 56 ... Resin material, 60 ... External terminal

Claims (6)

配線基板と、
前記配線基板の第１の面に搭載されたシリコンチップである、第１の半導体チップと、
前記第１の面に直接形成された第１の導電パターンと、
前記配線基板の第２の面に搭載されたシリコンチップであり、前記第１の半導体チップよりも小さい第２の半導体チップと、
前記第２の面に直接形成され、前記第１の導電パターンと同じ材料で形成された第２の導電パターンと、
を有し、
前記第１の半導体チップ及び前記第２の半導体チップは、前記配線基板よりも線膨張係数が小さく、
前記第１の導電パターン及び前記第２の導電パターンは、前記配線基板よりも線膨張係数が大きく、
前記第１の導電パターンにおける前記第１の半導体チップよりも外側に配置された部分の平面面積は、前記第２の導電パターンにおける前記第２の半導体チップよりも外側に配置された部分の平面面積よりも大きい半導体装置。 A wiring board;
A first semiconductor chip, which is a silicon chip mounted on the first surface of the wiring board;
A first conductive pattern formed directly on the first surface;
A second semiconductor chip that is a silicon chip mounted on the second surface of the wiring board and is smaller than the first semiconductor chip;
A second conductive pattern formed directly on the second surface and made of the same material as the first conductive pattern;
Have
The first semiconductor chip and the second semiconductor chip have a smaller linear expansion coefficient than the wiring board,
The first conductive pattern and the second conductive pattern have a larger linear expansion coefficient than the wiring board,
The planar area of the portion arranged outside the first semiconductor chip in the first conductive pattern is the planar area of the portion arranged outside the second semiconductor chip in the second conductive pattern. Larger semiconductor device. 請求項１記載の半導体装置において、
前記第１及び第２の導電パターンは、同じ厚みに形成されてなる半導体装置。 The semiconductor device according to claim 1 ,
The semiconductor device in which the first and second conductive patterns are formed to have the same thickness. 請求項１又は請求項２のいずれかに記載の半導体装置において、
前記配線基板の前記第２の面には外部端子が形成されてなり、
前記第１の導電パターンは、前記外部端子とオーバーラップするように形成されてなる半導体装置。 In the semiconductor device according to claim 1 or 2 ,
External terminals are formed on the second surface of the wiring board,
The semiconductor device, wherein the first conductive pattern is formed so as to overlap the external terminal. 配線基板を用意すること、
前記配線基板の第１の面にシリコンチップである第１の半導体チップを搭載すること、及び、
前記配線基板の第２の面に、前記第１の半導体チップよりも小さいシリコンチップである第２の半導体チップを搭載することを含み、
前記配線基板は、前記第１の面に直接形成された第１の導電パターンと、前記第２の面に直接形成され、前記第１の導電パターンと同じ材料で形成された第２の導電パターンとを有し、
前記第１の半導体チップ及び前記第２の半導体チップは、前記配線基板よりも線膨張係数が小さく、
前記第１の導電パターン及び前記第２の導電パターンは、前記配線基板よりも線膨張係数が大きく、
前記第１の導電パターンにおける前記第１の半導体チップを搭載するための領域よりも外側に配置された部分の平面面積は、前記第２の導電パターンにおける前記第２の半導体チップを搭載するための領域よりも外側に配置された部分の平面面積よりも大きい半導体装置の製造方法。 Preparing a wiring board,
Mounting a first semiconductor chip, which is a silicon chip, on the first surface of the wiring board; and
Mounting a second semiconductor chip, which is a silicon chip smaller than the first semiconductor chip, on the second surface of the wiring board;
The wiring board includes a first conductive pattern directly formed on the first surface and a second conductive pattern formed directly on the second surface and made of the same material as the first conductive pattern. And
The first semiconductor chip and the second semiconductor chip have a smaller linear expansion coefficient than the wiring board,
The first conductive pattern and the second conductive pattern have a larger linear expansion coefficient than the wiring board,
The planar area of the portion arranged outside the region for mounting the first semiconductor chip in the first conductive pattern is for mounting the second semiconductor chip in the second conductive pattern. A manufacturing method of a semiconductor device which is larger than a planar area of a portion arranged outside a region. 請求項４記載の半導体装置の製造方法において、
前記第１及び第２の導電パターンは、同じ厚みに形成されてなる半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 4 ,
The method for manufacturing a semiconductor device, wherein the first and second conductive patterns are formed to have the same thickness. 請求項４又は請求項５のいずれかに記載の半導体装置の製造方法において、
前記配線基板の前記第２の面に外部端子を形成することをさらに含み、
前記第１の導電パターンは、前記外部端子を形成するための領域とオーバーラップするように形成されてなる半導体装置の製造方法。 In the manufacturing method of the semiconductor device in any one of Claim 4 or Claim 5 ,
Forming an external terminal on the second surface of the wiring board;
The method of manufacturing a semiconductor device, wherein the first conductive pattern is formed so as to overlap with a region for forming the external terminal.
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