JP4364074B2 - 半導体素子の製造方法 - Google Patents
半導体素子の製造方法 Download PDFInfo
- Publication number
- JP4364074B2 JP4364074B2 JP2004190919A JP2004190919A JP4364074B2 JP 4364074 B2 JP4364074 B2 JP 4364074B2 JP 2004190919 A JP2004190919 A JP 2004190919A JP 2004190919 A JP2004190919 A JP 2004190919A JP 4364074 B2 JP4364074 B2 JP 4364074B2
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- JP
- Japan
- Prior art keywords
- bump
- flux
- layer
- bumps
- solder paste
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1131—Manufacturing methods by local deposition of the material of the bump connector in liquid form
- H01L2224/1132—Screen printing, i.e. using a stencil
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/118—Post-treatment of the bump connector
- H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
- H01L2224/11849—Reflowing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
- H01L2224/11901—Methods of manufacturing bump connectors involving a specific sequence of method steps with repetition of the same manufacturing step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13075—Plural core members
- H01L2224/1308—Plural core members being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
(1)まず、下地金属層23上に半田ペーストを塗布し、これを加熱して球状の下層バンプ25xを形成する(図5(a))。
まず、本発明の半導体素子について図1を用いて詳細に説明する。
次に本発明の半導体素子の製造方法について、上述の半導体素子を製造する場合を例に図2を用いて説明する。図2の(a)〜(g)は半導体素子の製造方法を説明するための各工程の断面図である。
2・・・回路配線
3・・・下地金属層
4・・・パッシベーション層
5・・・半田バンプ
5x・・・下層バンプ
5y・・・上層バンプ
5’,5”・・・半田ペースト
6・・・フラックス
7・・・レジスト層
7’・・・レジスト材料
8・・・印刷マスク
9・・・押圧手段(スキージ)
10・・・フラックス転写テーブル
11・・・ウェハー吸着ヘッド
Claims (2)
- 半導体基板上に形成された下地金属層上に、下層バンプを形成する第1の工程と、
前記下層バンプを平面視したときに該下層バンプの中央領域にフラックスを塗布する第2の工程と、
前記下層バンプの中央領域を除く周囲領域に、前記フラックスが露出するようにレジスト層を形成する第3の工程と、
前記下層バンプの中央領域上に半田ペーストを供給するとともに、該半田ペーストを加熱して、当該下層バンプ上に上層バンプを形成する第4の工程とを備えたことを特徴とする半導体素子の製造方法。 - 前記第1の工程において、前記下地金属層上に第2の半田ペーストを供給するとともに、該第2の半田ペーストを加熱して前記下層バンプを形成し、
前記半田ペースト中に含まれているフラックスの量は、前記第2の半田ペースト中に含まれているフラックスの量に比べて少なくすることを特徴とする請求項1に記載の半導体素子の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004190919A JP4364074B2 (ja) | 2004-06-29 | 2004-06-29 | 半導体素子の製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004190919A JP4364074B2 (ja) | 2004-06-29 | 2004-06-29 | 半導体素子の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006013293A JP2006013293A (ja) | 2006-01-12 |
JP4364074B2 true JP4364074B2 (ja) | 2009-11-11 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004190919A Expired - Fee Related JP4364074B2 (ja) | 2004-06-29 | 2004-06-29 | 半導体素子の製造方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4364074B2 (ja) |
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2004
- 2004-06-29 JP JP2004190919A patent/JP4364074B2/ja not_active Expired - Fee Related
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JP2006013293A (ja) | 2006-01-12 |
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