JP4327731B2 - 低密度パリティ検査符号を用いる符号化器と、その符号化方法 - Google Patents
低密度パリティ検査符号を用いる符号化器と、その符号化方法 Download PDFInfo
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- JP4327731B2 JP4327731B2 JP2004553278A JP2004553278A JP4327731B2 JP 4327731 B2 JP4327731 B2 JP 4327731B2 JP 2004553278 A JP2004553278 A JP 2004553278A JP 2004553278 A JP2004553278 A JP 2004553278A JP 4327731 B2 JP4327731 B2 JP 4327731B2
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/1177—Regular LDPC codes with parity-check matrices wherein all rows and columns have the same row weight and column weight, respectively
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/118—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure
- H03M13/1182—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure wherein the structure of the parity-check matrix is obtained by reordering of a random parity-check matrix
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- Theoretical Computer Science (AREA)
- Error Detection And Correction (AREA)
- Detection And Correction Of Errors (AREA)
Description
更に、前記符号語生成器は、前記パリティ検査行列Hを行列Aと行列Bに分解するAB分解部;前記行列Hに対してピボッティングを遂行するピボッティング部;ピボッティングされた行列に対してビット反転を遂行するビット反転部;前記行列Aを行列Lと行列Uに分解するLU分解部;及び前記各行列A、B、L及びUに論理演算を施す符号語生成部を含む。
a)パリティ検査行列Hを生成する段階;
b)前記行列Hを非特異行列に再構成する段階;
c)前記非特異行列を行列Aと行列Bに分解して保存する段階;
d)ピボッティングを行って実行結果を検査する段階;
e)該検査結果が1であれば、行列Aを行列Lと行列Uに分解して保存し、前記各行列A、B、L及びUから符号語を計算する段階;及び
f)前記d)段階で検査結果が1でなければ、ビット反転を行った後、再びピボッティングを遂行する段階を含む。
i)前記B行列とソース入力情報であるべクトルsに所定の演算を施してべクトルzを求める段階;ii)前記べクトルzと前記行列Lに所定の演算を施してべクトルyを求める段階;及び、iii)前記べクトルyと前記行列Uに所定の演算を施して符号語cを求める段階を含む。
このように生成されたパリティ検査行列の符号化を効率的なハードウェア回路に実現するためには、行と列の位置のみを保存してメモリ使用量を減少させる。また、符号化器の全体構造は、高速移動通信システムに適したパイプライン方式で動作するように構成する。
Claims (9)
- LDPC符号を用いる符号化器において、
パリティを検査するための行列Hを生成するパリティ検査行列生成器;及び
前記パリティ検査行列生成器で生成された行列Hを処理して符号語を生成する符号語生成器を含み、
前記符号語生成器は、
前記行列Hを行列A及び行列Bに分解するAB分解部;
前記行列Hに対してピボッティングを遂行するピボット部;
ピボッティングされた行列に対してビット反転を遂行するビット反転部;
前記行列Aを行列Lと行列Uに分解するLU分解部;及び
前記各行列A、B、L及びUに論理演算を施して符号語を生成する符号語生成部
を含むことを特徴とする、LDPC符号を用いる符号化器。 - 前記符号語生成部は、
前記行列Bとソース入力情報であるべクトルsに所定の演算を施してべクトルzを求める第1演算部;
前記べクトルzと前記行列Lに所定の演算を施してべクトルyを求める第2演算部;及び
前記べクトルyと前記行列Uに所定の演算を施して符号語cを求める第3演算部
を含むことを特徴とする、請求項1に記載の符号化器。 - 前記第1演算部は、前記べクトルsの長さを掛ける論理積演算をし、論理和演算を行って前記べクトルzを生成することを特徴とする、請求項2に記載の符号化器。
- 前記符号語生成部は、前記各行列A、B、L及びUを保存するためのメモリをさらに含むことを特徴とする、請求項1に記載の符号化器。
- 前記符号語生成部は、パイプライン方式で論理演算を行うため、また論理演算で計算された結果を保存するためのレジスタをさらに含むことを特徴とする、請求項1に記載の符号化器。
- LDPC符号を用いる符号化方法において、
a)パリティ検査行列Hを生成する段階;
b)前記H行列を非特異行列に再構成する段階;
c)前記非特異行列を行列Aと行列Bに分解して保存する段階;
d)ピボッティングを行って実行結果を検査する段階;
e)該検査結果が1であれば、行列Aを行列Lと行列Uに分解して保存し、前記各行列A、B、L及びU から符号語を算出する段階;及び
f)前記d)段階で検査結果が1でなければ、ビット反転を行った後、ピボッティングを遂行する段階
を含むことを特徴とする、LDPC符号を用いる符号化方法。 - 前記e)段階は、
i)前記B行列とソース入力情報であるべクトルsに所定の演算を施してべクトルzを求める段階;
ii)前記べクトルzと前記行列Lに所定の演算を施してべクトルyを求める段階;及び
iii)前記べクトルyと前記行列Uに所定の演算を施して符号語cを求める段階
を含むことを特徴とする、請求項6に記載の符号化方法。 - 前記i)段階は、前記べクトルsの長さを掛ける論理積演算をして前記べクトルzを生成することを特徴とする、請求項7に記載の符号化方法。
- 前記i)、ii)及びiii)段階において、パイプライン方式で所定の演算が行われることを特徴とする、請求項7に記載の符号化方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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KR10-2002-0072642A KR100502609B1 (ko) | 2002-11-21 | 2002-11-21 | Ldpc 코드를 이용한 부호화기 및 부호화 방법 |
PCT/KR2003/002532 WO2004047019A2 (en) | 2002-11-21 | 2003-11-21 | Encoder using low density parity check codes and encoding method thereof |
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JP2006507731A JP2006507731A (ja) | 2006-03-02 |
JP4327731B2 true JP4327731B2 (ja) | 2009-09-09 |
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JP2004553278A Expired - Fee Related JP4327731B2 (ja) | 2002-11-21 | 2003-11-21 | 低密度パリティ検査符号を用いる符号化器と、その符号化方法 |
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US (1) | US7178085B2 (ja) |
JP (1) | JP4327731B2 (ja) |
KR (1) | KR100502609B1 (ja) |
CN (1) | CN1739244A (ja) |
AU (1) | AU2003282425A1 (ja) |
WO (1) | WO2004047019A2 (ja) |
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US20030033570A1 (en) * | 2001-05-09 | 2003-02-13 | Khannanov Roman R. | Method and apparatus for encoding and decoding low density parity check codes and low density turbo product codes |
KR100502609B1 (ko) | 2002-11-21 | 2005-07-20 | 한국전자통신연구원 | Ldpc 코드를 이용한 부호화기 및 부호화 방법 |
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2002
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AU2003282425A1 (en) | 2004-06-15 |
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JP2006507731A (ja) | 2006-03-02 |
KR100502609B1 (ko) | 2005-07-20 |
WO2004047019A2 (en) | 2004-06-03 |
US7178085B2 (en) | 2007-02-13 |
CN1739244A (zh) | 2006-02-22 |
KR20040044590A (ko) | 2004-05-31 |
AU2003282425A8 (en) | 2004-06-15 |
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