JP4317471B2 - 最適回路化パターンを有するチップ・キャリヤ - Google Patents
最適回路化パターンを有するチップ・キャリヤ Download PDFInfo
- Publication number
- JP4317471B2 JP4317471B2 JP2004075099A JP2004075099A JP4317471B2 JP 4317471 B2 JP4317471 B2 JP 4317471B2 JP 2004075099 A JP2004075099 A JP 2004075099A JP 2004075099 A JP2004075099 A JP 2004075099A JP 4317471 B2 JP4317471 B2 JP 4317471B2
- Authority
- JP
- Japan
- Prior art keywords
- chip carrier
- conductor
- circuit board
- printed circuit
- solder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
- H05K1/113—Via provided in pad; Pad over filled via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
- H05K1/114—Pad being close to via, but not surrounding the via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
- H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/09454—Inner lands, i.e. lands around via or plated through-hole in internal layer of multilayer PCB
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/09472—Recessed pad for surface mounting; Recessed electrode of component
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09509—Blind vias, i.e. vias having one side closed
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/0979—Redundant conductors or connections, i.e. more than one current path between two points
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10227—Other objects, e.g. metallic pieces
- H05K2201/1031—Surface mounted metallic connector elements
- H05K2201/10318—Surface mounted metallic pins
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
- H05K3/3426—Leaded components characterised by the leads
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49147—Assembling terminal to base
- Y10T29/49149—Assembling terminal to base by metal fusion bonding
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
前記角の表面領域上の導体と、
前記基板の前記角の表面領域および前記導体上の絶縁層と、
前記導体に向かい合っている前記絶縁層の表面上の半田パッドとを備える可撓性チップ・キャリヤであって、前記半田パッドが、前記絶縁層の開口を通して前記導体に電気的に接続され、さらに、前記チップ・キャリヤが曲げられた場合前記導体の割れが抑制されるように、実質的に前記導体の上に重なっている可撓性チップ・キャリヤ。
(2)前記回路化基板が、4つの角の表面領域を含む、上記(1)に記載の可撓性チップ・キャリヤ。
(3)前記半田パッドが、所定の形状を有し、前記導体を実質的に完全に覆うように前記導体の上に配置されている、上記(2)に記載の可撓性チップ・キャリヤ。
(4)前記導体が、少なくとも4つの同軸列部分に配列された複数の前記導体の1つを含む、上記(3)に記載の可撓性チップ・キャリヤ。
(5)前記複数の導体のうちの選ばれたものが、ドッグボーンの形を含む、上記(4)に記載の可撓性チップ・キャリヤ。
(6)前記半田パッドが、少なくとも4つの同軸列部分に配列された複数の前記半田パッドのうちの1つを含む、上記(5)に記載の可撓性チップ・キャリヤ。
(7)前記複数の前記半田パッドの各々が、実質的に環状の形を含む、上記(6)に記載の可撓性チップ・キャリヤ。
(8)前記半田パッドが、ボール・グリッド・アレイのパッドを含む、上記(3)に記載の可撓性チップ・キャリヤ。
(9)所定の形状を有する少なくとも1つの他の導体が、前記4つの角の表面領域のうちの少なくとも1つに近接して位置付けされ、前記半田パッドが、前記少なくとも1つの他の導体をただ部分的にだけ覆うように、前記少なくとも1つの他の導体の上に配置された所定の形状を有する少なくとも1つの他の半田パッドを含む、上記(3)に記載の可撓性チップ・キャリヤ。
(10)前記絶縁層が、半田マスクを含む、上記(1)に記載の可撓性チップ・キャリヤ。
(11)前記半田パッドが、その上に位置付けされた電気要素を含む、上記(1)に記載の可撓性チップ・キャリヤ。
(12)前記電気要素が、半田ボールを含む、上記(11)に記載の可撓性チップ・キャリヤ。
(13)前記半田ボールが、回路化基板に電気的に接続されている、上記(12)に記載の可撓性チップ・キャリヤ。
(14)前記角の表面領域が、角でない表面の縁領域である、上記(2)に記載の可撓性チップ・キャリヤ。
(15)前記半田パッドが、所定の形状を有し、さらに、前記導体を実質的に完全に覆うように前記導体の上に配置されている、上記(14)に記載の可撓性チップ・キャリヤ。
(16)前記導体が、少なくとも4つの同軸列部分に配列された複数の前記導体のうちの1つを含む、上記(15)に記載の可撓性チップ・キャリヤ。
(17)前記複数の導体のうちの選ばれたものが、ドッグボーンの形を含む、上記(16)に記載の可撓性チップ・キャリヤ。
(18)前記半田パッドが、少なくとも4つの同軸列部分に配列された複数の前記半田パッドのうちの1つを含む、上記(17)に記載の可撓性チップ・キャリヤ。
(19)前記複数の前記半田パッドの各々が、実質的に環状の形を含む、上記(18)に記載の可撓性チップ・キャリヤ。
(20)前記半田パッドが、ボール・グリッド・アレイ(BGA)のパッドを含む、上記(15)に記載の可撓性チップ・キャリヤ。
(21)所定の形状を有する少なくとも1つの他の導体が、前記4つの角でない縁の表面領域のうちの少なくとも1つに近接して位置付けされ、前記半田パッドが、前記少なくとも1つの他の導体をただ部分的にだけ覆うように前記少なくとも1つの他の導体の上に配置された所定の形状を有する少なくとも1つの他の半田パッドを含む、上記(15)に記載の可撓性チップ・キャリヤ。
(22)前記絶縁層が、半田マスクを含む、上記(14)に記載の可撓性チップ・キャリヤ。
(23)前記半田パッドが、その上に位置付けされた電気要素を含む、上記(14)に記載の可撓性チップ・キャリヤ。
(24)前記電気要素が、半田ボールを含む、上記(23)に記載の可撓性チップ・キャリヤ。
(25)前記半田ボールが、回路化基板に電気的に接続されている、上記(24)に記載の可撓性チップ・キャリヤ。
112 回路化基板(チップ・キャリヤ)
115 回路化基板の表面領域
116 第1の回路パターン
117 ドッグボーン状導体
118 絶縁層
122 第2の回路パターン
124 開口
126 半田ボール
128 プリント回路基板
140 環状パッド(導電性部材)
141 回路化基板の角の表面領域
156 回路化基板の角でない表面の縁領域
142、144、146、148 列部分
158、160、162、164 縁の列部分
Claims (6)
- 半導体チップをプリント回路基板に接続するためのチップ・キャリヤであって、
該チップ・キャリヤは、
可撓性の基板と、
前記基板の、プリント回路基板側表面に備えられた導体、
前記導体のプリント回路基板側で前記導体を覆う絶縁層と、
前記絶縁層のプリント回路基板側表面上に備えられた半田パッドと、
を備え、
前記半田パッドの一つは、前記絶縁層を通る導電性の開口部を介して、前記導体の一つに接続されており、且つ、前記導体は、前記半田パッドの外周上の各点から、前記基板の厚み方向に沿ってプリント回路基板とは反対側に延ばした垂線が前記基板のプリント回路基板側表面と交わる点で画される領域内に在り、
前記導体の、前記基板と平行な方向の断面が、長方形であってその長手方向の両端に該長方形の幅より大きい直径を有する円形が接続されている形状を有し、及び、前記導体が前記開口部底面を、前記基板内に備えられたスルホールに接続する、チップ・キャリヤ。 - 前記半田パッドの、前記基板と平行な方向の断面が円形である、請求項1に記載のチップ・キャリヤ。
- 前記絶縁層が半田マスクを含む、請求項1項に記載のチップ・キャリヤ。
- 前記半田パッドのプリント回路基板側に接続された半田ボールをさらに含む、請求項1に記載のチップ・キャリヤ。
- 前記半田パッドが、ボール・グリッド・アレイのパッドである、請求項1に記載のチップ・キャリヤ。
- 前記チップ・キャリヤが、前記半田パッドと前記絶縁層と前記導体を、前記基板の角部に備える、請求項1に記載のチップ・キャリヤ。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/392,617 US7088008B2 (en) | 2003-03-20 | 2003-03-20 | Electronic package with optimized circuitization pattern |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2004289150A JP2004289150A (ja) | 2004-10-14 |
JP4317471B2 true JP4317471B2 (ja) | 2009-08-19 |
Family
ID=32987939
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004075099A Expired - Fee Related JP4317471B2 (ja) | 2003-03-20 | 2004-03-16 | 最適回路化パターンを有するチップ・キャリヤ |
Country Status (2)
Country | Link |
---|---|
US (3) | US7088008B2 (ja) |
JP (1) | JP4317471B2 (ja) |
Families Citing this family (37)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7205649B2 (en) * | 2003-06-30 | 2007-04-17 | Intel Corporation | Ball grid array copper balancing |
US7157646B2 (en) * | 2004-07-02 | 2007-01-02 | Endicott Interconnect Technologies, Inc. | Circuitized substrate with split conductive layer, method of making same, electrical assembly utilizing same, and information handling system utilizing same |
JP4432973B2 (ja) * | 2004-12-20 | 2010-03-17 | 株式会社村田製作所 | 積層セラミック電子部品の製造方法 |
WO2006097779A1 (en) * | 2005-03-16 | 2006-09-21 | Infineon Technologies Ag | Substrate, electronic component, electronic configuration and methods of producing the same |
US7542800B2 (en) * | 2005-04-05 | 2009-06-02 | Cardiac Pacemakers, Inc. | Method and apparatus for synchronizing neural stimulation to cardiac cycles |
US7334323B2 (en) * | 2005-07-11 | 2008-02-26 | Endicott Interconnect Technologies, Inc. | Method of making mutilayered circuitized substrate assembly having sintered paste connections |
US7342183B2 (en) * | 2005-07-11 | 2008-03-11 | Endicott Interconnect Technologies, Inc. | Circuitized substrate with sintered paste connections, multilayered substrate assembly, electrical assembly and information handling system utilizing same |
US7442879B2 (en) * | 2005-07-11 | 2008-10-28 | Endicott Interconect Technologies, Inc. | Circuitized substrate with solder-coated microparticle paste connections, multilayered substrate assembly, electrical assembly and information handling system utilizing same and method of making said substrate |
US8063315B2 (en) * | 2005-10-06 | 2011-11-22 | Endicott Interconnect Technologies, Inc. | Circuitized substrate with conductive paste, electrical assembly including said circuitized substrate and method of making said substrate |
US7378832B2 (en) * | 2006-08-22 | 2008-05-27 | Lecroy Corporation | Probing high-frequency signals |
US7659790B2 (en) * | 2006-08-22 | 2010-02-09 | Lecroy Corporation | High speed signal transmission line having reduced thickness regions |
CN101273494B (zh) * | 2006-10-27 | 2012-02-22 | 株式会社旭电化研究所 | 电连接构造 |
US7595454B2 (en) * | 2006-11-01 | 2009-09-29 | Endicott Interconnect Technologies, Inc. | Method of making a circuitized substrate with enhanced circuitry and electrical assembly utilizing said substrate |
US7547577B2 (en) * | 2006-11-14 | 2009-06-16 | Endicott Interconnect Technologies, Inc. | Method of making circuitized substrate with solder paste connections |
JP4522435B2 (ja) * | 2007-06-05 | 2010-08-11 | 富士通テン株式会社 | 高周波回路装置、及びレーダ装置 |
JP2009043844A (ja) * | 2007-08-07 | 2009-02-26 | Shinko Electric Ind Co Ltd | リードピン付き配線基板およびリードピン |
US8323798B2 (en) | 2007-09-28 | 2012-12-04 | Tri-Star Laminates, Inc. | Systems and methods for drilling holes in printed circuit boards |
US20090085207A1 (en) * | 2007-09-28 | 2009-04-02 | Texas Instruments, Inc. | Ball grid array substrate package and solder pad |
US7979151B2 (en) * | 2007-12-06 | 2011-07-12 | International Business Machines Corporation | Run-time dispatch system for enhanced product characterization capability |
US7929314B2 (en) * | 2008-06-20 | 2011-04-19 | International Business Machines Corporation | Method and apparatus of changing PCB pad structure to increase solder volume and strength |
TWI342608B (en) * | 2008-11-14 | 2011-05-21 | Micro Star Int Co Ltd | Surface mount technology structure for bga |
US20100127407A1 (en) * | 2008-11-25 | 2010-05-27 | Leblanc John | Two-sided substrateless multichip module and method of manufacturing same |
JP4613237B2 (ja) * | 2008-12-10 | 2011-01-12 | 新光電気工業株式会社 | リードピン付配線基板及びリードピン |
WO2012132880A1 (ja) * | 2011-03-25 | 2012-10-04 | 株式会社村田製作所 | セラミック多層基板 |
KR101933015B1 (ko) | 2012-04-19 | 2018-12-27 | 삼성전자주식회사 | 반도체 장치의 패드 구조물, 그의 제조 방법 및 패드 구조물을 포함하는 반도체 패키지 |
US20130299966A1 (en) * | 2012-05-10 | 2013-11-14 | Texas Instruments Incorporated | Wsp die with offset redistribution layer capture pad |
KR101451502B1 (ko) * | 2013-03-05 | 2014-10-15 | 삼성전기주식회사 | 인쇄회로기판 |
US9775231B2 (en) | 2014-11-21 | 2017-09-26 | Amphenol Corporation | Mating backplane for high speed, high density electrical connector |
US20170149155A1 (en) * | 2015-11-25 | 2017-05-25 | Mercury Systems, Inc. | Soldered interconnect for a printed circuit board having an angular radial feature |
US10187972B2 (en) | 2016-03-08 | 2019-01-22 | Amphenol Corporation | Backplane footprint for high speed, high density electrical connectors |
US10201074B2 (en) | 2016-03-08 | 2019-02-05 | Amphenol Corporation | Backplane footprint for high speed, high density electrical connectors |
KR102073294B1 (ko) * | 2016-09-29 | 2020-02-04 | 삼성전자주식회사 | 팬-아웃 반도체 패키지 |
CN112425274A (zh) * | 2018-06-11 | 2021-02-26 | 安费诺有限公司 | 高速、高密度电连接器的底板覆盖区 |
WO2020236794A1 (en) | 2019-05-20 | 2020-11-26 | Amphenol Corporation | High density, high speed electrical connector |
EP4097800A4 (en) | 2020-01-27 | 2024-02-14 | Amphenol Corporation | ELECTRICAL CONNECTOR WITH QUICK MOUNTING INTERFACE |
US11637403B2 (en) | 2020-01-27 | 2023-04-25 | Amphenol Corporation | Electrical connector with high speed mounting interface |
CN113709972A (zh) * | 2021-09-27 | 2021-11-26 | 合肥移瑞通信技术有限公司 | 一种电路板及其制造方法、封装件 |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4518112A (en) * | 1982-12-30 | 1985-05-21 | International Business Machines Corporation | Process for controlled braze joining of electronic packaging elements |
US4970570A (en) * | 1986-10-28 | 1990-11-13 | International Business Machines Corporation | Use of tapered head pin design to improve the stress distribution in the braze joint |
US4927983A (en) | 1988-12-16 | 1990-05-22 | International Business Machines Corporation | Circuit board |
US5097593A (en) | 1988-12-16 | 1992-03-24 | International Business Machines Corporation | Method of forming a hybrid printed circuit board |
US6300688B1 (en) * | 1994-12-07 | 2001-10-09 | Quicklogic Corporation | Bond pad having vias usable with antifuse process technology |
US5875102A (en) | 1995-12-20 | 1999-02-23 | Intel Corporation | Eclipse via in pad structure |
KR100485628B1 (ko) | 1996-01-11 | 2005-09-14 | 이비덴 가부시키가이샤 | 프린트배선판및그의제조방법 |
US6091155A (en) | 1996-02-23 | 2000-07-18 | Silicon Graphics, Inc. | BGA land pattern |
US5764485A (en) | 1996-04-19 | 1998-06-09 | Lebaschi; Ali | Multi-layer PCB blockade-via pad-connection |
US5891606A (en) | 1996-10-07 | 1999-04-06 | Motorola, Inc. | Method for forming a high-density circuit structure with interlayer electrical connections method for forming |
JP3340350B2 (ja) * | 1997-04-18 | 2002-11-05 | 富士通株式会社 | 薄膜多層基板及び電子装置 |
US5994781A (en) * | 1997-05-30 | 1999-11-30 | Tessera, Inc. | Semiconductor chip package with dual layer terminal and lead structure |
US6188028B1 (en) * | 1997-06-09 | 2001-02-13 | Tessera, Inc. | Multilayer structure with interlocking protrusions |
JP3618044B2 (ja) * | 1997-12-26 | 2005-02-09 | 富士通株式会社 | 多層薄膜配線基板 |
US6046909A (en) * | 1998-11-16 | 2000-04-04 | Intel Corporation | Computer card with a printed circuit board with vias providing strength to the printed circuit board |
US6552425B1 (en) * | 1998-12-18 | 2003-04-22 | Intel Corporation | Integrated circuit package |
JP3378550B2 (ja) * | 2000-02-03 | 2003-02-17 | 日本特殊陶業株式会社 | リードピン付き配線基板 |
US6623283B1 (en) * | 2000-03-08 | 2003-09-23 | Autosplice, Inc. | Connector with base having channels to facilitate surface mount solder attachment |
US6660946B2 (en) * | 2000-04-10 | 2003-12-09 | Ngk Spark Plug Co., Ltd. | Pin standing resin-made substrate, method of making pin standing resin-made substrate, pin and method of making pin |
TW507341B (en) * | 2001-11-01 | 2002-10-21 | Siliconware Precision Industries Co Ltd | Substrate capable of preventing delamination of chip and semiconductor encapsulation having such a substrate |
-
2003
- 2003-03-20 US US10/392,617 patent/US7088008B2/en not_active Expired - Fee Related
- 2003-04-28 US US10/423,877 patent/US6815837B2/en not_active Expired - Lifetime
- 2003-04-28 US US10/423,972 patent/US7087846B2/en not_active Expired - Lifetime
-
2004
- 2004-03-16 JP JP2004075099A patent/JP4317471B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US7088008B2 (en) | 2006-08-08 |
US20040183212A1 (en) | 2004-09-23 |
US6815837B2 (en) | 2004-11-09 |
US20040182604A1 (en) | 2004-09-23 |
US7087846B2 (en) | 2006-08-08 |
JP2004289150A (ja) | 2004-10-14 |
US20040183211A1 (en) | 2004-09-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4317471B2 (ja) | 最適回路化パターンを有するチップ・キャリヤ | |
US6756252B2 (en) | Multilayer laser trim interconnect method | |
US20190259733A1 (en) | Semiconductor package | |
US8014154B2 (en) | Circuit substrate for preventing warpage and package using the same | |
US7795743B2 (en) | Wiring substrate having variously sized ball pads, semiconductor package having the wiring substrate, and stack package using the semiconductor package | |
US8058721B2 (en) | Package structure | |
US7615872B2 (en) | Semiconductor device | |
US7952199B2 (en) | Circuit board including solder ball land having hole and semiconductor package having the circuit board | |
US6225687B1 (en) | Chip package with degassing holes | |
US20100327452A1 (en) | Mounting structure and method of manufacturing the same | |
KR100725517B1 (ko) | 본딩 패드와 볼 랜드가 복수 층에 형성된 다층 배선 기판및 이를 이용한 반도체 패키지 구조 | |
US9627224B2 (en) | Semiconductor device with sloped sidewall and related methods | |
US7015585B2 (en) | Packaged integrated circuit having wire bonds and method therefor | |
JP5372235B2 (ja) | 半導体装置および半導体装置実装体 | |
JP2010118592A (ja) | 半導体装置 | |
US20040238970A1 (en) | Electronic pckage with conductive pad capable of withstanding significant loads and information handling system utilizing same | |
EP1473977A2 (en) | Electronic package with strengthened conductive pad | |
US11139228B2 (en) | Semiconductor device | |
US11569155B2 (en) | Substrate bonding pad having a multi-surface trace interface | |
JP7459610B2 (ja) | 電子装置 | |
KR100882516B1 (ko) | 적층형 패키지 및 이의 제조 방법 | |
JP4523425B2 (ja) | 半導体素子搭載用基板 | |
JP2021190526A (ja) | 基板、電子部品、及び電子機器 | |
JP2007227757A (ja) | 半導体素子搭載用基板 | |
KR19980031028U (ko) | 비지에이(bga)형 반도체 패키지 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20070130 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20070426 Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20070426 |
|
RD12 | Notification of acceptance of power of sub attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7432 Effective date: 20070426 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20070427 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20080926 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20081002 |
|
RD14 | Notification of resignation of power of sub attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7434 Effective date: 20081002 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20081121 |
|
RD03 | Notification of appointment of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7423 Effective date: 20090206 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20090512 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20090522 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120529 Year of fee payment: 3 |
|
LAPS | Cancellation because of no payment of annual fees |