JP3765225B2 - Chip-type multiple electronic components - Google Patents

Chip-type multiple electronic components Download PDF

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Publication number
JP3765225B2
JP3765225B2 JP2000178289A JP2000178289A JP3765225B2 JP 3765225 B2 JP3765225 B2 JP 3765225B2 JP 2000178289 A JP2000178289 A JP 2000178289A JP 2000178289 A JP2000178289 A JP 2000178289A JP 3765225 B2 JP3765225 B2 JP 3765225B2
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Prior art keywords
chip
type multiple
multiple electronic
input
external electrode
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JP2001358034A (en
Inventor
宏幸 竹内
直応 大岩
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Murata Manufacturing Co Ltd
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Murata Manufacturing Co Ltd
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Priority to JP2000178289A priority Critical patent/JP3765225B2/en
Priority to TW090114127A priority patent/TW508602B/en
Priority to KR10-2001-0032848A priority patent/KR100418602B1/en
Priority to CNB011187875A priority patent/CN1172337C/en
Publication of JP2001358034A publication Critical patent/JP2001358034A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/40—Structural combinations of fixed capacitors with other electric elements, the structure mainly consisting of a capacitor, e.g. RC combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/228—Terminals
    • H01G4/252—Terminals the terminals being coated on the capacitive element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/30—Stacked capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/38—Multiple capacitors, i.e. structural combinations of fixed capacitors

Description

【０００１】
【発明が属する技術分野】
本発明は、チップ型多連電子部品、特に、セラミック製の素体に複数のコンデンサ、インダクタ、抵抗器等の電気的素子を内蔵したチップ型多連電子部品に関する。
【０００２】
【従来の技術】
従来、図４に示すように、シートを積層してなる素体１に、内部電極を設けて複数のコンデンサ、インダクタ、抵抗器等の電気的素子を構成し（図４では図示しないが、四つの素子が内蔵されている）、素体１の表面に各素子と電気的に接続した外部電極２を一定間隔で形成したチップ型多連電子部品が種々提供されている。
【０００３】
素体１は誘電体、磁性体、非磁性体あるいは絶縁体のセラミックシートを積層したものである。外部電極２は導電ペーストを塗布や転写した後、焼き付けた下地層の上にＣｕ、Ｎｉ、Ｓｎ等を電気メッキしたメッキ層からなる。各電極２の幅寸法ａ，ｂは同じである。
【０００４】
【発明が解決しようとする課題】
ところで、図４に示した従来のチップ型多連電子部品にあっては、外部電極２のメッキ層を形成する際、図５に示すように、下地層を形成した素体１とスチールボール等の導電性メディア３とをメッキ装置（図示せず）に投入、混合し、メディア３を介してメッキする。
【０００５】
しかしながら、メディア３の直径が相対的に大きいため、両端の電極２に対して内側の電極２のほうがメディア３との接触性が悪く、内側の電極２のメッキ厚がどうしても薄くなり、はんだ付き性が悪く、実装不良を招来するという問題点を有していた。特に、近年では、電子回路の小型化に伴って電子部品の小型化も要請され、外部電極２の配置間隔が小さくなる。そこで、電極２の短絡防止のためにメッキ層の成長を抑えるため、メッキ時間や電流密度を抑制し、全体的にメッキ厚が薄くなる傾向にある。このような傾向の下では、内側の電極２のメッキ厚が薄くなる不具合はより顕著である。
【０００６】
そこで、本発明の目的は、外部電極のメッキ厚のばらつきを是正し、特に、内側に配置された外部電極のメッキ厚が薄くなることを防止し、ひいては基板への実装不良を解消できるチップ型多連電子部品を提供することにある。
【０００７】
【課題を解決するための手段及び作用】
以上の目的を達成するため、本発明は、ほぼ矩形形状をなすシートを積層してなる素体と、前記シート上にその短辺方向に延在し、かつ、長辺方向に並置された少なくとも３本の内部電極と、前記内部電極の前記短辺方向の端部に電気的に接続され、かつ、前記素体の長辺方向の側面に配列された入出力用外部電極とを備えたチップ型多連電子部品において、配列方向の両端より内側に位置する入出力用外部電極の幅寸法が、両端に位置する入出力用外部電極の幅寸法よりも大きいことを特徴とする。
【０００８】
本発明に係るチップ型多連電子部品において、入出力用外部電極は下地層にメッキ層を形成してなる。このメッキ層形成時に、内側に位置する入出力用外部電極の幅寸法が両端に位置する入出力用外部電極の幅寸法よりも大きくされているため、内側に位置する入出力用外部電極は導電性メディアとの接触確率が高くなり、両端に位置する入出力用外部電極の接触確率とほぼ同等になる。従って、両端及び内側に位置する入出力用外部電極のメッキ層のばらつきが防止されることになる。
【０００９】
【発明の実施の形態】
以下、本発明に係るチップ型多連電子部品の実施形態について、添付図面を参照して説明する。
【００１０】
図１は、本発明の一実施形態であるチップ型多連コンデンサの外観を示す。また、図２はその分解状態を示す。
【００１１】
図１，２において、チップ型多連コンデンサは、誘電体からなるセラミックシート１１上に所定形状の内部電極１２を形成し、これらのシート１１と上下に同じ素材からなる複数枚の保護用シート１１を重ね合わせ、乾燥、焼結した後、図１，２に示す１単位ごとに切り出されたものである。上下に重なる内部電極１２によって４連のコンデンサアレイが形成される。
【００１２】
シート１１が積層されてなる素体１０の表面には、４対の外部電極１３ａ，１３ｂが各コンデンサ素子に対応して形成される。これらの外部電極１３ａ，１３ｂは、まず、下地層として、Ａｇ、Ａｇ−Ｐｄ、Ｃｕ等の導電性ペーストを塗布あるいは転写した後に焼き付け、その後、周知のバレルメッキ法等でＣｕ、Ｎｉ、Ｓｎ等を電気メッキしてメッキ層を形成する。
【００１３】
本実施形態において特徴的なのは、内側に位置する外部電極１３ｂの幅寸法ｂが両端に位置する外部電極１３ａの幅寸法ａよりも大きく設定されていることである。
【００１４】
通常、バレルメッキ法で使用される導電性メディアの直径は外部電極の間隔よりも大きく、どうしても内側に位置する電極１３ｂへの接触確率が低下するが、本実施形態の如く、内側に位置する電極１３ｂの幅寸法ｂを大きくすることで、両端に位置する電極１３ａとほぼ同等の接触確率まで高めることができる。
【００１５】
従って、本実施形態においては、内側に位置する電極１３ｂのメッキ層の厚みを両端に位置する電極１３ａとほぼ同じに成膜することができ、基板への実装時の接続不良等の不具合が解消される。
【００１６】
因みに、寸法的な一例を示すと、素体１０の大きさは縦２．０ｍｍ、横１．０ｍｍ、高さ０．５ｍｍ、外部電極１３ａの幅寸法ａは０．２３ｍｍ、外部電極１３ｂの幅寸法ｂは０．２５ｍｍであり、電極間隔は０．５ｍｍである。また、バレルメッキ法で使用されるメディアの直径は０．８ｍｍである。
【００１７】
一方、図３に示すように、チップ型多連電子部品が実装される基板２０には、両端の電極１３ａに対応するランド２１ａが内側の電極１３ｂに対応するランド２１ｂよりも大きく形成されたものがある。このような基板２０を使用する場合、ランド２１ｂはランド２１ａに比べてはんだ量が少なくなる。しかし、本実施形態においては、ランド２１ｂに対応する外部電極１３ｂの幅寸法が大きく設定されているため、はんだ量が少ないランド２１ｂとのはんだ付き性を確保することができる。
【００１８】
（他の実施形態）
なお、本発明に係るチップ型多連電子部品は前記実施形態に限定するものではなく、その要旨の範囲内で種々に変更することができる。
【００１９】
特に、電気的素子としては、前記コンデンサ以外にインダクタや抵抗器等種々の素子であってもよく、セラミックシートの材質も素子の種類に応じて、誘電体以外に磁性体、絶縁体等種々のものが使用される。また、外部電極に関しても前記実施形態で説明した以外の材料、方法によることができ、３層構造であってもよい。
【００２０】
【発明の効果】
以上の説明から明らかなように、本発明によれば、両端以外の内側に位置する入出力用外部電極の幅寸法を大きくしたため、該電極のメッキ層が薄くなることを防止し、両端に位置する入出力用外部電極のメッキ層とほぼ同等の厚みを得ることができ、ひいては基板への実装不良等の不具合を解消することができる。さらに、面積の小さいランドに対しても十分なはんだ付き性を確保することができる。
【図面の簡単な説明】
【図１】本発明の一実施形態であるチップ型多連コンデンサの外観を示す斜視図。
【図２】前記コンデンサのシートを分解した状態の斜視図。
【図３】前記コンデンサが実装される基板のランドを示す平面図。
【図４】従来のチップ型多連電子部品の外観を示す斜視図。
【図５】前記電子部品とメッキ時に使用されるメディアとの関係を示す説明図。
【符号の説明】
１０…セラミック製素体
１１…セラミックシート
１２…内部電極
１３ａ，１３ｂ…外部電極
ａ，ｂ…電極幅寸法[0001]
[Technical field to which the invention belongs]
The present invention relates to a chip-type multiple electronic component, and more particularly to a chip-type multiple electronic component in which electrical elements such as a plurality of capacitors, inductors and resistors are built in a ceramic body.
[0002]
[Prior art]
Conventionally, as shown in FIG. 4, an internal electrode is provided on an element body 1 formed by laminating sheets to constitute a plurality of electrical elements such as capacitors, inductors, resistors (not shown in FIG. 4, There are various chip-type multiple electronic components in which external electrodes 2 electrically connected to the respective elements are formed on the surface of the element body 1 at regular intervals.
[0003]
The element body 1 is a laminate of ceramic sheets of dielectric, magnetic, non-magnetic or insulating materials. The external electrode 2 is composed of a plating layer obtained by electroplating Cu, Ni, Sn or the like on the baked underlayer after applying or transferring a conductive paste. The width dimensions a and b of each electrode 2 are the same.
[0004]
[Problems to be solved by the invention]
By the way, in the conventional chip-type multiple electronic component shown in FIG. 4, when the plating layer of the external electrode 2 is formed, as shown in FIG. The conductive medium 3 is put into a plating apparatus (not shown), mixed, and plated through the medium 3.
[0005]
However, since the diameter of the medium 3 is relatively large, the inner electrode 2 has poor contact with the medium 3 with respect to the electrodes 2 at both ends, and the plating thickness of the inner electrode 2 is inevitably reduced, so that the solderability is improved. However, it has a problem of causing poor mounting. In particular, in recent years, with the miniaturization of electronic circuits, there has been a demand for miniaturization of electronic components, and the arrangement interval of the external electrodes 2 is reduced. Therefore, in order to suppress the growth of the plating layer in order to prevent the short circuit of the electrode 2, the plating time and the current density are suppressed, and the plating thickness tends to be reduced as a whole. Under such a tendency, the problem that the plating thickness of the inner electrode 2 becomes thin is more remarkable.
[0006]
Therefore, an object of the present invention is to correct the variation in the plating thickness of the external electrode, in particular, to prevent the plating thickness of the external electrode disposed on the inner side from becoming thin, and thus to eliminate the defective mounting on the substrate. It is to provide multiple electronic components.
[0007]
[Means and Actions for Solving the Problems]
In order to achieve the above object, the present invention provides an element body formed by laminating sheets having a substantially rectangular shape , and extends at least on the sheet in the short side direction and juxtaposed in the long side direction. A chip comprising three internal electrodes and input / output external electrodes electrically connected to the ends of the internal electrodes in the short side direction and arranged on the side surfaces in the long side direction of the element body The type multiple electronic component is characterized in that the width dimension of the input / output external electrodes positioned inside both ends in the arrangement direction is larger than the width dimension of the input / output external electrodes positioned at both ends.
[0008]
In the chip-type multiple electronic component according to the present invention, the input / output external electrodes are formed by forming a plating layer on the base layer. During this plating layer formation, since it is larger than the width of the input and output external electrode width of the input and output external electrode located inside at both ends, the input-output external electrodes positioned inside the conductive The contact probability with the sexual media is increased, and the contact probability between the input / output external electrodes located at both ends is almost equal. Accordingly, variations in the plating layer of the input / output external electrodes located at both ends and inside are prevented.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of a chip-type multiple electronic component according to the present invention will be described below with reference to the accompanying drawings.
[0010]
FIG. 1 shows the appearance of a chip-type multiple capacitor according to an embodiment of the present invention. FIG. 2 shows the disassembled state.
[0011]
1 and 2, a chip-type multiple capacitor includes a plurality of protective sheets 11 made of the same material as the upper and lower sides of an internal electrode 12 having a predetermined shape formed on a dielectric ceramic sheet 11. After being stacked, dried, and sintered, each unit shown in FIGS. A quadruple capacitor array is formed by the internal electrodes 12 that overlap vertically.
[0012]
Four pairs of external electrodes 13a and 13b are formed on the surface of the element body 10 on which the sheets 11 are laminated, corresponding to each capacitor element. These external electrodes 13a, 13b are first baked after applying or transferring a conductive paste such as Ag, Ag-Pd, Cu or the like as a base layer, and thereafter, Cu, Ni, Sn, etc. by a known barrel plating method or the like. Is electroplated to form a plating layer.
[0013]
What is characteristic in the present embodiment is that the width dimension b of the external electrode 13b located inside is set larger than the width dimension a of the external electrode 13a located at both ends.
[0014]
Normally, the diameter of the conductive medium used in the barrel plating method is larger than the interval between the external electrodes, and the probability of contact with the inner electrode 13b is inevitably lowered. However, as in this embodiment, the inner electrode is used. By increasing the width dimension b of 13b, it is possible to increase the contact probability substantially equal to that of the electrodes 13a located at both ends.
[0015]
Therefore, in this embodiment, the thickness of the plating layer of the electrode 13b located on the inner side can be formed to be almost the same as that of the electrode 13a located on both ends, and problems such as poor connection when mounted on the substrate are eliminated. Is done.
[0016]
For example, the dimension of the element body 10 is 2.0 mm in length, 1.0 mm in width, 0.5 mm in height, the width dimension a of the external electrode 13a is 0.23 mm, and the width of the external electrode 13b. The dimension b is 0.25 mm, and the electrode interval is 0.5 mm. The diameter of the media used in the barrel plating method is 0.8 mm.
[0017]
On the other hand, as shown in FIG. 3, on the substrate 20 on which the chip-type multiple electronic components are mounted, the lands 21a corresponding to the electrodes 13a at both ends are formed larger than the lands 21b corresponding to the inner electrodes 13b. There is. When such a substrate 20 is used, the land 21b has a smaller amount of solder than the land 21a. However, in the present embodiment, since the width dimension of the external electrode 13b corresponding to the land 21b is set large, it is possible to ensure solderability with the land 21b with a small amount of solder.
[0018]
(Other embodiments)
Note that the chip-type multiple electronic component according to the present invention is not limited to the above-described embodiment, and can be variously modified within the scope of the gist thereof.
[0019]
In particular, the electric element may be various elements such as an inductor and a resistor in addition to the capacitor, and the material of the ceramic sheet may vary depending on the type of the element, such as a magnetic material, an insulator, and the like. Things are used. Further, the external electrodes can be made of materials and methods other than those described in the above embodiment, and may have a three-layer structure.
[0020]
【The invention's effect】
As is clear from the above description, according to the present invention, the width of the input / output external electrode located inside other than both ends is increased, so that the plating layer of the electrode is prevented from being thinned, Therefore, it is possible to obtain a thickness substantially equal to the plated layer of the input / output external electrode, and to eliminate problems such as mounting defects on the substrate. Furthermore, sufficient solderability can be ensured even for lands having a small area.
[Brief description of the drawings]
FIG. 1 is a perspective view showing an external appearance of a chip-type multiple capacitor according to an embodiment of the present invention.
FIG. 2 is a perspective view of the capacitor sheet in an exploded state.
FIG. 3 is a plan view showing a land of a substrate on which the capacitor is mounted.
FIG. 4 is a perspective view showing an appearance of a conventional chip-type multiple electronic component.
FIG. 5 is an explanatory diagram showing a relationship between the electronic component and a medium used during plating.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Ceramic body 11 ... Ceramic sheet 12 ... Internal electrode 13a, 13b ... External electrode a, b ... Electrode width dimension

Claims (2)

ほぼ矩形形状をなすシートを積層してなる素体と、前記シート上にその短辺方向に延在し、かつ、長辺方向に並置された少なくとも３本の内部電極と、前記内部電極の前記短辺方向の端部に電気的に接続され、かつ、前記素体の長辺方向の側面に配列された入出力用外部電極とを備えたチップ型多連電子部品において、
配列方向の両端より内側に位置する入出力用外部電極の幅寸法が、両端に位置する入出力用外部電極の幅寸法よりも大きいこと、
を特徴とするチップ型多連電子部品。 An element body formed by laminating sheets having a substantially rectangular shape, at least three internal electrodes extending in the short-side direction on the sheet and juxtaposed in the long-side direction, and the internal electrodes In a chip-type multiple electronic component comprising an input / output external electrode electrically connected to an end portion in the short side direction and arranged on a side surface in the long side direction of the element body,
The width dimension of the input / output external electrode located inside both ends in the arrangement direction is larger than the width dimension of the input / output external electrode positioned at both ends,
Chip-type multiple electronic components characterized by 前記入出力用外部電極は、前記素体の表面に形成された導電性ペーストを焼き付けてなる下地層と、該下地層上に電気メッキされたメッキ層とで構成されていることを特徴とする請求項１記載のチップ型多連電子部品。The input / output external electrode includes a base layer formed by baking a conductive paste formed on the surface of the element body, and a plating layer electroplated on the base layer. The chip-type multiple electronic component according to claim 1.
JP2000178289A 2000-06-14 2000-06-14 Chip-type multiple electronic components Expired - Lifetime JP3765225B2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2000178289A JP3765225B2 (en) 2000-06-14 2000-06-14 Chip-type multiple electronic components
TW090114127A TW508602B (en) 2000-06-14 2001-06-12 Chip-type multi-connection electric device
KR10-2001-0032848A KR100418602B1 (en) 2000-06-14 2001-06-12 Chip type array electronic component
CNB011187875A CN1172337C (en) 2000-06-14 2001-06-13 Chip type multiple linking electronic device

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Application Number Priority Date Filing Date Title
JP2000178289A JP3765225B2 (en) 2000-06-14 2000-06-14 Chip-type multiple electronic components

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JP2001358034A JP2001358034A (en) 2001-12-26
JP3765225B2 true JP3765225B2 (en) 2006-04-12

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JP4091054B2 (en) * 2004-07-20 2008-05-28 三星電機株式会社 Multilayer ceramic capacitor
JP4276649B2 (en) * 2005-09-27 2009-06-10 Ｔｄｋ株式会社 Feedthrough multilayer capacitor array and mounting structure of feedthrough multilayer capacitor array
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