JP3737504B2 - 半導体装置の製造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims description 95
- 238000004519 manufacturing process Methods 0.000 title claims description 50
- 239000012535 impurity Substances 0.000 claims description 86
- 238000000034 method Methods 0.000 claims description 62
- 238000010438 heat treatment Methods 0.000 claims description 56
- 239000013078 crystal Substances 0.000 claims description 54
- 238000001994 activation Methods 0.000 claims description 33
- 150000002500 ions Chemical class 0.000 claims description 29
- 230000015572 biosynthetic process Effects 0.000 claims description 20
- 230000003213 activating effect Effects 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 56
- 229910052710 silicon Inorganic materials 0.000 description 56
- 239000010703 silicon Substances 0.000 description 56
- 239000000758 substrate Substances 0.000 description 54
- 230000007547 defect Effects 0.000 description 47
- 125000001475 halogen functional group Chemical group 0.000 description 25
- 230000004913 activation Effects 0.000 description 23
- 230000000694 effects Effects 0.000 description 20
- 238000005468 ion implantation Methods 0.000 description 17
- 238000000348 solid-phase epitaxy Methods 0.000 description 17
- 238000002513 implantation Methods 0.000 description 13
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 10
- 229910052796 boron Inorganic materials 0.000 description 10
- 229910052732 germanium Inorganic materials 0.000 description 7
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 7
- 238000000137 annealing Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 4
- 238000011084 recovery Methods 0.000 description 4
- 229910052785 arsenic Inorganic materials 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000005465 channeling Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000005224 laser annealing Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- -1 Arsenic ions Chemical class 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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Description
ジョン・O・ボーランド(John O. Borland)、Low Temperature Activation of Ion Implanted Dopants、Extended Abstracts of International Workshop on Junction Technology 2002、応用物理学会(Japan Society of Applied Physics)、2002年12月、p.85-88
第4の半導体装置の製造方法によると、浅いpn接合を有する不純物層を備えたMOSFET等を形成する際、第1の製造方法と同様に接合リーク電流を低減することができる。また、アモルファス層に対する熱処理及び第1の不純物層に対する活性化処理の際に比較的長時間である数分間の熱処理を行なうと、アモルファス層の結晶構造回復及び不純物層活性化のそれぞれの工程において、パターン依存性の発生を防止することができる。
以下、本発明の第1の実施形態に係る半導体装置の製造方法について、図面を参照しながら説明する。
以下、本発明の第2の実施形態に係る半導体装置の製造方法について、図面を参照しながら説明する。
以下、本発明の第3の実施形態に係る半導体装置の製造方法について、図面を参照しながら説明する。
101 アモルファス層
102 アモルファス・結晶界面
103 欠陥
104 pn接合
106 ゲート絶縁膜
107 ゲート電極
108 ドレインエクステンション
109 ハロー領域
110 サイドウォール
111 コンタクトドレイン
A 第1の深さ
B 第2の深さ
C 第3の深さ
Claims (12)
- 半導体領域におけるその表面から第1の深さまでの領域にアモルファス層を形成する工程と、
前記アモルファス層に対して所定の温度において熱処理を行なうことにより、前記アモルファス層のうち、前記第1の深さから前記第1の深さよりも浅い第2の深さまでの領域について結晶構造を回復させ、それによって前記アモルファス層を前記第2の深さまで後退させる工程と、
前記熱処理が行なわれた前記アモルファス層にイオンを導入することにより、前記第2の深さよりも浅い第3の深さにpn接合を形成する工程とを備えていることを特徴とする半導体装置の製造方法。 - 前記所定の温度は、475℃以上で且つ600℃以下であることを特徴とする請求項1に記載の半導体装置の製造方法。
- 第1導電型の半導体領域におけるその表面から第1の深さまでの領域にアモルファス層を形成する工程と、
前記アモルファス層に対して所定の温度において熱処理を行なうことにより、前記アモルファス層のうち、前記第1の深さから前記第1の深さよりも浅い第2の深さまでの領域について結晶構造を回復させ、それによって前記アモルファス層を前記第2の深さまで後退させる工程と、
前記熱処理が行なわれた前記アモルファス層にイオンを導入することにより、前記第2の深さよりも浅い第3の深さにpn接合を有する第2導電型の第1の不純物層を形成する工程と、
前記第1の不純物層に対して活性化処理を行なう工程とを備えていることを特徴とする半導体装置の製造方法。 - 第1導電型の半導体領域上にゲート電極を形成する工程と、
前記第1導電型の半導体領域におけるその表面から第1の深さまでの領域にアモルファス層を形成する工程と、
前記アモルファス層に対して所定の温度において熱処理を行なうことにより、前記アモルファス層のうち、前記第1の深さから前記第1の深さよりも浅い第2の深さまでの領域について結晶構造を回復させ、それによって前記アモルファス層を前記第2の深さまで後退させる工程と、
前記熱処理が行なわれた前記アモルファス層にイオンを導入することにより、前記第2の深さよりも浅い第3の深さにpn接合を有する第2導電型の第1の不純物層を形成する工程と、
前記熱処理が行なわれた前記アモルファス層にイオンを導入することにより、前記第1の深さよりも浅く且つ前記第3の深さよりも深い位置にpn接合を有する第1導電型の第2の不純物層を形成する工程と、
前記第1の不純物層及び前記第2の不純物層に対して活性化処理を行なう工程とを備えていることを特徴とする半導体装置の製造方法。 - 前記第3の深さは5nm以上で且つ15nm以下である請求項1〜4のいずれか1つに記載の半導体装置の製造方法。
- 前記所定の温度は、475℃以上で且つ600℃以下であると共に、
前記第1の不純物層又は前記第1の不純物層と前記第2の不純物層との活性化処理は、500℃以上で且つ700℃以下の温度範囲で行なうことを特徴とする請求項3〜5のいずれか1つに記載の半導体装置の製造方法。 - 前記半導体領域上に形成されるゲート電極のパターンは前記半導体領域上で不均一に分布していることを特徴とする請求項3〜6のいずれか1つに記載の半導体装置の製造方法。
- 第1導電型の半導体領域上にゲート電極を形成する工程と、
前記半導体領域におけるその表面から第1の深さまでの領域にアモルファス層を形成する工程と、
前記ゲート電極の側面に絶縁性のサイドウォールを形成すると同時に、前記サイドウォール形成の際に行なわれる所定の温度の熱処理によって、前記アモルファス層のうち、前記第1の深さから前記第1の深さよりも浅い第2の深さまでの領域について結晶構造を回復させ、それによって前記アモルファス層を前記第2の深さまで後退させる工程と、
前記熱処理が行なわれた前記アモルファス層における前記ゲート電極両側の領域にイオンを導入することにより、前記第2の深さよりも浅い第3の深さにpn接合を有し且つ第2導電型である第1の不純物層を形成する工程と、
前記第1の不純物層の活性化処理を行なう工程とを備えていることを特徴とする半導体装置の製造方法。 - 前記第1の不純物層を形成する工程よりも後に、前記アモルファス層における前記ゲート電極両側の領域にイオンを導入することにより、前記第1の深さよりも浅く且つ前記第3の深さよりも深い位置にpn接合を有する第1導電型の第2の不純物層を形成する工程を更に備え、
前記第1の不純物層の活性化処理を行なう工程において、前記第2の不純物層の活性化処理を同時に行なうことを特徴とする請求項8に記載の半導体装置の製造方法。 - 前記第1の不純物層の深さは5nm以上で且つ15nm以下である請求項8又は9に記載の半導体装置の製造方法。
- 前記所定の温度は、475℃以上で且つ600℃以下であり、
前記活性化処理は、500℃以上で且つ700℃以下の温度範囲で行なわれることを特徴とする請求項8〜10のいずれか1つに記載の半導体装置の製造方法。 - 前記半導体領域上に形成されるゲート電極のパターンは前記半導体領域上で不均一に分布していることを特徴とする請求項8〜11のいずれか1つに記載の半導体装置の製造方法。
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JP2004103681A JP3737504B2 (ja) | 2004-03-31 | 2004-03-31 | 半導体装置の製造方法 |
US10/557,746 US7737012B2 (en) | 2004-03-31 | 2005-03-29 | Manufacturing method of a semiconductor device |
EP05727888A EP1732112A4 (en) | 2004-03-31 | 2005-03-29 | METHOD FOR PRODUCING A SEMICONDUCTOR COMPONENT |
PCT/JP2005/005947 WO2005096357A1 (ja) | 2004-03-31 | 2005-03-29 | 半導体装置の製造方法 |
KR1020057022315A KR20060136300A (ko) | 2004-03-31 | 2005-03-29 | 반도체장치의 제조방법 |
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US8421130B2 (en) * | 2007-04-04 | 2013-04-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for manufacturing SRAM devices with reduced threshold voltage deviation |
JP5303881B2 (ja) | 2007-08-15 | 2013-10-02 | 富士通セミコンダクター株式会社 | 電界効果トランジスタ及び電界効果トランジスタの製造方法 |
CN102194868B (zh) * | 2010-03-16 | 2013-08-07 | 北京大学 | 一种抗辐照的Halo结构MOS器件 |
JP2013026345A (ja) * | 2011-07-19 | 2013-02-04 | Toshiba Corp | 半導体装置の製造方法 |
US8884341B2 (en) | 2011-08-16 | 2014-11-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuits |
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CN1286157C (zh) * | 2002-10-10 | 2006-11-22 | 松下电器产业株式会社 | 半导体装置及其制造方法 |
US6936505B2 (en) * | 2003-05-20 | 2005-08-30 | Intel Corporation | Method of forming a shallow junction |
US7071069B2 (en) * | 2003-12-22 | 2006-07-04 | Chartered Semiconductor Manufacturing, Ltd | Shallow amorphizing implant for gettering of deep secondary end of range defects |
US7094671B2 (en) * | 2004-03-22 | 2006-08-22 | Infineon Technologies Ag | Transistor with shallow germanium implantation region in channel |
US7091097B1 (en) * | 2004-09-03 | 2006-08-15 | Advanced Micro Devices, Inc. | End-of-range defect minimization in semiconductor device |
US7247547B2 (en) * | 2005-01-05 | 2007-07-24 | International Business Machines Corporation | Method of fabricating a field effect transistor having improved junctions |
-
2004
- 2004-03-31 JP JP2004103681A patent/JP3737504B2/ja not_active Expired - Fee Related
-
2005
- 2005-03-29 EP EP05727888A patent/EP1732112A4/en not_active Withdrawn
- 2005-03-29 WO PCT/JP2005/005947 patent/WO2005096357A1/ja not_active Application Discontinuation
- 2005-03-29 US US10/557,746 patent/US7737012B2/en active Active
- 2005-03-29 CN CNB2005800003028A patent/CN100401476C/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
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KR20070000330A (ko) | 2007-01-02 |
EP1732112A4 (en) | 2008-10-01 |
WO2005096357A1 (ja) | 2005-10-13 |
EP1732112A1 (en) | 2006-12-13 |
CN100401476C (zh) | 2008-07-09 |
JP2005294341A (ja) | 2005-10-20 |
US20070054444A1 (en) | 2007-03-08 |
US7737012B2 (en) | 2010-06-15 |
CN1774795A (zh) | 2006-05-17 |
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