JP3632564B2 - Semiconductor wafer manufacturing method and plasma CVD apparatus - Google Patents

Semiconductor wafer manufacturing method and plasma CVD apparatus Download PDF

Info

Publication number
JP3632564B2
JP3632564B2 JP2000145338A JP2000145338A JP3632564B2 JP 3632564 B2 JP3632564 B2 JP 3632564B2 JP 2000145338 A JP2000145338 A JP 2000145338A JP 2000145338 A JP2000145338 A JP 2000145338A JP 3632564 B2 JP3632564 B2 JP 3632564B2
Authority
JP
Japan
Prior art keywords
plasma
semiconductor wafer
chamber
sealing region
cvd apparatus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2000145338A
Other languages
Japanese (ja)
Other versions
JP2001326184A (en
Inventor
勇 南百瀬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP2000145338A priority Critical patent/JP3632564B2/en
Publication of JP2001326184A publication Critical patent/JP2001326184A/en
Application granted granted Critical
Publication of JP3632564B2 publication Critical patent/JP3632564B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Landscapes

  • Chemical Vapour Deposition (AREA)

Description

【0001】
【発明の属する技術分野】
本発明は、半導体ウェハの製造方法およびプラズマCVD装置に係り、特に半導体ウェハへの成膜と、この成膜工程によって生じる生成物の除去を効率的に行うようにした半導体ウェハの製造方法およびプラズマCVD装置に関する。
【0002】
【従来の技術】
半導体装置は、円盤状のシリコン基板(以下半導体ウェハと称す)の表面に不純物を打ち込み、その表面にトランジスタや抵抗および容量などを形成した後、さらにその表面に絶縁膜や配線を形成していくことで製造される。
【0003】
ところで半導体ウェハの表面に絶縁膜を形成したり、あるいは配線の基となるポリシリコンを堆積したりする方法としてCVD法(化学気相堆積法:Chemical Vapor Deposition 法)が知られており、中でもエネルギ源としてプラズマ放電を利用したプラズマCVD法が広く用いられている。
【0004】
図4は、従来のプラスマCVD装置を用いた成膜工程を示す説明図である。同図(1)に示すように前記プラズマCVD法を実施するためのプラズマCVD装置1は、処理対象となる半導体ウェハ2を投入可能にするチャンバ3と、このチャンバ3の内部に設けられたプラズマ発生装置4とで構成される。なお当該プラズマ発生装置4は、一対の平板電極5と、これら平板電極5の間に高周波電圧を印加可能な電源装置6とで構成され、平板電極5の間にプラズマ放電を発生させるようにしている。
【0005】
このように構成されたプラズマCVD装置1では、まずチャンバ3内に半導体ウェハ2を投入し、当該半導体ウェハ2をプラズマ発生装置4を構成する平板電極5の間に設置する。そしてチャンバ3内に半導体ウェハ2の表面に成膜したい構成元素を有した気体(以下、反応ガスと称す)7を導入させるとともに、プラズマ発生装置4を稼働させ平板電極5の間にプラズマを発生させ、半導体ウェハ2の表面への成膜を行う。
【0006】
なお半導体ウェハ2への成膜が終了した後は、同図(2)に示すようにチャンバ3の内壁にも反応ガスのプラズマ化により生成物8が付着している。そしてこの生成物8は、次回以降の成膜工程の際、チャンバ3の壁面より剥がれ半導体ウェハ2の表面に堆積し障害となるおそれがあるので、1乃至2回の成膜工程の後、チャンバ3内にPFC(パーフルオロカーボンおよびそのフッ素の一部が水素に代替された化合物(HFC))9を導入し、これをプラズマ化し生成物8の除去を行うようにしている。
【0007】
【発明が解決しようとする課題】
しかし前述したプラズマCVD装置では、以下に示すような問題があった。
【0008】
すなわち前述のとおりプラズマCVD装置では(半導体ウェハの表面だけに成膜を行いたいのであるが)プラズマが発生する領域(以下、プラズマ発生領域と称す)はチャンバの内壁まで達し、このため次回以降の成膜工程に障害となる生成物がチャンバの内壁に付着してしまう。そしてチャンバに付着した生成物を除去するために成膜工程後、清掃工程としてPFCを導入するようにしているが当該PFCは、GWP(地球温暖化係数)が二酸化炭素に対して数千〜数万倍と高い。このためチャンバの内壁に付着した生成物を除去するのに前記PFCを大量に使用するということは環境上好ましいものではなかった。
【0009】
本発明は上記従来の問題点に着目し、成膜工程にて生じた生成物の除去を行うPFCの使用量を低減させるとともに、その清掃時間の短縮を図るようにした半導体ウェハの製造方法およびプラズマCVD装置を提供することを目的とする。
【0010】
【課題を解決するための手段】
本発明は、半導体ウェハを取り囲むプラズマ発生領域をチャンバ内で縮小させれば、当該チャンバ内に生成物を付着させることが防止でき前記生成物の拡散防止が図れるので、清掃工程に用いるPFCの使用量の低減と清掃時間の短縮を図れるという知見に基づいてなされたものである。
【0011】
すなわち請求項1に記載の半導体ウェハの製造方法は、半導体ウェハが装着されたチャンバに反応ガスを導入するとともに前記半導体ウェハを内包する複数の環状部材の間隔を狭め当該環状部材の内側に形成されたプラズマ封止領域内でプラズマ化した前記反応ガスにより前記半導体ウェハの成膜をなす成膜工程と、
半導体ウェハを取り除いた前記チャンバにPFCを導入させるとともに前記環状部材の間隔を前記成膜工程時よりも拡開させ前記プラズマ封止領域を拡大し前記成膜工程にて前記環状部材に付着した生成物をプラズマ化した前記PFCにて除去する清掃工程とを有することを特徴としている。請求項1に係る半導体ウェハの製造方法によれば、成膜工程時、一定の間隔をおいて環状部材を積層させその中央部に半導体ウェハを設置しておく。そして環状部材に内包された領域をプラズマ封止領域として設定すれば、チャンバ内に導入された反応ガスは、環状部材の隙間からプラズマ封止領域に進入し、当該プラズマ封止領域でプラズマ化がなされ半導体ウェハへの成膜を行う。そしてプラズマ処理を行った反応ガスは、再び隙間よりプラズマ封止領域外へと抜け出す。ところでプラスマとは原子の中にいる電子が電子殻から飛び出し、これら電子や原子が高速で運動している状態である(全体としてほぼ電気的に中性である)。このため複数の環状部材を一定の間隔に保つようにしておけば(隙間が形成されるよう環状部材を配置しておけば)、高速で移動する電子や原子がプラズマ封止領域の外部に飛び出ようとすると、電子や原子は隙間を形成する環状部材に衝突し、そのエネルギが失われることとなりプラズマが消滅する。故にプラズマがプラズマ封止領域を構成する環状部材を超えて拡散することを防止することができ、プラズマ封止領域の外部に位置するチャンバ内壁に反応による生成物が付着するのを防止することができる。なおプラズマ反応はプラズマ封止領域内で集中して行われるため半導体ウェハにおける成膜速度を向上させることも可能になる。
【0012】
なお清掃工程においては、チャンバの内壁に清掃を行う必要がなく、プラズマ封止領域についてのみ生成物の除去を行うようにすればよい。ここで環状部材の間隔を成膜工程時より広げるようにすれば、PFCのプラズマ粒子は、環状部材の間隔が広がった分だけ外方まで到達するので成膜工程時に対し遠方までエネルギが保たれることとなり、プラズマ封止領域が成膜工程時よりも拡大する。このため成膜工程時に環状部材に付着した生成物を確実に除去することができる。また生成物の付着はプラズマ封止領域だけで生じるので、生成物の除去に用いるPFCの使用量の低減を図ることができるとともに、生成物を除去する時間すなわち清掃時間の短縮を図ることができることはいうまでもない。
【0013】
そして半導体ウェハを内包する複数の環状部材の形状は、円形に限定されるものでは無くCVD対象物の形状に合わせて、平面四角形状に代表されるように様々な形状を適用させることが可能である。
【0014】
請求項2に記載のプラズマCVD装置は、反応ガスとPFCとを導入可能とするチャンバを設けるとともに当該チャンバ内にプラズマ発生手段を設け、前記チャンバ内に設置される半導体ウェハへの成膜をなすプラズマCVD装置であって、前記チャンバ内に前記半導体ウェハを内包可能な環状部材を設けこれをプラズマ封止領域とするとともに前記環状部材に間隔調整部を設け、前記プラズマ封止領域内に導入された前記反応ガスをプラズマ化し前記半導体ウェハへの成膜をなした後に、前記プラズマ封止領域内に導入された前記PFCをプラズマ化し前記プラズマ封止領域に付着した生成物を除去可能にしたことを特徴としている。請求項2に係るプラズマCVD装置によれば、成膜工程時、隙間間隔調整部を稼働させ、一定の間隔をおいて積層された環状部材に内包された領域をプラズマ封止領域として構成しておけば、チャンバ内に導入された反応ガスは、環状部材の隙間からプラズマ封止領域に進入し、当該プラズマ封止領域でプラズマ化がなされ半導体ウェハへの成膜を行う。そしてプラズマ処理を行った反応ガスは、再び隙間よりプラズマ封止領域外へと抜け出す。ところでプラスマとは原子の中にいる電子が電子殻から飛び出し、これら電子や原子が高速で運動している状態である(全体としてほぼ電気的に中性である)。このため複数の環状部材を一定の間隔に保つようにしておけば(隙間が形成されるよう環状部材を配置しておけば)、高速で移動する電子や原子がプラズマ封止領域の外部に飛び出ようとすると、電子や原子は隙間を形成する環状部材に衝突し、そのエネルギが失われることとなりプラズマが消滅する。故にプラズマがプラズマ封止領域を構成する環状部材を超えて拡散することを防止することができ、プラズマ封止領域の外部に位置するチャンバ内壁に反応による生成物が付着するのを防止することができる。なおプラズマ反応はプラズマ封止領域内で集中して行われるため半導体ウェハにおける成膜速度を向上させることも可能になる。
【0015】
なお清掃工程においては、チャンバの内壁に清掃を行う必要がなく、プラズマ封止領域についてのみ生成物の除去を行うようにすればよい。ここで隙間間隔調整部を再度稼働させ、環状部材の間隔を成膜工程時より広げるようにすれば、環状部材の間隔が広がった分だけ外方まで到達するので成膜工程時に対し遠方までエネルギが保たれることとなり、プラズマ封止領域が成膜工程時よりも拡大する。このため成膜工程時に環状部材に付着した生成物を確実に除去することができる。また生成物の付着はプラズマ封止領域だけで生じるので、生成物の除去に用いるPFCの使用量の低減を図ることができるとともに、生成物を除去する時間すなわち清掃時間の短縮を図ることができることはいうまでもない。
【0016】
請求項3に記載のプラズマCVD装置は、前記環状部材は、螺旋状のバネ部材からなることを特徴としている。請求項3に係るプラズマCVD装置によれば、隙間間隔調整部を昇降機構とし螺旋状のバネ部材の端部に配置すれば、前記昇降機構を上下させることで前記バネ部材が伸縮し、当該バネ部材の側面に形成される隙間の間隔を調整することができる。このため複雑な機構を設けずとも隙間間隔の調整を行うことができる。
【0017】
【発明の実施の形態】
以下に本発明に係る半導体ウェハの製造方法およびプラズマCVD装置に好適な具体的実施の形態を図面を参照した詳細に説明する。
【0018】
図1は、本実施の形態に係るプラズマCVD装置の構成を示す説明図であり、図2は、プラズマCVD装置の内部構造を示した部品展開図である。
【0019】
これらの図に示すように、本実施の形態に係るプラズマCVD装置10では、処理対象となる半導体ウェハ12を取り込み可能なチャンバ14が設けられており、このチャンバ14には配管16を介して半導体ウェハ12の表面に成膜したい構成元素を有した気体(以下、反応ガスと称す)が充填された第1ガスボンベ18と、配管20を介してPFCが充填された第2ガスボンベ22が取り付けられている。なお前述した配管16および配管20にはその途中に開閉バルブ24、開閉バルブ26が取り付けられており、これら開閉バルブの開閉動作によりチャンバ14内に任意のガスを導入可能にしている。
【0020】
一方、チャンバ14の後段側からも配管28が引き出され、その配管途中には真空ポンプ30が設けられている。そして前記真空ポンプ30を稼働させることでチャンバ14への吸引をなし、当該チャンバ14内を任意の減圧状態にすることができる。また真空ポンプ30の吸引動作により、第1カスボンベ18や第2ガスボンベ22から送り込まれたガスを後段側へと送り出し、チャンバ14内をガスが通過できるようにしている。
【0021】
チャンバ14の内部には、プラズマ発生装置32が設けられている。当該プラズマ発生装置32は、チャンバ14内の上下に設けられた一対の平板電極34と、これら平板電極34の間に高周波電圧を印加可能な電源装置36とで構成され、平板電極34の間にプラズマ放電を発生させるようにしている。
【0022】
なお設置電位側となる平板電極34(図中下側の平板電極34)の上面には、半導体ウェハ12を搭載するためのステージ38が取り付けられている。ここでステージ38には、その表面からボスを突出させステージ38と半導体ウェハ12との間に隙間を形成させる持上機構と、半導体ウェハ12をステージ38の表面に密着させるための吸引機構とが設けられている。さらに図示しないがチャンバ14の外部にはステージ38上に伸張を可能とする把持アームが設けられており、前記持上機構によって形成されたステージ38と半導体ウェハ12との隙間に把持アームを挿入し、半導体ウェハ12の取り込み/取り出しを行えるようにしている。
【0023】
ところで設置電位側となる平板電極34(図中下側の平板電極34)の周囲4箇所には、チャンバ14の天井方向に伸張をなすシリンダ装置40が設けられており、チャンバ14の天井42からは前記シリンダ装置40のロッド44に軸心を一致させるようアンカーガイド46が設けられている。なおシリンダ装置40においては、後述する螺旋バネが半導体ウェハ12の取り込み/取り出しをなす把持アームと干渉しないようにする目的から、ロッド44をステージ38の上面より高い位置まで伸張できるようにしている。
【0024】
そして前記シリンダ装置40のロッド44先端と、アンカーガイド46の先端との間には、両部材を連結するように環状部材となる螺旋バネ48が取り付けられている。当該螺旋バネ48は、その内径が平板電極34の外径よりも若干大きく設定されており、螺旋バネ48内に平板電極34を取り込み可能にしている。またバネ全長も少なくとも一対の平板電極34を覆うだけの長さに設定されている。なお螺旋バネ48は一定の幅を有した断面四角形の部材を螺旋状に形成したもので、その側面に形成される隙間は一定間隔になっている。
【0025】
ここで環状部材となる螺旋バネの形状は、CVD対象物の外径にあわせて設定すればよい。すなわちCVD対象物が円形の半導体ウェハである場合には円形に設定すればよく、またCVD対象物がノートパソコンの液晶パネルを切り出す四角形状の基板である場合は、これにあわせて螺旋バネの形状を四角形に設定すればよい。
【0026】
このように構成されたプラズマCVD装置10を用いて、半導体ウェハ12の表面に成膜を形成する手順を説明する。
【0027】
図3は、半導体ウェハへの成膜手順を示す工程説明図である。同図に示すように、まず吸引機構を用いてステージ38の表面に半導体ウェハ12を密着固定させた後、開閉バルブ24を開き反応ガス50をチャンバ14内に導入させ、既に稼働している真空ポンプ30の吸引力によって反応ガス50がチャンバ14内を通過するようにする。なおこの状態では、反応ガス50は螺旋バネ48の側面に形成される隙間52から、螺旋バネ48の内側と一対の平板電極34とで形成されるプラズマ封止領域54に進入し、反対側の隙間52より排出される状態になっている。
【0028】
そしてプラズマ封止領域54を反応ガス50が通過する状態になった後、電源装置36を稼働させ、一対の平板電極34の間でプラズマ放電を発生させる。なおこのプラズマ放電の際、シリンダ装置40におけるロッド44を伸張させておき隙間52の間隔(図中t1寸法)を狭めておく。
【0029】
このような状態でプラズマ放電をさせると、プラズマ封止領域54を通過する反応ガス50がプラズマ化し、これによって半導体ウェハ12の表面に絶縁層となる酸化膜や、配線となる多結晶シリコン、金属シリサイド膜、合金膜などが形成される。
【0030】
ここで平板電極34からエネルギを得てプラズマ化した反応ガス50は、拡散作用により螺旋バネ48の隙間52に進入するが、反応ガス50のプラズマ粒子は狭い隙間52を通過する際、螺旋バネ48の表面に衝突を繰り返すのでプラズマ粒子自体のエネルギが失われる。故に隙間52を通過した後は、反応ガス50はプラズマの状態から通常の気体の状態に戻るので、螺旋バネ48の外側すなわちチャンバ14の内壁に反応ガス50による生成物が付着するのを防止することができる。
【0031】
またプラズマが存在する領域すなわちプラズマ封止領域54は、同図(1)においてA寸法で示されており、この範囲内でプラズマ反応は集中して行われることから半導体ウェハ12における成膜速度を向上させることができる。
【0032】
そして半導体ウェハ12の表面に成膜を任意の膜厚まで形成した後は、開閉バルブ24を閉じ反応ガス50のチャンバ14内への導入を停止させるとともに、電源装置36の稼働を停止させ成膜工程を終了させる。その後はシリンダ装置40のロッド44を伸張させ、ロッド44の先端の高さをステージ38の上方まで移動させる。このようにロッド44を伸張させれば螺旋バネ48が圧縮され、ステージ38の側方から伸張される把持アームが螺旋バネ48に干渉せずに成膜形成後の半導体ウェハ12をチャンバ14の外部に取り出すことができる。
【0033】
このように半導体ウェハ12をチャンバ14の外部に取り出した後は、シリンダ装置40のロッド44を成膜工程時よりも引き込み、螺旋バネ48を成膜工程時の間隔(t1)より広く設定する。この時の隙間52の間隔をt2とし同図(2)に示す。なお同図(2)は、螺旋バネ48に付着した反応ガス50による生成物56の除去を行う清掃工程を示している。同図(2)に示すように清掃工程時は、隙間52の間隔を成膜工程時よりも広くする(t2>t1)。そしてこの状態から開閉バルブ26を開きPFC58をチャンバ14内に導入させるとともに電源装置36を稼働させプラズマ封止領域54にPFC58のプラズマを発生させる。なお前記隙間52の拡開に伴いプラズマ封止領域54は図中B寸法に示されるように拡大する。
【0034】
ここで隙間52の拡大に対応してプラズマ封止領域54が拡大する理由は下記の通りである。
【0035】
前述のとおり隙間52を通過するプラズマ粒子は、前記隙間52を形成する螺旋バネ48に衝突を繰り返してエネルギを失っていくが、隙間52の間隔が広くなると螺旋バネ48への衝突の回数が減り、その分だけプラズマ粒子は外方へと移動する。このため隙間52の間隔を広げるとプラズマ粒子が存在する領域すなわちプラズマ封止領域54が拡大するのである。
【0036】
このようにプラズマ封止領域54を拡大すれば、当該プラズマ封止領域54が狭かった際に螺旋バネ48に付着した生成物56は全て拡大したプラズマ封止領域54内に含まれることとなり、プラズマ化したPFC58に接する。故に螺旋バネ48に付着した生成物56はプラズマ化したPFC58に反応し、チャンバ14外部へと排出される。そして前述した清掃作業は、プラズマ封止領域54のみに対して行われることから、清掃時間およびPFC58の使用量を低減することができる。
【0037】
なお前述した清掃工程が終了すれば、シリンダ装置40のロッド44の伸張により螺旋バネ48を圧縮させ、把持アームによって新たな成膜対象となる半導体ウェハ12をステージ38に搭載する。そして新たな半導体ウェハ12をステージ38上に搭載した後はロッド44を引き込み、螺旋バネ48の隙間52を同図(1)に示すt1寸法に設定し、その後成膜工程を行うようにすればよい。
【0038】
このように成膜工程と清掃工程とを繰り返し行うようにすれば、チャンバ14の内側全体を清掃する必要が無くなり、清掃時間の短縮と清掃に用いるPFC58の使用量の低減を図ることができる。
【0039】
【発明の効果】
以上説明したように本発明によれば、半導体ウェハが装着されたチャンバに反応ガスを導入するとともに前記半導体ウェハを内包する複数の環状部材の間隔を狭め当該環状部材の内側に形成されたプラズマ封止領域内でプラズマ化した前記反応ガスにより前記半導体ウェハの成膜をなす成膜工程と、半導体ウェハを取り除いた前記チャンバにPFCを導入させるとともに前記環状部材の間隔を前記成膜工程時よりも拡開させ前記プラズマ封止領域を拡大し前記成膜工程にて前記環状部材に付着した生成物をプラズマ化した前記PFCにて除去する清掃工程とを有するようにしたり、
またプラズマCVD装置を、反応ガスとPFCとを導入可能とするチャンバを設けるとともに当該チャンバ内にプラズマ発生手段を設け、前記チャンバ内に設置される半導体ウェハへの成膜をなすプラズマCVD装置であって、前記チャンバ内に前記半導体ウェハを内包可能な環状部材を設けこれをプラズマ封止領域とするとともに前記環状部材に間隔調整部を設け、前記プラズマ封止領域内に導入された前記反応ガスをプラズマ化し前記半導体ウェハへの成膜をなした後に、前記プラズマ封止領域内に導入された前記PFCをプラズマ化し前記プラズマ封止領域に付着した生成物を除去可能にしたことから、成膜工程にて生じた生成物の除去を行うPFCの使用量を低減させるとともに、その清掃時間の短縮を図ることができる。
【図面の簡単な説明】
【図1】本実施の形態に係るプラズマCVD装置の構成を示す説明図である。
【図2】プラズマCVD装置の内部構造を示した部品展開図である。
【図3】半導体ウェハへの成膜手順を示す工程説明図である。
【図4】従来のプラスマCVD装置を用いた成膜工程を示す説明図である。
【符号の説明】
1………プラズマCVD装置
2………半導体ウェハ
3………チャンバ
4………プラズマ発生装置
5………平板電極
6………電源装置
7………成膜したい構成元素を有した気体
8………生成物
9………PFC
10………プラズマCVD装置
12………半導体ウェハ
14………チャンバ
16………配管
18………第1ガスボンベ
20………配管
22………第2ガスボンベ
24………開閉バルブ
26………開閉バルブ
28………配管
30………真空ポンプ
32………プラズマ発生装置
34………平板電極
36………電源装置
38………ステージ
40………シリンダ装置
42………天井
44………ロッド
46………アンカーガイド
48………螺旋バネ
50………成膜したい構成元素を有した気体
52………隙間
54………プラズマ封止領域
56………生成物
58………PFC
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor wafer and a plasma CVD apparatus, and more particularly, to a method for manufacturing a semiconductor wafer and a plasma to efficiently perform film formation on the semiconductor wafer and removal of products generated by the film formation process. The present invention relates to a CVD apparatus.
[0002]
[Prior art]
In a semiconductor device, impurities are implanted into the surface of a disk-shaped silicon substrate (hereinafter referred to as a semiconductor wafer), transistors, resistors, capacitors, and the like are formed on the surface, and an insulating film and wiring are further formed on the surface. It is manufactured by.
[0003]
By the way, a CVD method (Chemical Vapor Deposition method) is known as a method for forming an insulating film on the surface of a semiconductor wafer or depositing polysilicon as a wiring base. A plasma CVD method using plasma discharge as a source is widely used.
[0004]
FIG. 4 is an explanatory view showing a film forming process using a conventional plasma CVD apparatus. As shown in FIG. 1A, a plasma CVD apparatus 1 for performing the plasma CVD method includes a chamber 3 that allows a semiconductor wafer 2 to be processed to be charged, and a plasma provided in the chamber 3. It is comprised with the generator 4. The plasma generator 4 is composed of a pair of plate electrodes 5 and a power supply device 6 capable of applying a high frequency voltage between the plate electrodes 5 so as to generate plasma discharge between the plate electrodes 5. Yes.
[0005]
In the plasma CVD apparatus 1 configured as described above, the semiconductor wafer 2 is first put into the chamber 3, and the semiconductor wafer 2 is placed between the plate electrodes 5 constituting the plasma generator 4. Then, a gas (hereinafter referred to as a reaction gas) 7 having a constituent element to be deposited on the surface of the semiconductor wafer 2 is introduced into the chamber 3 and the plasma generator 4 is operated to generate plasma between the flat plate electrodes 5. Then, film formation is performed on the surface of the semiconductor wafer 2.
[0006]
After the film formation on the semiconductor wafer 2 is completed, the product 8 is also attached to the inner wall of the chamber 3 due to the reaction gas plasmatization as shown in FIG. The product 8 is peeled off from the wall surface of the chamber 3 in the next and subsequent film formation processes, and may accumulate on the surface of the semiconductor wafer 2, which may cause an obstacle. 3, PFC (perfluorocarbon and a compound (HFC) in which a part of fluorine thereof is replaced with hydrogen) 9 is introduced, and this is converted into plasma to remove the product 8.
[0007]
[Problems to be solved by the invention]
However, the above-described plasma CVD apparatus has the following problems.
[0008]
In other words, as described above, in the plasma CVD apparatus (where it is desired to form a film only on the surface of the semiconductor wafer), a region where plasma is generated (hereinafter referred to as a plasma generation region) reaches the inner wall of the chamber. A product that hinders the film forming process adheres to the inner wall of the chamber. In order to remove the product attached to the chamber, PFC is introduced as a cleaning process after the film forming process. The PFC has a GWP (global warming potential) of several thousands to several carbon dioxide. 10,000 times higher. For this reason, it is not environmentally preferable to use a large amount of the PFC to remove the product adhering to the inner wall of the chamber.
[0009]
The present invention pays attention to the above-mentioned conventional problems, and reduces the amount of PFC used for removing products generated in the film forming process, and shortens the cleaning time, and a method for manufacturing a semiconductor wafer. An object is to provide a plasma CVD apparatus.
[0010]
[Means for Solving the Problems]
In the present invention, if the plasma generation region surrounding the semiconductor wafer is reduced in the chamber, the product can be prevented from adhering to the chamber and the product can be prevented from diffusing. This is based on the knowledge that the amount can be reduced and the cleaning time can be shortened.
[0011]
That is, the semiconductor wafer manufacturing method according to claim 1 is formed inside the annular member by introducing a reaction gas into the chamber in which the semiconductor wafer is mounted and narrowing the interval between the plurality of annular members containing the semiconductor wafer. A film forming step of forming a film of the semiconductor wafer with the reaction gas converted into plasma in the plasma sealing region;
The PFC is introduced into the chamber from which the semiconductor wafer has been removed, and the interval between the annular members is expanded more than that during the film formation step, so that the plasma sealing region is enlarged, and the generation is attached to the annular member during the film formation step. And a cleaning step of removing the object with the PFC converted into plasma. According to the semiconductor wafer manufacturing method of the first aspect, during the film forming process, the annular member is laminated at a constant interval, and the semiconductor wafer is placed at the center. Then, if the region enclosed in the annular member is set as the plasma sealing region, the reaction gas introduced into the chamber enters the plasma sealing region through the gap between the annular members, and is converted into plasma in the plasma sealing region. The film is formed on the semiconductor wafer. And the reactive gas which performed the plasma process escapes out of a plasma sealing area | region through a clearance gap again. By the way, plasma is a state in which electrons in an atom jump out of the electron shell and these electrons and atoms are moving at high speed (as a whole, it is almost electrically neutral). For this reason, if a plurality of annular members are kept at regular intervals (if the annular members are arranged so that a gap is formed), electrons and atoms that move at high speed jump out of the plasma sealing region. When trying to do so, electrons and atoms collide with the annular member forming the gap, the energy is lost, and the plasma disappears. Therefore, it is possible to prevent the plasma from diffusing beyond the annular member constituting the plasma sealing region, and it is possible to prevent the reaction product from adhering to the inner wall of the chamber located outside the plasma sealing region. it can. Since the plasma reaction is concentrated in the plasma sealing region, it is possible to improve the deposition rate on the semiconductor wafer.
[0012]
In the cleaning process, it is not necessary to clean the inner wall of the chamber, and the product may be removed only from the plasma sealing region. Here, if the interval between the annular members is made wider than that during the film forming process, the plasma particles of PFC reach the outside by an amount corresponding to the increase in the interval between the annular members, so that the energy is maintained far from the film forming step. As a result, the plasma sealing region becomes larger than that in the film forming process. For this reason, the product adhering to the annular member during the film forming step can be reliably removed. In addition, since product adhesion occurs only in the plasma sealing region, it is possible to reduce the amount of PFC used to remove the product and to shorten the time for removing the product, that is, the cleaning time. Needless to say.
[0013]
The shape of the plurality of annular members enclosing the semiconductor wafer is not limited to a circle, and various shapes can be applied to the shape of the CVD object, as represented by a planar square shape. is there.
[0014]
The plasma CVD apparatus according to claim 2 is provided with a chamber capable of introducing the reaction gas and the PFC, and also provided with plasma generating means in the chamber to form a film on a semiconductor wafer installed in the chamber. In the plasma CVD apparatus, an annular member capable of containing the semiconductor wafer is provided in the chamber, and this is used as a plasma sealing region, and an interval adjusting portion is provided in the annular member, and is introduced into the plasma sealing region. In addition, after the reaction gas is converted into plasma and the film is formed on the semiconductor wafer, the PFC introduced into the plasma sealing region is converted into plasma so that products attached to the plasma sealing region can be removed. It is characterized by. According to the plasma CVD apparatus according to claim 2, during the film forming process, the gap interval adjustment unit is operated, and the region enclosed by the annular member laminated at a certain interval is configured as the plasma sealing region. In this case, the reaction gas introduced into the chamber enters the plasma sealing region through the gap between the annular members, and is converted into plasma in the plasma sealing region to form a film on the semiconductor wafer. And the reactive gas which performed the plasma process escapes out of a plasma sealing area | region through a clearance gap again. By the way, plasma is a state in which electrons in an atom jump out of the electron shell and these electrons and atoms are moving at high speed (as a whole, it is almost electrically neutral). For this reason, if a plurality of annular members are kept at regular intervals (if the annular members are arranged so that a gap is formed), electrons and atoms that move at high speed jump out of the plasma sealing region. When trying to do so, electrons and atoms collide with the annular member forming the gap, the energy is lost, and the plasma disappears. Therefore, it is possible to prevent the plasma from diffusing beyond the annular member constituting the plasma sealing region, and it is possible to prevent the reaction product from adhering to the inner wall of the chamber located outside the plasma sealing region. it can. Since the plasma reaction is concentrated in the plasma sealing region, it is possible to improve the deposition rate on the semiconductor wafer.
[0015]
In the cleaning process, it is not necessary to clean the inner wall of the chamber, and the product may be removed only from the plasma sealing region. If the gap interval adjusting unit is operated again and the interval between the annular members is increased from the time of the film formation process, the distance between the annular members increases to the outside, so that the energy is increased far from the film formation process. As a result, the plasma sealing region is expanded more than in the film forming process. For this reason, the product adhering to the annular member during the film forming step can be reliably removed. In addition, since product adhesion occurs only in the plasma sealing region, it is possible to reduce the amount of PFC used to remove the product and to shorten the time for removing the product, that is, the cleaning time. Needless to say.
[0016]
The plasma CVD apparatus according to claim 3 is characterized in that the annular member is formed of a spiral spring member. According to the plasma CVD apparatus according to claim 3, if the gap interval adjusting portion is used as an elevating mechanism and arranged at the end of the spiral spring member, the spring member expands and contracts by moving the elevating mechanism up and down, and the spring The gap between the gaps formed on the side surfaces of the member can be adjusted. For this reason, the gap interval can be adjusted without providing a complicated mechanism.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Specific embodiments suitable for a semiconductor wafer manufacturing method and a plasma CVD apparatus according to the present invention will be described below in detail with reference to the drawings.
[0018]
FIG. 1 is an explanatory view showing the configuration of the plasma CVD apparatus according to the present embodiment, and FIG. 2 is a component development view showing the internal structure of the plasma CVD apparatus.
[0019]
As shown in these drawings, in the plasma CVD apparatus 10 according to the present embodiment, a chamber 14 capable of taking in a semiconductor wafer 12 to be processed is provided. A first gas cylinder 18 filled with a gas having a constituent element to be deposited (hereinafter referred to as a reaction gas) on the surface of the wafer 12 and a second gas cylinder 22 filled with PFC via a pipe 20 are attached. Yes. An opening / closing valve 24 and an opening / closing valve 26 are attached to the pipe 16 and the pipe 20 described above, and an arbitrary gas can be introduced into the chamber 14 by opening / closing the opening / closing valves.
[0020]
On the other hand, a pipe 28 is also drawn from the rear stage side of the chamber 14, and a vacuum pump 30 is provided in the middle of the pipe. Then, by operating the vacuum pump 30, suction into the chamber 14 can be performed, and the inside of the chamber 14 can be brought into an arbitrary reduced pressure state. Further, by the suction operation of the vacuum pump 30, the gas sent from the first gas cylinder 18 and the second gas cylinder 22 is sent to the rear stage side so that the gas can pass through the chamber 14.
[0021]
A plasma generator 32 is provided inside the chamber 14. The plasma generator 32 includes a pair of flat plate electrodes 34 provided above and below the chamber 14, and a power supply device 36 that can apply a high-frequency voltage between the flat plate electrodes 34. Plasma discharge is generated.
[0022]
A stage 38 for mounting the semiconductor wafer 12 is attached to the upper surface of the flat plate electrode 34 (lower flat plate electrode 34 in the figure) on the installation potential side. Here, the stage 38 has a lifting mechanism for projecting a boss from the surface to form a gap between the stage 38 and the semiconductor wafer 12 and a suction mechanism for bringing the semiconductor wafer 12 into close contact with the surface of the stage 38. Is provided. Although not shown, a gripping arm that can be extended on the stage 38 is provided outside the chamber 14. The gripping arm is inserted into the gap between the stage 38 and the semiconductor wafer 12 formed by the lifting mechanism. The semiconductor wafer 12 can be taken in / out.
[0023]
By the way, cylinder devices 40 extending in the ceiling direction of the chamber 14 are provided at four locations around the flat plate electrode 34 (the flat plate electrode 34 on the lower side in the drawing) on the installation potential side. An anchor guide 46 is provided to align the axis with the rod 44 of the cylinder device 40. In the cylinder device 40, the rod 44 can be extended to a position higher than the upper surface of the stage 38 for the purpose of preventing a later-described spiral spring from interfering with a gripping arm that takes in / out the semiconductor wafer 12.
[0024]
A helical spring 48 serving as an annular member is attached between the tip of the rod 44 of the cylinder device 40 and the tip of the anchor guide 46 so as to connect both members. The inner diameter of the spiral spring 48 is set to be slightly larger than the outer diameter of the flat plate electrode 34 so that the flat plate electrode 34 can be taken into the spiral spring 48. The total length of the spring is also set to a length that covers at least the pair of flat plate electrodes 34. The spiral spring 48 is formed by spirally forming a member having a square cross section having a certain width, and the gaps formed on the side surfaces thereof are at regular intervals.
[0025]
Here, the shape of the spiral spring serving as the annular member may be set according to the outer diameter of the CVD object. In other words, if the CVD object is a circular semiconductor wafer, it may be set to a circle, and if the CVD object is a quadrangular substrate that cuts out a liquid crystal panel of a notebook computer, the shape of the spiral spring is adjusted accordingly. Should be set to a square.
[0026]
A procedure for forming a film on the surface of the semiconductor wafer 12 using the plasma CVD apparatus 10 configured as described above will be described.
[0027]
FIG. 3 is a process explanatory view showing a film forming procedure on a semiconductor wafer. As shown in the figure, first, after the semiconductor wafer 12 is firmly fixed to the surface of the stage 38 by using a suction mechanism, the open / close valve 24 is opened to introduce the reaction gas 50 into the chamber 14, and the vacuum already in operation. The reaction gas 50 is caused to pass through the chamber 14 by the suction force of the pump 30. In this state, the reactive gas 50 enters the plasma sealing region 54 formed by the inner side of the spiral spring 48 and the pair of flat plate electrodes 34 from the gap 52 formed on the side surface of the spiral spring 48, and on the opposite side. It is in a state of being discharged from the gap 52.
[0028]
After the reactive gas 50 passes through the plasma sealing region 54, the power supply device 36 is operated to generate plasma discharge between the pair of flat plate electrodes 34. In this plasma discharge, the rod 44 in the cylinder device 40 is extended to narrow the gap 52 (t1 dimension in the figure).
[0029]
When plasma discharge is performed in such a state, the reaction gas 50 that passes through the plasma sealing region 54 is turned into plasma, whereby an oxide film serving as an insulating layer on the surface of the semiconductor wafer 12, polycrystalline silicon serving as wiring, metal A silicide film, an alloy film, or the like is formed.
[0030]
Here, the reaction gas 50 that has been converted into plasma by obtaining energy from the plate electrode 34 enters the gap 52 of the spiral spring 48 by the diffusion action, but when the plasma particles of the reaction gas 50 pass through the narrow gap 52, the spiral spring 48. The energy of the plasma particles themselves is lost because of repeated collisions with the surface. Therefore, after passing through the gap 52, the reaction gas 50 returns from the plasma state to the normal gas state, so that the product of the reaction gas 50 is prevented from adhering to the outside of the spiral spring 48, that is, the inner wall of the chamber 14. be able to.
[0031]
A region where plasma exists, that is, a plasma sealing region 54 is indicated by a dimension A in FIG. 1A. Since the plasma reaction is concentrated within this range, the film formation rate on the semiconductor wafer 12 is increased. Can be improved.
[0032]
After the film is formed on the surface of the semiconductor wafer 12 to an arbitrary film thickness, the opening / closing valve 24 is closed to stop the introduction of the reaction gas 50 into the chamber 14 and the operation of the power supply device 36 is stopped to form the film. Finish the process. Thereafter, the rod 44 of the cylinder device 40 is extended, and the height of the tip of the rod 44 is moved to above the stage 38. When the rod 44 is extended in this manner, the helical spring 48 is compressed, and the gripping arm extended from the side of the stage 38 does not interfere with the helical spring 48, and the semiconductor wafer 12 after film formation is placed outside the chamber 14. Can be taken out.
[0033]
After the semiconductor wafer 12 is taken out of the chamber 14 in this way, the rod 44 of the cylinder device 40 is pulled in more than during the film formation process, and the spiral spring 48 is set wider than the interval (t1) during the film formation process. The interval of the gap 52 at this time is shown as t2 in FIG. FIG. 2B shows a cleaning process in which the product 56 is removed by the reaction gas 50 attached to the spiral spring 48. As shown in FIG. 2B, the gap 52 is made wider during the cleaning process than during the film forming process (t2> t1). In this state, the opening / closing valve 26 is opened to introduce the PFC 58 into the chamber 14, and the power supply device 36 is operated to generate plasma of the PFC 58 in the plasma sealing region 54. As the gap 52 expands, the plasma sealing region 54 expands as shown by dimension B in the figure.
[0034]
Here, the reason why the plasma sealing region 54 is enlarged corresponding to the enlargement of the gap 52 is as follows.
[0035]
As described above, the plasma particles passing through the gap 52 repeatedly collide with the spiral spring 48 forming the gap 52 and lose energy. However, as the gap 52 becomes wider, the number of collisions with the spiral spring 48 decreases. The plasma particles move outward by that much. Therefore, when the gap 52 is widened, the region where the plasma particles are present, that is, the plasma sealing region 54 is enlarged.
[0036]
When the plasma sealing region 54 is enlarged in this way, all the products 56 attached to the spiral spring 48 when the plasma sealing region 54 is narrow are included in the enlarged plasma sealing region 54. It contacts the converted PFC58. Therefore, the product 56 adhering to the spiral spring 48 reacts with the PFC 58 that has been converted to plasma, and is discharged to the outside of the chamber 14. And since the cleaning operation mentioned above is performed only to the plasma sealing area | region 54, the cleaning time and the usage-amount of PFC58 can be reduced.
[0037]
When the above-described cleaning process is completed, the helical spring 48 is compressed by the extension of the rod 44 of the cylinder device 40, and the semiconductor wafer 12 to be newly formed by the gripping arm is mounted on the stage 38. Then, after the new semiconductor wafer 12 is mounted on the stage 38, the rod 44 is pulled in, the gap 52 of the spiral spring 48 is set to the dimension t1 shown in FIG. Good.
[0038]
If the film forming process and the cleaning process are repeated as described above, it is not necessary to clean the entire inside of the chamber 14, and the cleaning time can be shortened and the amount of PFC 58 used for cleaning can be reduced.
[0039]
【The invention's effect】
As described above, according to the present invention, the plasma gas formed inside the annular member by introducing the reaction gas into the chamber in which the semiconductor wafer is mounted and narrowing the interval between the plurality of annular members enclosing the semiconductor wafer. A film forming step of forming the semiconductor wafer with the reaction gas converted into plasma in a stop region; and introducing a PFC into the chamber from which the semiconductor wafer has been removed and setting the interval between the annular members to be larger than that in the film forming step. And expanding the plasma sealing region to have the cleaning process of removing the product adhering to the annular member in the film forming process with the PFC converted into plasma,
In addition, the plasma CVD apparatus is provided with a chamber capable of introducing a reaction gas and PFC, and also provided with a plasma generating means in the chamber to form a film on a semiconductor wafer installed in the chamber. An annular member capable of enclosing the semiconductor wafer is provided in the chamber, and this is used as a plasma sealing region, and an interval adjusting portion is provided in the annular member, and the reaction gas introduced into the plasma sealing region is Since the PFC introduced into the plasma sealing region is converted into plasma after the film formation on the semiconductor wafer is made into plasma, the product adhering to the plasma sealing region can be removed. In addition to reducing the amount of PFC used to remove the product produced in step 1, the cleaning time can be shortened.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram showing a configuration of a plasma CVD apparatus according to the present embodiment.
FIG. 2 is an exploded view showing the internal structure of the plasma CVD apparatus.
FIG. 3 is a process explanatory diagram showing a film forming procedure on a semiconductor wafer;
FIG. 4 is an explanatory view showing a film forming process using a conventional plasma CVD apparatus.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ......... Plasma CVD apparatus 2 ......... Semiconductor wafer 3 ......... Chamber 4 ......... Plasma generator 5 ......... Plate electrode 6 ......... Power supply device 7 ......... Gas having a constituent element to be formed 8 ……… Product 9 ……… PFC
10 ... Plasma CVD apparatus 12 ... Semiconductor wafer 14 ... Chamber 16 ... Piping 18 ... First gas cylinder 20 ... Pipe 22 ... Second gas cylinder 24 ... Open / close valve 26 ... ...... Opening and closing valve 28 ...... Piping 30 ...... Vacuum pump 32 ...... Plasma generator 34 ...... Plate electrode 36 ...... Power supply 38 ...... Stage 40 ...... Cylinder device 42 ...... Ceiling 44... Rod 46... Anchor guide 48... Helical spring 50... Gas 52 with constituent elements to be deposited 52. ……… PFC

Claims (3)

半導体ウェハが装着されたチャンバに反応ガスを導入するとともに前記半導体ウェハを内包する複数の環状部材の間隔を狭め当該環状部材の内側に形成されたプラズマ封止領域内でプラズマ化した前記反応ガスにより前記半導体ウェハの成膜をなす成膜工程と、
半導体ウェハを取り除いた前記チャンバにPFCを導入させるとともに前記環状部材の間隔を前記成膜工程時よりも拡開させ前記プラズマ封止領域を拡大し前記成膜工程にて前記環状部材に付着した生成物をプラズマ化した前記PFCにて除去する清掃工程とを有することを特徴とする半導体ウェハの製造方法。
The reaction gas is introduced into the chamber in which the semiconductor wafer is mounted and the intervals between the plurality of annular members enclosing the semiconductor wafer are narrowed, and the reaction gas converted into plasma in the plasma sealing region formed inside the annular member is used. A film forming step for forming the semiconductor wafer;
The PFC is introduced into the chamber from which the semiconductor wafer has been removed, and the interval between the annular members is expanded more than that during the film formation step, so that the plasma sealing region is enlarged, and the generation is attached to the annular member during the film formation step. And a cleaning step of removing the object with the PFC converted into plasma.
反応ガスとPFCとを導入可能とするチャンバを設けるとともに当該チャンバ内にプラズマ発生手段を設け、前記チャンバ内に設置される半導体ウェハへの成膜をなすプラズマCVD装置であって、前記チャンバ内に前記半導体ウェハを内包可能な環状部材を設けこれをプラズマ封止領域とするとともに前記環状部材に間隔調整部を設け、前記プラズマ封止領域内に導入された前記反応ガスをプラズマ化し前記半導体ウェハへの成膜をなした後に、前記プラズマ封止領域内に導入された前記PFCをプラズマ化し前記プラズマ封止領域に付着した生成物を除去可能にしたことを特徴とするプラズマCVD装置。A plasma CVD apparatus for providing a chamber capable of introducing a reaction gas and PFC and providing plasma generation means in the chamber, and forming a film on a semiconductor wafer installed in the chamber, An annular member capable of enclosing the semiconductor wafer is provided, and this is used as a plasma sealing region, and an interval adjusting portion is provided in the annular member, and the reaction gas introduced into the plasma sealing region is converted into plasma and applied to the semiconductor wafer. The plasma CVD apparatus is characterized in that, after the film formation is performed, the PFC introduced into the plasma sealing region is converted into plasma so that a product attached to the plasma sealing region can be removed. 前記環状部材は、螺旋状のバネ部材からなることを特徴とする請求項2に記載のプラズマCVD装置。The plasma CVD apparatus according to claim 2, wherein the annular member is a spiral spring member.
JP2000145338A 2000-05-17 2000-05-17 Semiconductor wafer manufacturing method and plasma CVD apparatus Expired - Fee Related JP3632564B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000145338A JP3632564B2 (en) 2000-05-17 2000-05-17 Semiconductor wafer manufacturing method and plasma CVD apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000145338A JP3632564B2 (en) 2000-05-17 2000-05-17 Semiconductor wafer manufacturing method and plasma CVD apparatus

Publications (2)

Publication Number Publication Date
JP2001326184A JP2001326184A (en) 2001-11-22
JP3632564B2 true JP3632564B2 (en) 2005-03-23

Family

ID=18651861

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000145338A Expired - Fee Related JP3632564B2 (en) 2000-05-17 2000-05-17 Semiconductor wafer manufacturing method and plasma CVD apparatus

Country Status (1)

Country Link
JP (1) JP3632564B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6433484B1 (en) * 2000-08-11 2002-08-13 Lam Research Corporation Wafer area pressure control
CN107276405B (en) * 2017-05-27 2019-06-04 南京理工大学 The fine electric spark pulse power and Discrete control method based on the power supply

Also Published As

Publication number Publication date
JP2001326184A (en) 2001-11-22

Similar Documents

Publication Publication Date Title
JP4666912B2 (en) Plasma reinforced atomic layer deposition apparatus and thin film forming method using the same
US5405491A (en) Plasma etching process
JP3606588B2 (en) Method and apparatus for metallizing silicon semiconductor device contacts with high aspect ratio
JP5893864B2 (en) Plasma etching method
JP5319782B2 (en) Method and apparatus for deforming cross-sectional shape of trench and via
US5954887A (en) Cleaning processing method of a film forming apparatus
US20030119328A1 (en) Plasma processing apparatus, and cleaning method therefor
US20090221148A1 (en) Plasma etching method, plasma etching apparatus and computer-readable storage medium
JPH0689873A (en) Formation of metal thin film by chemical vapor growth
US20040242012A1 (en) Method of plasma treatment
KR20170039573A (en) Silicide phase control by confinement
US7351665B2 (en) Plasma etching method, plasma etching apparatus, control program, computer recording medium and recording medium having processing recipe recorded thereon
WO2019103995A1 (en) Methods of reducing or eliminating defects in tungsten film
JP4151308B2 (en) Gas introduction method for processing equipment
JP4405715B2 (en) Method of forming silicon nanocrystal structure terminated with oxygen or nitrogen and silicon nanocrystal structure terminated with oxygen or nitrogen formed thereby
JPH06338479A (en) Etching method
JP3632564B2 (en) Semiconductor wafer manufacturing method and plasma CVD apparatus
JP2001176807A (en) Device and method for manufacturing semiconductor device, and cleaning method
JPH0722393A (en) Dry etching equipment and method
EP0791669B1 (en) Method for etching inside of cvd reaction chamber
CN110622282B (en) Deposition of metal silicide layers on substrates and chamber components
CN116065140A (en) Thin film deposition method
JP3951976B2 (en) Plasma processing method
JP3335762B2 (en) Plasma cleaning method
JPH11307521A (en) Plasma cvd equipment and its use

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20040113

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20041118

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20041130

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20041213

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090107

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100107

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110107

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110107

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120107

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120107

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130107

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130107

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140107

Year of fee payment: 9

LAPS Cancellation because of no payment of annual fees