JP3603423B2 - Semiconductor device - Google Patents

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JP3603423B2
JP3603423B2 JP27832895A JP27832895A JP3603423B2 JP 3603423 B2 JP3603423 B2 JP 3603423B2 JP 27832895 A JP27832895 A JP 27832895A JP 27832895 A JP27832895 A JP 27832895A JP 3603423 B2 JP3603423 B2 JP 3603423B2
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JPH09102563A (en
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均 深谷
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Yamaha Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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Description

【０００１】
【発明の属する技術分野】
この発明は、樹脂封止されたＩＣ（集積回路）素子等の半導体素子を備えた半導体装置に関し、特に樹脂封止半導体素子を保持部材に設けた孔又は凹部に固定して端子導出を行なうことによりリードピッチの減少を可能とし、多端子化を容易にしたものである。
【０００２】
【従来の技術】
従来、樹脂封止ＩＣ素子としては、図６に示すＱＦＰ（Ｑｕａｄ Ｆｌａｔ
ｐａｃｋａｇｅ）型のものが知られている。
【０００３】
ＩＣ素子１は、図７に示すようなリードフレームを用いて製作される。ＩＣを内蔵した半導体チップ３は、リードフレームにおいてアイランドと呼ばれる支持部材２に固定される。４ａ，４ｂを含む多数のリード４は、半導体チップ３上の多数の電極（図示せず）にボンディングワイヤによりそれぞれ接続される。例えば、リード４ａ，４ｂは、ボンディングワイヤ５ａ，５ｂにより半導体チップ３上の対応する電極にそれぞれ接続される。
【０００４】
支持部材２、半導体チップ３、各リード４のインナーリード部及び５ａ，５ｂ等のボンディングワイヤは、樹脂体６によりモールド封止される。図７において、一点鎖線６Ａは、樹脂体６の輪郭を示す。
【０００５】
この後、リードフレームから図７にてハッチングを施した部分が切断除去される。このとき、樹脂モールド時に型から樹脂が流出するのを阻止していたダムバー４ｄが切断除去されることにより隣り合うリードが電気的に分離される。各リードのアウターリード部は、実装を容易にするために適宜折り曲げられる。
【０００６】
ＩＣ素子１をプリント基板７に実装する際には、各リードのアウターリード部が半田等により対応する配線層に接続される。例えば、リード４ａ，４ｂのアウターリード部は、配線層８ａ，８ｂにそれぞれ接続される。
【０００７】
図８は、従来のＩＣ素子の他の例を示すもので、この例の素子は、ＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）として知られている。
【０００８】
ＩＣ素子１０は、接続孔１１ａを有する基板１１を備えている。基板１１の上面には、ＩＣを内蔵した半導体チップ１３が接着層１２により固定される。基板１１上には、半導体チップ１３上の多数の電極（図示せず）に対応して１４ａ，１４ｂ等の多数の配線層が形成されており、これらの配線層は、半導体チップ１３上の対応する電極にボンディングワイヤによりそれぞれ接続される。例えば、配線層１４ａ，１４ｂは、ボンディングワイヤ１５ａ，１５ｂにより半導体チップ１３上の対応する電極に接続される。
【０００９】
基板１１において、半導体チップ１３を固定した面には、モールド樹脂体１６が設けられる。樹脂体１６は、半導体チップ１３、ボンディングワイヤ１５ａ，１５ｂ、配線層１４ａ，１４ｂの接続部等を封止する。
【００１０】
基板１１において、半導体チップ１３を固定した面とは反対側の面には、１５ａ，１５ｂ等のボンディングワイヤを接続した１４ａ，１４ｂ等の配線層に対応して多数の半田バンプ等の端子電極１７が設けられる。１４ａ，１４ｂ等の配線層は、１１ａ等の接続孔を介して対応する端子電極１７に接続される。
【００１１】
ＩＣ素子１０をプリント基板に実装する際には、端子電極１７がプリント基板上の配線層にそれぞれ接続される。
【００１２】
【発明が解決しようとする課題】
図６のＩＣ素子によると、図７に示したようにダムバー４ｄを隣り合うリード間で切断除去する際に切断する刃の薄肉化に限界があり、隣り合うアウターリード部の中心線間の距離（リードピッチ）が小さく（例えば０．４ｍｍ以下に）なると、隣り合うアウターリード部を分離することができなかった。このため、分離可能な限界がリードピッチの限界となり、多端子化（多ピン化）が制約されていた。
【００１３】
一方、図８のＩＣ素子によると、ホトリソグラフィ及び選択エッチング技術により１４ａ，１４ｂ等の配線層を形成でき、多端子化が容易である利点があるものの、（イ）基板１１のチップ固定面のみ樹脂体１６で封止するため、モールド時の熱収縮量の違いにより基板１１にそりが生ずること、（ロ）基板１１と樹脂体１６との接着力が弱く、界面ではがれやすいこと、（ハ）端子電極１７が基板１１に隠れるため、実装状態を目視して確認できないことなどの問題点がある。
【００１４】
この発明の目的は、これらの問題点を解決することができ、しかもリードピッチの減少により多端子化を図ることができる新規な半導体装置を提供することにある。
【００１５】
【課題を解決するための手段】
この発明に係る半導体装置は、
半導体チップ上の多数の電極を多数のリードのインナーリード部にそれぞれ電気的に接続すると共に前記半導体チップ及び前記多数のリードのインナーリード部を互いに対向する２つのフラット面を有する偏平状の樹脂体で封止し、前記多数のリードのアウターリード部を前記樹脂体の側部において前記２つのフラット面の中間の位置から側方に直線的に導出した構成の半導体素子と、
この半導体素子を保持するための保持部材であって、一方の主表面には前記多数のリードのアウターリード部の導出位置から前記樹脂体の一方のフラット面側に位置する前記樹脂体の半分に順応した形状の孔又は凹部が設けられ、前記一方の主表面側で前記多数のリードのアウターリード部を前記孔又は凹部の周辺部に係止すると共に前記樹脂体の前記半分を前記孔又は凹部に挿入した状態で前記半導体素子が固定されたものと、
前記保持部材の一主表面側で前記孔又は凹部の周辺部に前記多数のリードにそれぞれ対応して形成された多数の導電層であって、対応するリードのアウターリード部に電気的に接続されたものと
を備えたものである。
【００１６】
この発明の構成によれば、樹脂封止半導体素子を保持部材に設けた孔又は凹部に固定すると共に該孔又は凹部の周辺部に設けた多数の導電層を介してプリント基板等の実装基板との接続を行なうようにしたので、各リードのアウターリード部は、電気的接続が許容される程度に短くてよい。このため、各リードのアウターリード部は、樹脂モールドの後ダムバー位置より短く切断することができ、従来のように隣り合うアウターリード部を分離するようにダムバーを切断する必要がない。従って、リードピッチは、ホトリソグラフィ及び選択エッチング技術により加工可能な限界まで減少可能であり、多端子化が容易となる。
【００１７】
【発明の実施の形態】
図１は、この発明に係る半導体装置のプリント基板への取付状態を示すもので、この装置の取付面を図２に示す。図２のＡ−Ａ’断面が図１に相当する。
【００１８】
ＩＣ素子１は、各リードのアウターリード部の切断位置を除き図６で前述したものと同様の構成であり、図６と同様の部分には同様の符号を付して詳細な説明を省略する。
【００１９】
図３は、図１のＩＣ素子１に用いられるリードフレームを示すもので、図７と同様の部分には同様の符号を付して詳細な説明を省略する。
【００２０】
リードフレームにおいて、支持部材２には、ＩＣを内蔵した半導体チップ３が固定される。半導体チップ３上の多数の電極（図示せず）は、５ａ，５ｂ等のボンディングワイヤを介して４ａ，４ｂ等のリードのインナーリード部にそれぞれ接続される。支持部材２、半導体チップ３、各リードのインナーリード部及び各ボンディングワイヤは、樹脂体６で上下から包囲された状態でモールド封止される。この後、リードフレームは、図３にてハッチングを施した部分が切断除去される。この場合、前述した図７の場合と異なる点は、４ａ，４ｂを含む多数のリード４のアウターリード部を接続に必要な長さを残してダムバー４ｄより短く切断したことである。各リードのアウターリード部には、Ａｇメッキが施されている。
【００２１】
このようにして製作されたＩＣ素子１は、図１に示すように保持部材２０の一主表面（取付面）に設けた素子孔２０Ａに固定される。保持部材２０は、一例として透明な樹脂を正方形状に成形したものであるが、図２において破線ａ〜ｄの個所で分割したものに相当する４つの部品を接着して構成してもよい。素子孔２０Ａは、樹脂体６のチップ３側の半分に順応した形状になっており、樹脂体６を素子孔２０Ａに挿入すると、４ａ，４ｂ等のリードのアウターリード部が素子孔２０Ａの周辺部に係止されると共に樹脂体６のチップ３側の面が保持部材２０の取付面とは反対側の面に露呈するようになっている。図１，２において、２０Ｅは、保持部材２０の取付面とは反対側の面における素子孔２０Ａの開口端を示す。ＩＣ素子１は、例えば樹脂体６の側面を素子孔２０Ａの側壁に接着するなどして固定される。
【００２２】
保持部材２０の取付面側において、素子孔２０Ａの周辺部には、図２に示すように２２ａ，２２ｂ等の２０個の導電層が保持部材２０の一辺当り５個ずつ設けられている。各導電層は、Ａｌ又はＣｕ等からなるもので、金属を被着してパターニングするか、金属ペーストを印刷するか又は配線付きのポリイミド樹脂等のテープを貼付するかして形成される。
【００２３】
２２ａ，２２ｂ等の導電層において、対応するリードのアウターリード部に近い端部には２４ａ，２４ｂ等のボンディングパッドが設けられている。４ａ，４ｂ等のリードのアウターリード部は、２６ａ，２６ｂ等のボンディングワイヤ（例えばＡｕワイヤ）により２４ａ，２４ｂ等のボンディングパッドにそれぞれ接続される。
【００２４】
保持部材２０と樹脂体６との間に形成される閉ループ状の凹部には、２６ａ，２６ｂ等のボンディングワイヤ及びその接続部を封止すべくポッティング等によりエポキシ樹脂を充填するなどして樹脂層３０が形成される。
【００２５】
２２ａ，２２ｂ等の導電層は、保持部材２０の端縁（又はその近傍）まで延長して形成される。２２ａ，２２ｂ等の導電層において、保持部材２０の端縁近傍部分には２８ａ，２８ｂ等の突起状の端子電極が設けられる。各端子電極は、Ａｕ、Ｃｕ又はＳｎ合金等のバンプ又はボールからなるものである。２８ａ，２８ｂ等の２０個の端子電極は、図２に示すように２２ａ，２２ｂ等の２０個の導電層にそれぞれ対応して保持部材２０の一辺当り５個ずつ配置されている。
【００２６】
上記した構成の半導体装置をプリント基板７に実装する際には、保持部材２０の取付面を下にしてプリント基板７の配線形成面に重ねる。このとき、２８ａ，２８ｂ等の端子電極が８ａ，８ｂ等の配線層にそれぞれ接触するように位置合わせを行なう。そして、熱処理により接触状態にある端子電極及び配線層を相互接続する。
【００２７】
上記した実施形態によれば、図３に示したように各リード４のアウターリード部をダムバー４ｄの位置より短く切断除去するので、リードピッチをエッチング加工可能な程度にまで狭くすることができ、例えば０．１２ｍｍにすることができる。従って、容易に多端子化を図ることができる。また、樹脂封止したＩＣ素子１を保持部材２０で保持するようにしたので、半導体チップ３等を上下の両面から封止することができ、樹脂体６のそりやはがれを抑制することができる。
【００２８】
保持部材２０の取付面側では、２８ａ，２８ｂ等の多数の突起状電極を先端位置を揃えて他の樹脂体６、樹脂層３０等の部分より突出させて形成したので、プリント基板７との間に適切な間隔を維持して取付けを行なうことができ、取付作業が簡単である。また、保持部材２０を透明材料で構成したので、位置合せ状態や接続状態を目視して確認することができる。
【００２９】
図４は、端子電極配置の変形例を示すもので、この例の端子電極配置の特徴は、より多くの端子を導出可能にするため、端子電極を千鳥足状に配置したことである。
【００３０】
すなわち、ＩＣ素子１を保持する保持部材２０の取付面において、保持部材２０の一辺の近傍部分には、端子電極Ｂ１ ，Ｂ３ ，Ｂ７ ，Ｂ９ の列と、端子電極Ｂ２ ，Ｂ４ ，Ｂ５ ，Ｂ６ ，Ｂ８ の列とが両列間で電極位置をずらすようにして並設されている。端子電極Ｂ１ 〜Ｂ９ は、いずれも図１の２８ａ，２８ｂと同様のもので、それぞれＩＣ素子１のリードＬ１ 〜Ｌ９ のアウターリード部とボンディングワイヤＰ、ボンディングパッドＱ及び導電層Ｒを介して接続される。
【００３１】
保持部材２０の他の三辺についても図４に関して上記したと同様の端子電極配置になっている。図４の例では、９×４＝３６個の端子を導出することができる。
【００３２】
図５は、この発明の他の実施形態を示すもので、この実施形態が図１のものと異なる点は、ＩＣ素子１における半導体チップ３とは反対側の面が保持部材２０の取付面より突出していることである。図５において、図１と同様の部分には、同様の符号を付してある。
【００３３】
保持部材２０の取付面において、素子孔２０Ａの周辺部には、２２ａ，２２ｂ等の多数の導電層がＩＣ素子１の４ａ，４ｂ等の多数のリードのアウターリード部にそれぞれ対応して配置されている。４ａ，４ｂ等の多数のリードのアウターリード部は、２６ａ，２６ｂ等のボンディングワイヤ及び２４ａ，２４ｂ等の多数のボンディングパッドを介して２２ａ，２２ｂ等の多数の導電層にそれぞれ接続される。
【００３４】
保持部材２０と樹脂体６との間に形成される閉ループ状の凹部には、２６ａ，２６ｂ等のボンディングワイヤ及びその接続部を封止すべくポッティング等にエポキシ樹脂を充填するなどして樹脂層３０が形成される。樹脂層３０は、保持部材２０の取付面に２４ａ，２４ｂ等のボンディングパッドを設けたことに伴って保持部材２０の取付面より突出している。
【００３５】
保持部材２０の取付面において、保持部材２０の端縁近傍には、２２ａ，２２ｂ等の多数の導電層にそれぞれ接続した状態で２８ａ，２８ｂ等の多数の突起状の端子電極が設けられる。
【００３６】
図５の半導体装置をプリント基板７に実装する際には、２８ａ，２８ｂ等の端子電極のサイズをできるだけ大きくする方法及び／又はプリント基板７の配線形成面に凹部７Ａを形成する方法を用いると、２８ａ，２８ｂ等の端子電極を８ａ，８ｂ等の配線層に確実に接続することができる。
【００３７】
保持部材２０としては、樹脂体６のチップ３側の面を全面的に露呈するものに限らず、一点鎖線２０Ｓで示すように樹脂体６のチップ３側の面を一部分だけ露呈するものや一点鎖線２０Ｓ及び破線２０Ｐで示すように樹脂体６のチップ３側の面をすべて覆うもの（この場合、素子孔２０Ａは凹部となる）を用いてもよい。また、ＩＣ素子１は、図示の状態とは上下を逆にして保持部材２０に装着することもできる。
【００３８】
この発明は、上記した実施形態に限定されるものではなく、種々の改変形態で実施可能である。例えば、次の（１）〜（３）のような変更が可能である。
【００３９】
（１）ＩＣ素子としては、５ａ，５ｂ等のボンディングワイヤを用いずにリードのインナーリード部に半導体チップ上の突起状電極をフェースダウンボンディングしたものを用いてもよい。
【００４０】
（２）４ａ，４ｂ等のリードのアウターリード部と２２ａ，２２ｂ等の導電層とは、２４ａ，２４ｂ等のボンディングパッドや２６ａ，２６ｂ等のボンディングワイヤを介さずに接続してもよい。このためには、例えば、導電層をアウターリード部まで延長して形成し、半田等でアウターリード部と接続すればよい。この場合、樹脂層３０を省略してもよい。
【００４１】
（３）２８ａ，２８ｂ等の端子電極を省略し、それらに相当する突起電極を実装基板側に設けてもよい。場合によっては、２２ａ，２２ｂ等の導電層と実装基板側の配線層とを突起電極なしに導電性接着剤等により接続してもよい。
【００４２】
【発明の効果】
以上のように、この発明によれば、各リードをダムバー位置より短く切断することによりリードピッチの減少を可能としたので、多端子化が容易となる効果が得られる。また、樹脂封止した半導体素子を保持部材で保持する構成にしたので、半導体チップやインナーリード部を上下の両面から封止することができ、樹脂体のそりやはがれを抑制できる利点もある。
【００４３】
その上、保持部材の取付面側で多数の突起状の端子電極を先端位置を揃えて他の部分より突出させて形成すると、実装基板への取付けが容易となる利点がある。
【００４４】
さらに、保持部材を透明材料で構成すると、実装基板上の接続状態を目視して確認できる利点がある。
【図面の簡単な説明】
【図１】この発明に係る半導体装置の取付状態を示す断面図である。
【図２】図１の装置の取付面を示す平面図である。
【図３】リードフレームの切断状況を示す平面図である。
【図４】端子電極配置の変形例を示す平面図である。
【図５】この発明の他の実施形態を示す断面図である。
【図６】従来のＩＣ素子の一例を示す断面図である。
【図７】従来のリードフレームの切断状況を示す平面図である。
【図８】従来のＩＣ素子の他の例を示す断面図である。
【符号の説明】
１：ＩＣ素子、２０：保持部材、２０Ａ：素子孔、２２ａ，２２ｂ，Ｒ：導電層、２４ａ，２４ｂ，Ｑ：ボンディングパッド、２６ａ，２６ｂ，Ｐ：ボンディングワイヤ、２８ａ，２８ｂ，Ｂ１ 〜Ｂ９ ：端子電極。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device provided with a semiconductor element such as a resin-sealed IC (integrated circuit) element or the like, and more particularly to fixing a resin-sealed semiconductor element to a hole or a recess provided in a holding member and leading out a terminal. Accordingly, the lead pitch can be reduced, and the number of terminals can be easily increased.
[0002]
[Prior art]
Conventionally, as a resin-sealed IC element, a QFP (Quad Flat
package) type is known.
[0003]
The IC element 1 is manufactured using a lead frame as shown in FIG. The semiconductor chip 3 having a built-in IC is fixed to a support member 2 called an island in a lead frame. A large number of leads 4 including 4a and 4b are respectively connected to a large number of electrodes (not shown) on the semiconductor chip 3 by bonding wires. For example, the leads 4a and 4b are connected to corresponding electrodes on the semiconductor chip 3 by bonding wires 5a and 5b, respectively.
[0004]
The support member 2, the semiconductor chip 3, the inner lead portions of the leads 4, and the bonding wires such as 5 a and 5 b are molded and sealed by the resin body 6. In FIG. 7, an alternate long and short dash line 6 </ b> A indicates an outline of the resin body 6.
[0005]
Thereafter, the hatched portion in FIG. 7 is cut and removed from the lead frame. At this time, the adjacent leads are electrically separated by cutting and removing the dam bar 4d that has prevented the resin from flowing out of the mold during the resin molding. The outer lead portion of each lead is appropriately bent to facilitate mounting.
[0006]
When mounting the IC element 1 on the printed circuit board 7, the outer lead portion of each lead is connected to a corresponding wiring layer by soldering or the like. For example, outer leads of the leads 4a and 4b are connected to the wiring layers 8a and 8b, respectively.
[0007]
FIG. 8 shows another example of a conventional IC element, and the element of this example is known as a BGA (Ball Grid Array).
[0008]
The IC element 10 includes a substrate 11 having a connection hole 11a. On the upper surface of the substrate 11, a semiconductor chip 13 containing an IC is fixed by an adhesive layer 12. On the substrate 11, a number of wiring layers such as 14a and 14b are formed corresponding to a number of electrodes (not shown) on the semiconductor chip 13, and these wiring layers are Are connected to the respective electrodes by bonding wires. For example, the wiring layers 14a and 14b are connected to corresponding electrodes on the semiconductor chip 13 by bonding wires 15a and 15b.
[0009]
On the surface of the substrate 11 on which the semiconductor chip 13 is fixed, a mold resin body 16 is provided. The resin body 16 seals the semiconductor chip 13, the bonding wires 15a and 15b, the connection portions of the wiring layers 14a and 14b, and the like.
[0010]
On the surface of the substrate 11 opposite to the surface to which the semiconductor chip 13 is fixed, a large number of terminal electrodes 17 such as solder bumps corresponding to wiring layers 14a and 14b to which bonding wires 15a and 15b are connected. Is provided. The wiring layers such as 14a and 14b are connected to the corresponding terminal electrodes 17 via connection holes such as 11a.
[0011]
When mounting the IC element 10 on a printed board, the terminal electrodes 17 are connected to wiring layers on the printed board, respectively.
[0012]
[Problems to be solved by the invention]
According to the IC element of FIG. 6, as shown in FIG. 7, there is a limit to the thickness of the blade to be cut when the dam bar 4d is cut and removed between the adjacent leads, and the distance between the center lines of the adjacent outer lead portions is limited. When the (lead pitch) became small (for example, 0.4 mm or less), it was not possible to separate adjacent outer lead portions. For this reason, the limit of separation is the limit of the lead pitch, and the increase in the number of terminals (the increase in the number of pins) has been restricted.
[0013]
On the other hand, according to the IC element shown in FIG. 8, although the wiring layers such as 14a and 14b can be formed by photolithography and selective etching technology, there is an advantage that the number of terminals can be easily increased. The sealing with the resin body 16 causes warpage of the substrate 11 due to the difference in the amount of heat shrinkage during molding. (B) The adhesive strength between the substrate 11 and the resin body 16 is weak, and the interface 11 is easily peeled off at the interface. ) Since the terminal electrode 17 is hidden by the substrate 11, there is a problem that the mounting state cannot be visually confirmed.
[0014]
An object of the present invention is to provide a novel semiconductor device which can solve these problems and can increase the number of terminals by reducing the lead pitch.
[0015]
[Means for Solving the Problems]
The semiconductor device according to the present invention includes:
A flat resin body electrically connecting a number of electrodes on a semiconductor chip to inner leads of a number of leads and having two flat surfaces facing the semiconductor chip and the inner leads of the plurality of leads, respectively. A semiconductor element having a configuration in which outer lead portions of the plurality of leads are linearly led out laterally from an intermediate position between the two flat surfaces at a side portion of the resin body,
A holding member for holding the semiconductor element, on one main surface being half of the resin body located on one flat surface side of the resin body from a lead-out position of an outer lead portion of the plurality of leads. A hole or a recess having an adapted shape is provided, and the outer lead portions of the plurality of leads are locked to the periphery of the hole or the recess on the one main surface side, and the half of the resin body is connected to the hole or the recess. The semiconductor element is fixed in a state of being inserted into the
A plurality of conductive layers formed on one main surface side of the holding member around the hole or the concave portion so as to correspond to the plurality of leads, respectively, and are electrically connected to outer lead portions of the corresponding leads. It is equipped with
[0016]
According to the configuration of the present invention, the resin-encapsulated semiconductor element is fixed to the hole or the recess provided in the holding member, and is mounted on a mounting board such as a printed board via a number of conductive layers provided around the hole or the recess. Is made, the outer lead portion of each lead may be short enough to allow electrical connection. For this reason, the outer lead portion of each lead can be cut shorter than the dam bar position after the resin mold, and there is no need to cut the dam bar so as to separate adjacent outer lead portions as in the related art. Therefore, the lead pitch can be reduced to the limit that can be processed by photolithography and selective etching technology, and it is easy to increase the number of terminals.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 shows a mounting state of a semiconductor device according to the present invention on a printed circuit board. FIG. 2 shows a mounting surface of the device. A section taken along line AA ′ of FIG. 2 corresponds to FIG.
[0018]
The IC element 1 has the same configuration as that described above with reference to FIG. 6 except for the cutting position of the outer lead portion of each lead, and the same portions as those in FIG. .
[0019]
FIG. 3 shows a lead frame used for the IC element 1 of FIG. 1, and the same parts as those of FIG. 7 are denoted by the same reference numerals, and detailed description will be omitted.
[0020]
In the lead frame, a semiconductor chip 3 containing an IC is fixed to the support member 2. A large number of electrodes (not shown) on the semiconductor chip 3 are connected to inner leads of leads 4a, 4b, etc., via bonding wires 5a, 5b, etc. The support member 2, the semiconductor chip 3, the inner lead portion of each lead, and each bonding wire are molded and sealed in a state of being surrounded by the resin body 6 from above and below. Thereafter, the portion of the lead frame hatched in FIG. 3 is cut and removed. In this case, the point different from the case of FIG. 7 described above is that the outer lead portions of a large number of leads 4 including 4a and 4b are cut shorter than the dam bar 4d, leaving a necessary length for connection. The outer lead portion of each lead is plated with Ag.
[0021]
The IC element 1 manufactured as described above is fixed to an element hole 20A provided on one main surface (mounting surface) of the holding member 20, as shown in FIG. As an example, the holding member 20 is formed by molding a transparent resin into a square shape, but it may be configured by bonding four parts corresponding to those divided at the portions indicated by broken lines a to d in FIG. The element hole 20A has a shape conforming to half of the resin body 6 on the chip 3 side, and when the resin body 6 is inserted into the element hole 20A, outer lead portions of the leads such as 4a and 4b are formed around the element hole 20A. The surface of the resin body 6 on the chip 3 side is exposed to the surface opposite to the mounting surface of the holding member 20. In FIGS. 1 and 2, reference numeral 20E denotes an opening end of the element hole 20A on the surface opposite to the mounting surface of the holding member 20. The IC element 1 is fixed, for example, by bonding the side surface of the resin body 6 to the side wall of the element hole 20A.
[0022]
On the mounting surface side of the holding member 20, around the element hole 20A, as shown in FIG. 2, 20 conductive layers such as 22a and 22b are provided five by one side of the holding member 20. Each conductive layer is made of Al or Cu or the like, and is formed by applying a metal and patterning, printing a metal paste, or attaching a tape such as a polyimide resin with wiring.
[0023]
In the conductive layers such as 22a and 22b, bonding pads such as 24a and 24b are provided at the ends near the outer leads of the corresponding leads. The outer lead portions of the leads 4a and 4b are connected to bonding pads 24a and 24b by bonding wires (for example, Au wires) such as 26a and 26b.
[0024]
The closed loop-shaped concave portion formed between the holding member 20 and the resin body 6 is filled with an epoxy resin by potting or the like so as to seal the bonding wires such as 26a and 26b and the connection portion thereof. 30 are formed.
[0025]
The conductive layers such as 22 a and 22 b are formed to extend to the edge of the holding member 20 (or the vicinity thereof). In the conductive layers such as 22a and 22b, protruding terminal electrodes such as 28a and 28b are provided near the edges of the holding member 20. Each terminal electrode is made of a bump or a ball of Au, Cu or Sn alloy or the like. As shown in FIG. 2, the twenty terminal electrodes 28a, 28b, etc. are arranged five by one per one side of the holding member 20, corresponding to the twenty conductive layers 22a, 22b, etc., respectively.
[0026]
When mounting the semiconductor device having the above-described configuration on the printed circuit board 7, the semiconductor device is overlaid on the wiring forming surface of the printed circuit board 7 with the mounting surface of the holding member 20 facing down. At this time, the positioning is performed so that the terminal electrodes such as 28a and 28b are in contact with the wiring layers such as 8a and 8b. Then, the terminal electrodes and the wiring layers in contact with each other are interconnected by heat treatment.
[0027]
According to the above-described embodiment, as shown in FIG. 3, the outer lead portion of each lead 4 is cut and removed shorter than the position of the dam bar 4d, so that the lead pitch can be reduced to an extent that can be etched. For example, it can be set to 0.12 mm. Therefore, the number of terminals can be easily increased. In addition, since the resin-sealed IC element 1 is held by the holding member 20, the semiconductor chip 3 and the like can be sealed from both upper and lower surfaces, and warpage or peeling of the resin body 6 can be suppressed. .
[0028]
On the mounting surface side of the holding member 20, a large number of projecting electrodes such as 28a and 28b are formed by aligning the end positions and protruding from the other resin body 6, the resin layer 30 and the like. Attachment can be performed while maintaining an appropriate interval therebetween, and the attachment operation is simple. In addition, since the holding member 20 is made of a transparent material, the alignment state and the connection state can be visually confirmed.
[0029]
FIG. 4 shows a modification of the terminal electrode arrangement. The feature of the terminal electrode arrangement in this example is that the terminal electrodes are arranged in a staggered manner so that more terminals can be led out.
[0030]
That is, on the mounting surface of the holding member 20 that holds the IC element 1, a row of the terminal electrodes B 1 , B 3 , B 7 , B 9 and the terminal electrodes B 2 , B 4, B 5, B and 6, columns of B 8 are juxtaposed so as to shift the electrode position between the two columns. Terminal electrodes B 1 .about.B 9 are both in FIG. 1 28a, similar to the 28b, the outer lead portions and bonding wires P of the lead L 1 ~L 9 of IC device 1, respectively, the bonding pads Q and the conductive layer R Connected via
[0031]
The other three sides of the holding member 20 have the same terminal electrode arrangement as described above with reference to FIG. In the example of FIG. 4, 9 × 4 = 36 terminals can be derived.
[0032]
FIG. 5 shows another embodiment of the present invention. This embodiment is different from that of FIG. 1 in that the surface of the IC element 1 on the side opposite to the semiconductor chip 3 is higher than the mounting surface of the holding member 20. It is protruding. In FIG. 5, the same parts as those in FIG. 1 are denoted by the same reference numerals.
[0033]
On the mounting surface of the holding member 20, on the periphery of the element hole 20A, a number of conductive layers such as 22a and 22b are arranged corresponding to outer leads of a number of leads such as 4a and 4b of the IC element 1, respectively. ing. Outer lead portions of a number of leads such as 4a and 4b are connected to a number of conductive layers such as 22a and 22b through bonding wires such as 26a and 26b and many bonding pads such as 24a and 24b.
[0034]
In a closed loop-shaped recess formed between the holding member 20 and the resin body 6, a resin layer is formed by filling a potting or the like with an epoxy resin to seal the bonding wires such as 26a and 26b and the connection portion thereof. 30 are formed. The resin layer 30 protrudes from the mounting surface of the holding member 20 with the provision of the bonding pads 24a, 24b and the like on the mounting surface of the holding member 20.
[0035]
On the mounting surface of the holding member 20, near the edge of the holding member 20, a number of projecting terminal electrodes 28a and 28b are provided in a state of being connected to a number of conductive layers such as 22a and 22b, respectively.
[0036]
When mounting the semiconductor device of FIG. 5 on the printed circuit board 7, a method of increasing the size of the terminal electrodes such as 28a and 28b as much as possible and / or a method of forming the recess 7A on the wiring forming surface of the printed circuit board 7 is used. , 28a, 28b and the like can be reliably connected to the wiring layers such as 8a, 8b.
[0037]
The holding member 20 is not limited to one that completely exposes the surface of the resin body 6 on the chip 3 side, one that partially exposes the surface of the resin body 6 on the chip 3 side as shown by a one-dot chain line 20S, or one point. As shown by a chain line 20S and a broken line 20P, a resin body 6 that entirely covers the surface of the resin body 6 on the chip 3 side (in this case, the element hole 20A becomes a concave portion) may be used. Further, the IC element 1 can be mounted on the holding member 20 with the upside down of the illustrated state.
[0038]
The present invention is not limited to the above embodiments, and can be implemented in various modified forms. For example, the following changes (1) to (3) are possible.
[0039]
(1) As an IC element, a device in which a protruding electrode on a semiconductor chip is face-down bonded to an inner lead portion of a lead without using a bonding wire such as 5a or 5b may be used.
[0040]
(2) The outer lead portions of the leads such as 4a and 4b may be connected to the conductive layers such as 22a and 22b without using bonding pads such as 24a and 24b or bonding wires such as 26a and 26b. For this purpose, for example, the conductive layer may be formed so as to extend to the outer lead portion, and connected to the outer lead portion with solder or the like. In this case, the resin layer 30 may be omitted.
[0041]
(3) The terminal electrodes such as 28a and 28b may be omitted, and the corresponding protruding electrodes may be provided on the mounting substrate side. In some cases, the conductive layers such as 22a and 22b and the wiring layer on the mounting substrate side may be connected by a conductive adhesive or the like without a protruding electrode.
[0042]
【The invention's effect】
As described above, according to the present invention, the lead pitch can be reduced by cutting each lead shorter than the position of the dam bar, so that the effect of easily increasing the number of terminals can be obtained. In addition, since the semiconductor element sealed with the resin is held by the holding member, the semiconductor chip and the inner lead portion can be sealed from both upper and lower surfaces, and there is an advantage that warpage or peeling of the resin body can be suppressed.
[0043]
In addition, when a large number of protruding terminal electrodes are formed on the mounting surface side of the holding member so as to protrude from other portions with the tip positions aligned, there is an advantage that the mounting to the mounting board becomes easy.
[0044]
Further, when the holding member is made of a transparent material, there is an advantage that the connection state on the mounting substrate can be visually confirmed.
[Brief description of the drawings]
FIG. 1 is a sectional view showing a mounting state of a semiconductor device according to the present invention.
FIG. 2 is a plan view showing a mounting surface of the device of FIG.
FIG. 3 is a plan view showing a cutting state of a lead frame.
FIG. 4 is a plan view showing a modification of the terminal electrode arrangement.
FIG. 5 is a sectional view showing another embodiment of the present invention.
FIG. 6 is a sectional view showing an example of a conventional IC element.
FIG. 7 is a plan view showing a cutting state of a conventional lead frame.
FIG. 8 is a cross-sectional view showing another example of a conventional IC element.
[Explanation of symbols]
1: IC element, 20: holding member, 20A: element hole, 22a, 22b, R: conductive layer, 24a, 24b, Q: bonding pad, 26a, 26b, P: bonding wire, 28a, 28b, B 1 to B 9 : Terminal electrode.

Claims (6)

半導体チップ上の多数の電極を多数のリードのインナーリード部にそれぞれ電気的に接続すると共に前記半導体チップ及び前記多数のリードのインナーリード部を互いに対向する２つのフラット面を有する偏平状の樹脂体で封止し、前記多数のリードのアウターリード部を前記樹脂体の側部において前記２つのフラット面の中間の位置から側方に直線的に導出した構成の半導体素子と、
この半導体素子を保持するための保持部材であって、一方の主表面には前記多数のリードのアウターリード部の導出位置から前記樹脂体の一方のフラット面側に位置する前記樹脂体の半分に順応した形状の孔又は凹部が設けられ、前記一方の主表面側で前記多数のリードのアウターリード部を前記孔又は凹部の周辺部に係止すると共に前記樹脂体の前記半分を前記孔又は凹部に挿入した状態で前記半導体素子が固定されたものと、
前記保持部材の一主表面側で前記孔又は凹部の周辺部に前記多数のリードにそれぞれ対応して形成された多数の導電層であって、対応するリードのアウターリード部に電気的に接続されたものと
を備えた半導体装置。 A flat resin body electrically connecting a number of electrodes on a semiconductor chip to inner leads of a number of leads and having two flat surfaces facing the semiconductor chip and the inner leads of the plurality of leads, respectively. A semiconductor element having a configuration in which outer lead portions of the plurality of leads are linearly led out laterally from an intermediate position between the two flat surfaces at a side portion of the resin body,
A holding member for holding the semiconductor element, on one main surface being half of the resin body located on one flat surface side of the resin body from a lead-out position of an outer lead portion of the plurality of leads. A hole or a recess having an adapted shape is provided, and the outer lead portions of the plurality of leads are locked to the periphery of the hole or the recess on the one main surface side, and the half of the resin body is connected to the hole or the recess. The semiconductor element is fixed in a state of being inserted into the
A plurality of conductive layers formed on one main surface side of the holding member around the hole or the concave portion so as to correspond to the plurality of leads, respectively, and are electrically connected to outer lead portions of the corresponding leads. A semiconductor device comprising: 前記保持部材の一主表面側で前記孔又は凹部の周辺部に前記多数の導電層にそれぞれ接続した状態で多数の突起状の端子電極を設けると共に、これらの端子電極を先端位置を揃えて前記保持部材の一主表面に垂直な方向に各端子電極以外の部分より突出させた請求項１記載の半導体装置。On the one main surface side of the holding member, a large number of protruding terminal electrodes are provided in a state of being connected to the large number of conductive layers on the periphery of the hole or the concave portion, respectively, and these terminal electrodes are aligned at the tip end positions. The semiconductor device according to claim 1, wherein the semiconductor device protrudes from a portion other than each terminal electrode in a direction perpendicular to one main surface of the holding member . 前記樹脂体の他方のフラット面が前記保持部材の一方の主表面より外方に突出している請求項１又は２記載の半導体装置。The semiconductor device according to claim 1, wherein the other flat surface of the resin body protrudes outward from one main surface of the holding member . 前記多数のリードのアウターリード部がいずれもリードフレームのダムバー位置より短く切断されている請求項１〜３のいずれかに記載の半導体装置。4. The semiconductor device according to claim 1, wherein outer lead portions of the plurality of leads are all cut shorter than a dam bar position of the lead frame. 5. 前記保持部材の一方の主表面側で前記孔又は凹部の周辺部が閉ループ状の凹部をなしており、この閉ループ状の凹部には前記多数の導電層と前記多数のリードのアウターリード部との電気的接続を覆うように樹脂層が形成されている請求項１〜４のいずれかに記載の半導体装置。A peripheral portion of the hole or the concave portion forms a closed loop-shaped concave portion on one main surface side of the holding member. The semiconductor device according to claim 1, wherein a resin layer is formed to cover the electrical connection. 前記保持部材を透明材料で構成した請求項１〜５のいずれかに記載の半導体装置。6. The semiconductor device according to claim 1, wherein said holding member is made of a transparent material.
JP27832895A 1995-10-02 1995-10-02 Semiconductor device Expired - Fee Related JP3603423B2 (en)

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JP3603423B2 true JP3603423B2 (en) 2004-12-22

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