JP3540918B2 - Method for manufacturing semiconductor device - Google Patents
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- JP3540918B2 JP3540918B2 JP23551597A JP23551597A JP3540918B2 JP 3540918 B2 JP3540918 B2 JP 3540918B2 JP 23551597 A JP23551597 A JP 23551597A JP 23551597 A JP23551597 A JP 23551597A JP 3540918 B2 JP3540918 B2 JP 3540918B2
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Description
【0001】
【発明の属する技術分野】
この発明は、半導体装置の製造方法に係るものであり、注入した不純物を活性化するためのアニール処理、特に、化合物半導体に注入した不純物活性化のための活性化アニールを基板表面に熱処理用保護膜を形成して行うキャップアニール処理に関する。
【0002】
【従来の技術】
電界効果トランジスタなどの半導体素子の活性層(チャネル層)などは、半導体基板に不純物をイオン注入して形成することが多いが、注入した不純物をキャリアとして機能させるには、注入不純物を所望の結晶格子位置に配置し、かつ注入時に生じた半導体基板の結晶欠陥を回復しなければならない。このため、従来より不純物注入層を機能させるために、活性化アニール処理と称される高温の熱処理が行われている。ところが、化合物半導体に対してこのような高温熱処理を直接施そうとした場合、化合物構成元素の物性の違い、即ち、解離圧力の差などにより、化合物半導体自身の組成バランスが失われてしまう。その結果、本来の目的である不純物の活性化が全く起こらないことになってしまう可能性がある。
【0003】
例えば、GaAs化合物半導体の場合、n型の活性層を得ようとする際には、通常、不純物としてSiをイオン注入し、Ga格子位置にSiイオンを配置させることになる。この際に必要な活性化アニール処理温度は850℃程度となる。ところが、GaAsを構成するGaとAsの平衡蒸気圧は、850℃にてそれぞれGa:1×10-7torr、As:1.5×10-6torrであり、As圧の方が約1桁高い。このため850℃の加熱を行うと、その際Asが、GaAs結晶表面から蒸散することになり、熱処理の後は、GaとAsのストイキオメトリ(化学量論組成)がズレてしまうという結果となる。これらの事情を回避する手法としては、瞬時アニール法や、構成元素の解離を防止するための熱処理用保護膜を基板表面に形成してアニールを行うキャップアニール法、又は解離性の強い構成元素(GaAsの場合As)の蒸気圧下で熱処理するキャップレスアニール法などが知られている。
【0004】
これらの内、キャップアニール法は、最も簡単な熱処理炉を用いて処理でき、広く採用されている。従来、このキャップアニール法で用いられる熱処理用保護膜の構成は、加熱時の基板変形を避けるため、表裏、つまり第1面及び第2面に同種類の膜を被覆させている。また、その膜材料としては、SiNが良いと考えられている。その理由としては、保護膜として採用される条件が次のようなものであり、SiN膜がこれらの条件の多くを満たしているからである。
【0005】
(i)高温でのアニール処理時に、基板結晶の表面から構成元素が蒸散するのを防止し、基板構成元素の外部拡散や保護膜中への拡散に対しても十分な障壁となること
(ii)保護膜と結晶界面が熱的に安定で、基板と反応したり、保護膜自身の結晶内部への散拡がないこと
(iii)半導体基板結晶に対する密着性がよく、保護膜にピンホールやクラックが発生しないこと
(iv)アニール後の保護膜の除去が容易であること
図3は、実際にSiN膜をGaAs基板に被覆した状態を示している。図3において、SiN膜の膜厚は1000Åとしている。この保護膜の膜厚は、保護膜として膜厚が厚ければ厚いほど信頼できるものとなるが、膜自身の耐熱性から1500Å程度が限界となる。図3に示すように、SiN膜は、基板の第1面及び第2面の両方に形成されている。これは、活性化アニール時には基板全体が加熱されるので第1面及び第2面の両方を保護するためである。
【0006】
このようにGaAs基板の表面をSiN膜で被覆して加熱処理を行うと、図4に示すように保護膜とGaAs結晶基板表面との間(界面)では、基板中のAsの解離圧を支える形で保護膜が作用する。このため、界面からのAsの脱離を抑えながら加熱処理できることになる。つまり、GaAs母体結晶のストイキオメトリが維持されることになり、母体結晶の崩壊を伴わずアニール処理を行うことが可能となる。
【0007】
【発明が解決しようとする課題】
しかしながら、デバイス設計上の理由などから、活性層を表面のごく近傍(浅い所)に形成しようとした場合、上述の方法では注入不純物の活性化能率が著しく低下することが知られている。
【0008】
この原因は、図5に示すように、第1面と第2面に同じSiN膜を形成していることにある。つまり、図3に示した構造で基板が加熱されると、第1面、第2面の保護膜内にそれぞれ生ずる熱応力が釣り合う形となり、GaAs基板の加熱変形が全く生じないことになる。その結果、加熱処理時に生じた熱応力は、全て基板表面と保護膜との界面をせん断する方向に集中してしまい、結果として、GaAs基板表面に熱応力が集中することとなる。このように界面に応力が生ずることで、GaAs基板の結晶内に欠陥が導入されてしまい、最終的に、不純物の所望の活性化が達成されなくなるのである。
【0009】
上記課題を解決するために、この発明は、半導体基板に注入された不純物を活性化するための活性化アニールの際に、熱処理用保護膜による基板表面への熱応力の集中を緩和する方法を提供することを目的とする。
【0010】
【課題を解決するための手段】
上記目的を達成するためにこの発明は、GaAs半導体基板に注入された不純物を活性化するための活性化アニールに先立ち、前記GaAs半導体基板の不純物注入層の形成面である第1面に熱処理用第1保護膜としてSiN膜を形成し、前記GaAs半導体基板の第2面に熱処理用第2保護膜としてAlN膜を形成し、その後前記活性化アニールを行う。
【0011】
この発明では、上記のように基板の表裏面である第1面、第2面に同種類の保護膜を成膜するのではなく、異なる種類の保護膜を第1面と第2面とに形成する。そして、第2面には基板と熱膨張係数の類似した材料を用いた保護膜を形成することで、半導体基板の変形を積極的に促し、熱応力の集中を軽減させる。
【0012】
特に、上述のGaAs基板のアニールキャップ方法における条件を満足する膜としては、SiN膜が有望である点を考慮し、第1面、例えば半導体素子の活性層などを形成するための不純物の注入層面側に、SiN膜を形成する。また基板の第2面には、GaAs基板の熱膨張係数に近い膨張係数を有する膜としてAlN膜を形成し、アニール時に、第1面側のSiN膜とGaAs表面とが密着して変形することを妨害しないようにする。
【0013】
このようにそれぞれ特性の異なる熱処理用保護膜を第1面及び第2面に形成することで、熱処理用保護膜と半導体基板(例えば、GaAs基板)の表面との密着構造による基板の熱変形が許容され、加熱処理中においても、その変形により、熱応力の集中を分散・軽減できる。従って、界面に働く応力を低下させて、基板表面からの結晶欠陥の導入を回避することが可能となる。結晶欠陥の導入が回避されることは、半導体素子の活性層などを基板の第1面の表層付近に構成しようとする場合などにおいて、特に有利となる。
【0014】
【発明の実施の形態】
以下、図面を用いてこの発明の好適な実施の形態(以下実施形態という)について説明する。
【0015】
図1は、この発明の実施形態に係る活性化アニール前の半導体基板の構成を示している。半導体基板、ここではGaAs基板10の第1面側には不純物(例えばSi)がイオン注入されて注入層16が形成されており、その第1面を覆うように熱処理用第1保護膜として1000Åの厚さにSiN膜12が形成されている。また、裏面である第2面側には熱処理用第2保護膜として1000Åの厚さにAlN膜14が形成されている。なお、これらの膜厚は、一例であって、必ずしも1000Åとする必要はない。
【0016】
第1面側の保護膜にSiN膜12を選択した理由は、SiN膜12がアニール時に化学的安定性に優れていることと、処理後の基板10からの剥離性が良いためである。また、第2面側の保護膜にAlN膜14を用いたのは、AlNの熱膨張係数がGaAs結晶のそれと類似しているためである。GaAsと、SiNであるSi3N4、AlNの各熱膨張係数は下記表1の通りである。GaAsの熱膨張係数6.8×10-6/℃に対し、Si3N4は3.2×10-6/℃、そしてAlNは6.1×10-6/℃であり、AlNの熱膨張係数は、GaAs母体結晶に非常に近い。このため、AlN膜14の形成された第2面側は、あたかも保護膜が無いかのように変形することが可能となる。
【0017】
【表1】
上記AlN膜14を第1面側の熱処理用保護膜として採用しなかったのは、膜の剥離性があまり良くないためである。剥離性が悪いと活性化アニールによって例えば注入層16が活性層となっても、アニール後に表面にAlN膜14が残存して、デバイス構造を構築しようとした際に不都合となるためである。
【0018】
図2は、図1に示したGaAs基板を加熱した際の基板の挙動を示している。実際にどのような変形が生じ、どの程度の界面の応力を軽減し得るかということについては、採用するSiN膜やAlN膜の特性・膜厚に繊細に依存するが、該略すると図2のようになると考えられる。第1面に形成されたSiN膜12は、熱膨張係数がGaAsと異なっているので、アニール時にSiN膜12とGaAs基板10との界面に応力が働き、これによりGaAs基板10は変形しようとする。従来のように第2面にも同じSiN膜が形成されていると、基板の変形が妨げられるが、この実施形態の場合には、第2面にGaAsと熱膨張係数の類似したAlN膜14が形成されている。よって、GaAs基板10の第1面と第2面とで生ずる応力は釣り合わず、またAlN膜14はGaAs基板10とほぼ同じように熱膨張する。従って、GaAs基板10は、AlN膜14の存在によって妨げられることなく図2のように変形できる。このため基板10の界面をせん断するような熱応力の集中が緩和される。
【0019】
実際に、アニール時におけるGaAs基板10がどのように変形するかは、実測する以外に手段がないが、850℃といった熱雰囲気で基板の変形を直接観察することは困難である。そこで、この実施形態の構成と従来の構成について、基板の変形が可能かどうかにより不純物活性化能率にどのような差が現れるかを評価してみた。
【0020】
この評価では、67KeVでSiを3×1012 atoms/cm-2注入したGaAsウェハー(厚み600μm)を用い、図3に示すような両面にSiN膜を形成して得たサンプル(従来型サンプル)と、図1に示すような第1面にSiN膜、第2面にAlN膜を形成したサンプル(本発明型サンプル)とを形成し、2種類のサンプルを同時にアニール加熱処理を施した。また、活性化能率の評価は、ホール効果測定によりキャリア総量を測定し、これとSiの注入総量との比を採って行っている。結果は、下記表2に示すようになっている。
【0021】
【表2】
従来型サンプルが活性化能率41%であるのに対し、本発明型サンプルでは45%の活性化能率が得られており、上述のように第2面に基板と熱膨張係数の類似した材料からなる熱処理用第2保護膜を形成することにより、活性化能率の向上が図られていることがわかる。また、第1面には化学的安定性と剥離性に優れた材料からなる熱処理用第1保護膜を形成する。この熱処理用第1保護膜として要求される条件を満たすような保護膜、例えばSiN膜を用いることでGaAsの界面が汚染されることがなく、GaAsのストイキオメトリを維持しながらアニール処理を行うことが可能となる。また、アニール後に半導体素子が形成される第1面の保護膜の剥離性が良いため、保護膜が一部残存するといった問題が防止され、半導体素子製造の上で有利となっている。
【0022】
【発明の効果】
以上、説明したようにこの発明によれば、同一種類の熱処理用保護膜を半導体基板の第1面と第2面に形成する従来のキャップアニール法に比して、本発明によるキャップアニール法の方が高い活性化能率が得られている。このように高い活性化能率が得られれば、活性化能率に見合った注入量の再調整を行うことで、不純物の注入総量を低減でき、また活性化に寄与しないSiの残留量も小さく抑えられる。よって、アニール後に得られるキャリアとしてのモビリティーも高い状態で得られることになる。そして、このような活性化アニールによって形成された活性層を用いてMESFET(Metal Semiconductor 電界効果トランジスタ)などの素子を形成した半導体装置では、その動作速度をより高速とすることが可能となる。
【図面の簡単な説明】
【図1】本発明の実施形態に係る熱処理用保護膜で被覆したGaAs基板を示す図である。
【図2】本発明の実施形態に係る熱処理用保護膜で被覆した場合の界面応力軽減機構を示す概念図である。
【図3】GaAs基板の両面をSiN膜で被覆した従来のGaAs基板を示す図である。
【図4】850℃熱雰囲気中における従来のGaAs基板の表面を説明する図である。
【図5】加熱中に従来のGaAs基板の界面に働く膜応力を説明する図である。
【符号の説明】
10 GaAs基板、12 SiN膜、14 AlN膜、16 注入層。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, in which an annealing process for activating an implanted impurity, in particular, an activation anneal for activating an impurity implanted in a compound semiconductor is protected on a substrate surface for heat treatment. The present invention relates to cap annealing performed by forming a film.
[0002]
[Prior art]
The active layer (channel layer) of a semiconductor element such as a field-effect transistor is often formed by ion-implanting an impurity into a semiconductor substrate. It must be placed at the lattice position and must recover crystal defects of the semiconductor substrate generated at the time of implantation. Therefore, a high-temperature heat treatment called an activation annealing treatment has been conventionally performed in order to make the impurity injection layer function. However, when the compound semiconductor is subjected to such a high-temperature heat treatment directly, the composition balance of the compound semiconductor itself is lost due to a difference in physical properties of the compound constituent elements, that is, a difference in dissociation pressure. As a result, there is a possibility that activation of impurities, which is the original purpose, does not occur at all.
[0003]
For example, in the case of a GaAs compound semiconductor, when obtaining an n-type active layer, usually, Si is ion-implanted as an impurity, and Si ions are arranged at the position of the Ga lattice. At this time, the necessary activation annealing temperature is about 850 ° C. However, the equilibrium vapor pressures of Ga and As constituting GaAs are Ga: 1 × 10 −7 torr and As: 1.5 × 10 −6 torr at 850 ° C., respectively, and the As pressure is about one digit. high. For this reason, when heating at 850 ° C., As evaporates from the GaAs crystal surface at that time, and after the heat treatment, the stoichiometry (stoichiometric composition) of Ga and As is shifted. Become. As a method for avoiding these circumstances, an instantaneous annealing method, a cap annealing method in which a heat treatment protective film for preventing dissociation of constituent elements is formed on the substrate surface and annealing is performed, or a constituent element having strong dissociation ( In the case of GaAs, a capless annealing method of performing heat treatment under the vapor pressure of As) is known.
[0004]
Of these, the cap annealing method can be processed using the simplest heat treatment furnace and is widely adopted. Conventionally, in the configuration of the heat treatment protective film used in the cap annealing method, the same type of film is coated on the front and back surfaces, that is, the first surface and the second surface, in order to avoid deformation of the substrate during heating. It is considered that SiN is good as the film material. The reason is that the conditions adopted as the protective film are as follows, and the SiN film satisfies many of these conditions.
[0005]
(I) During annealing at a high temperature, the constituent elements are prevented from evaporating from the surface of the substrate crystal, and serve as a sufficient barrier against external diffusion of the substrate constituent elements and diffusion into the protective film (ii). ) The interface between the protective film and the crystal is thermally stable and does not react with the substrate and does not spread inside the crystal of the protective film itself. (Iii) The adhesion to the semiconductor substrate crystal is good, No cracks occur (iv) Easy removal of protective film after annealing FIG. 3 shows a state in which a GaAs substrate is actually covered with a SiN film. In FIG. 3, the thickness of the SiN film is 1000 °. The thickness of the protective film becomes more reliable as the thickness of the protective film increases, but the limit is about 1500 ° due to the heat resistance of the film itself. As shown in FIG. 3, the SiN film is formed on both the first surface and the second surface of the substrate. This is to protect both the first surface and the second surface since the entire substrate is heated during the activation annealing.
[0006]
When the surface of the GaAs substrate is covered with the SiN film and subjected to the heat treatment, the dissociation pressure of As in the substrate is supported between the protective film and the surface of the GaAs crystal substrate (interface) as shown in FIG. The protective film acts in the form. Therefore, so that the desorption of As from the interface can be heated treatment while suppression e. That is, the stoichiometry of the GaAs host crystal is maintained, and the annealing process can be performed without the host crystal being collapsed.
[0007]
[Problems to be solved by the invention]
However, when the active layer is formed very close to the surface (shallow place) for reasons such as device design, it is known that the activation efficiency of the implanted impurity is significantly reduced by the above-described method.
[0008]
This is because the same SiN film is formed on the first surface and the second surface as shown in FIG. That is, when the substrate is heated with the structure shown in FIG. 3, the thermal stresses generated in the protective films on the first surface and the second surface are balanced, and the GaAs substrate is not deformed by heating at all. As a result, all the thermal stresses generated during the heat treatment concentrate in the direction of shearing the interface between the substrate surface and the protective film, and as a result, the thermal stress concentrates on the GaAs substrate surface. When the stress is generated at the interface as described above, a defect is introduced into the crystal of the GaAs substrate, and finally, the desired activation of the impurity cannot be achieved.
[0009]
In order to solve the above problems, the present invention provides a method for reducing the concentration of thermal stress on the substrate surface by a heat treatment protective film during activation annealing for activating impurities implanted in a semiconductor substrate. The purpose is to provide.
[0010]
[Means for Solving the Problems]
The invention to achieve the above object, prior to the activation annealing process for activating the impurities implanted into the GaAs semiconductor substrate, the thermal the first surface is a forming surface impurity doped layer of the GaAs semiconductor substrate the SiN film is formed as the first protective layer, wherein the AlN layer is formed as the second protective film heat-treating the second surface of the GaAs semiconductor substrate, performing then the activation annealing.
[0011]
In the present invention, instead of forming the same type of protective film on the first and second surfaces which are the front and back surfaces of the substrate as described above, different types of protective films are formed on the first and second surfaces. Form. By forming a protective film using a material having a similar thermal expansion coefficient to that of the substrate on the second surface, the semiconductor substrate is positively deformed and the concentration of thermal stress is reduced.
[0012]
In particular, the film satisfying the conditions in the annealing cap method of the GaAs substrate mentioned above, and consideration SiN film is promising, a first surface, for example, implantation of an impurity for forming the like active layer of the semiconductor element An SiN film is formed on the layer surface side. On the second surface of the substrate, an AlN film is formed as a film having an expansion coefficient close to the thermal expansion coefficient of the GaAs substrate. During annealing, the SiN film on the first surface and the GaAs surface are closely adhered and deformed. Not to disturb.
[0013]
By forming the heat treatment protective films having different characteristics on the first surface and the second surface in this manner, thermal deformation of the substrate due to the close contact structure between the heat treatment protective film and the surface of the semiconductor substrate (for example, a GaAs substrate) is prevented. It is permissible and even during the heat treatment, the concentration of the thermal stress can be dispersed and reduced by the deformation. Therefore, it is possible to reduce the stress acting on the interface and avoid the introduction of crystal defects from the substrate surface. Avoiding the introduction of crystal defects is particularly advantageous when an active layer or the like of a semiconductor element is to be formed near the surface layer on the first surface of the substrate.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, preferred embodiments of the present invention (hereinafter, referred to as embodiments) will be described with reference to the drawings.
[0015]
FIG. 1 shows a configuration of a semiconductor substrate before activation annealing according to an embodiment of the present invention. An impurity (for example, Si) is ion-implanted on the first surface side of the semiconductor substrate, here, the GaAs substrate 10 to form an implantation layer 16, and a first protective film for heat treatment of 1000 覆 う is formed so as to cover the first surface. The thickness of the SiN film 12 is formed. An AlN film 14 having a thickness of 1000 と し て is formed as a second heat treatment protective film on the second surface, which is the back surface. Note that these film thicknesses are merely examples and need not necessarily be 1000 °.
[0016]
The reason for selecting the SiN film 12 as the protective film on the first surface side is that the SiN film 12 has excellent chemical stability at the time of annealing and has good releasability from the substrate 10 after processing. The reason why the AlN film 14 is used as the protective film on the second surface side is that AlN has a thermal expansion coefficient similar to that of the GaAs crystal. Table 1 below shows the respective thermal expansion coefficients of GaAs and SiN, ie, Si 3 N 4 and AlN. The thermal expansion coefficient of GaAs is 6.8 × 10 −6 / ° C., whereas that of Si 3 N 4 is 3.2 × 10 −6 / ° C. and that of AlN is 6.1 × 10 −6 / ° C. The expansion coefficient is very close to that of the GaAs host crystal. For this reason, the second surface on which the AlN film 14 is formed can be deformed as if there is no protective film.
[0017]
[Table 1]
The reason that the AlN film 14 was not employed as the heat-treating protective film on the first surface side is that the peelability of the film is not so good. This is because if the releasability is poor, the AlN film 14 remains on the surface after annealing, for example, even if the injection layer 16 becomes an active layer due to activation annealing, which is inconvenient when constructing a device structure.
[0018]
FIG. 2 shows the behavior of the GaAs substrate shown in FIG. 1 when the substrate is heated. Actually what kind of deformation occurs and how much the stress at the interface can be reduced depends delicately on the characteristics and film thickness of the SiN film or AlN film to be adopted. It is thought to be. Since the thermal expansion coefficient of the SiN film 12 formed on the first surface is different from that of GaAs, stress acts on the interface between the SiN film 12 and the GaAs substrate 10 during annealing, and the GaAs substrate 10 tends to deform. . If the same SiN film is formed on the second surface as in the prior art, the deformation of the substrate is hindered. In this embodiment, however, the AlN film 14 having a similar thermal expansion coefficient to that of GaAs is formed on the second surface. Is formed. Therefore, the stresses generated on the first surface and the second surface of the GaAs substrate 10 are not balanced, and the AlN film 14 thermally expands in substantially the same manner as the GaAs substrate 10. Therefore, the GaAs substrate 10 can be deformed as shown in FIG. 2 without being hindered by the presence of the AlN film 14. For this reason, concentration of thermal stress that shears the interface of the substrate 10 is reduced.
[0019]
Actually, there is no other way than actually measuring how the GaAs substrate 10 is deformed during annealing, but it is difficult to directly observe the deformation of the substrate in a hot atmosphere such as 850 ° C. Therefore, the difference between the configuration of this embodiment and the configuration of the related art in the impurity activation efficiency depending on whether the substrate was deformable was evaluated.
[0020]
In this evaluation, a sample (conventional sample) obtained by forming a SiN film on both sides as shown in FIG. 3 using a GaAs wafer (thickness: 600 μm) implanted with 3 × 10 12 atoms / cm −2 of Si at 67 KeV. Then, as shown in FIG. 1, a sample having an SiN film on the first surface and an AlN film on the second surface (a sample of the present invention) was formed, and the two types of samples were subjected to annealing heat treatment at the same time. In addition, the evaluation of the activation efficiency is performed by measuring the total amount of carriers by measuring the Hall effect and taking the ratio of this to the total amount of injected Si. The results are as shown in Table 2 below.
[0021]
[Table 2]
The conventional sample has an activation efficiency of 41%, while the sample of the present invention has an activation efficiency of 45%. As described above, the second surface is made of a material having a similar thermal expansion coefficient to that of the substrate. It can be seen that the activation efficiency is improved by forming the second heat treatment second protective film. Further, a first protective film for heat treatment made of a material having excellent chemical stability and releasability is formed on the first surface. By using a protective film that satisfies the conditions required as the first protective film for heat treatment, for example, a SiN film, the interface of GaAs is not contaminated , and the annealing treatment is performed while maintaining the stoichiometry of GaAs. It is possible to do. Further, since a good peelability of the protective film of the first surface on which semiconductor elements are formed after annealing, the protective film is prevented a problem remains part, becomes advantageous in a semiconductor device fabrication.
[0022]
【The invention's effect】
As described above, according to the present invention, the cap annealing method according to the present invention is more effective than the conventional cap annealing method in which the same type of heat treatment protective film is formed on the first surface and the second surface of the semiconductor substrate. The higher activation efficiency is obtained. If such a high activation efficiency can be obtained, the injection amount can be readjusted in accordance with the activation efficiency, whereby the total amount of impurity implantation can be reduced, and the residual amount of Si that does not contribute to activation can be reduced. . Therefore, the mobility as a carrier obtained after annealing can be obtained in a high state. In a semiconductor device in which an element such as a MESFET (Metal Semiconductor field effect transistor) is formed using an active layer formed by such activation annealing, the operation speed can be further increased.
[Brief description of the drawings]
FIG. 1 is a view showing a GaAs substrate covered with a protective film for heat treatment according to an embodiment of the present invention.
FIG. 2 is a conceptual diagram showing an interfacial stress reducing mechanism when covered with a heat treatment protective film according to an embodiment of the present invention.
FIG. 3 is a diagram showing a conventional GaAs substrate in which both surfaces of a GaAs substrate are covered with SiN films.
FIG. 4 is a diagram illustrating the surface of a conventional GaAs substrate in a hot atmosphere at 850 ° C.
FIG. 5 is a diagram illustrating film stress acting on the interface of a conventional GaAs substrate during heating.
[Explanation of symbols]
10 GaAs substrate, 12 SiN film, 14 AlN film, 16 injection layer.
Claims (1)
前記GaAs半導体基板の不純物注入層の形成面である第1面に熱処理用第1保護膜としてSiN膜を形成し、前記GaAs半導体基板の第2面に熱処理用第2保護膜としてAlN膜を形成し、
その後前記活性化アニールを行う半導体装置の製造方法。Prior to activation annealing for activating the impurities implanted in the GaAs semiconductor substrate,
An SiN film is formed as a first heat treatment protective film on a first surface of the GaAs semiconductor substrate on which an impurity implantation layer is formed, and an AlN film is formed on a second surface of the GaAs semiconductor substrate as a second heat treatment protective film. And
A method of manufacturing a semiconductor device, wherein the activation annealing is performed thereafter.
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