JP3491904B2 - Manufacturing method of liquid crystal display device - Google Patents
Manufacturing method of liquid crystal display deviceInfo
- Publication number
- JP3491904B2 JP3491904B2 JP3523692A JP3523692A JP3491904B2 JP 3491904 B2 JP3491904 B2 JP 3491904B2 JP 3523692 A JP3523692 A JP 3523692A JP 3523692 A JP3523692 A JP 3523692A JP 3491904 B2 JP3491904 B2 JP 3491904B2
- Authority
- JP
- Japan
- Prior art keywords
- data line
- connection hole
- insulating film
- conductive layer
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Description
【発明の詳細な説明】
【０００１】
【産業上の利用分野】本発明は液晶表示装置に関し、特
に、その表示品質の向上技術に関する。
【０００２】
【従来の技術】液晶表示装置においては、画素信号を供
給するデ−タ線および走査信号を伝達するゲ−ト線が格
子状に配置されており各画素領域が区画形成された一方
側の透明絶縁基板と共通電極が形成された他方側の透明
絶縁基板との間に液晶が封入されており、共通電極と各
画素領域の画素電極との間に印加される電位を制御し
て、画素領域毎の液晶の配向状態を変化させるようにな
っている。このため、各画素領域から構成されたマトリ
クスアレイの一般的な構造は、垂直方向のデ−タ線と、
水平方向のゲ−ト線とによって区画形成された画素領域
にデ−タ線が導通接続するソ−スおよびゲ−ト線が導通
接続するゲ−トを有するＴＦＴが構成されており、その
ドレインには、それらの表面側に形成されたシリコン酸
化膜からなる層間絶縁膜の接続孔を介して画素電極が導
通接続している。
【０００３】従来の液晶表示装置においては、デ−タ線
も画素電極と同一の層間絶縁膜上に形成されて、その接
続孔を介してソ−スに導通接続しているため、デ−タ線
と画素電極とデ−タ線とが短絡しやすい構造である。
（図２に従来の構造であるデ−タ線と画素電極が同一の
層間絶縁膜上に形成されている場合の構造断面図を示
す）従って、それらを絶縁分離しておくためには、画素
電極の端部とデ−タ線との間に所定の間隔を確保する必
要があり、その間隔に相当して、画素電極の形成領域が
狭くなり、開口率が低減するという問題がある。この問
題を解決する方法として、デ−タ線と画素電極とを異な
る絶縁膜上に形成すれば良い。これは、下層側層間絶縁
膜の第１の接続孔を介して導通接続するデ−タ線と、下
層側層間絶縁膜の第２の接続孔を介して導通接続する積
み上げ電極層とを同一材料で形成し、この積み上げ電極
層に上層層間絶縁膜の接続孔を介して端部がデ−タ線の
上方に位置する画素電極が導通接続する構造である。
（図３に画素電極とデ−タ線とを別層に形成した場合の
構造断面図を示す。）従って、デ−タ線と画素電極とは
互いに別層に形成されているため短絡する危険性がない
ので、デ−タ線の上方位置にまで画素電極の端部を配置
することができるため、開口率が増加し、表示品質が向
上する。
【０００４】
【発明が解決しようとする課題】しかし、デ−タ線およ
び積み上げ電極層に低抵抗のＡｌを使用すると、画素電
極のＩＴＯ膜との接続抵抗が高く、不安定なために表示
品質低下の原因となる。また、画素電極のＩＴＯ膜をウ
ェットエッチングによりパタ−ニングする場合、塩酸系
の溶液を用いるため、画素電極の端部がデ−タ線の上方
位置に配置されているこの構造においては、上層側層間
絶縁膜の欠陥（ピンホ−ル）からエッチング液がしみこ
みデ−タ線の断線を引き起こし、歩留り低下の原因にも
なる。
【０００５】従って、本発明の課題は、前述の画素電極
と積み上げ電極層の接続抵抗の低減と、ＩＴＯ膜のエッ
チング液によるデ−タ線の断線防止が可能な構造とする
ことにより、表示品質向上可能な液晶表示装置を実現す
ることにある。
【０００６】
【課題を解決するための手段】本発明は、薄膜トランジ
スタのソース・ドレイン領域となるシリコン層上に、ゲ
ート絶縁膜を介してゲート電極を形成し、前記ゲート電
極上に第１層間絶縁膜を形成し、前記第１層間絶縁膜の
前記ソース領域上に第１の接続孔を、前記ドレイン領域
上に第２の接続孔を形成し、前記ソース領域及び前記ド
レイン領域に接続されるように第１導電層を形成し、前
記第１導電層上に第２導電層を連続して形成し、前記第
１導電層と前記第２導電層を同時にパターニングして前
記ソース領域に接続されるデータ線と前記ドレイン領域
に接続される積み上げ電極層とを形成し、前記積み上げ
電極層上に第２層間絶縁膜を形成し、前記第２の接続孔
と平面的に重ならないように前記第２層間絶縁膜に第３
の接続孔を形成し、前記第３の接続孔を介し、ＩＴＯ膜
をウェットエッチングすることによりパターニングし
て、前記積み上げ電極層に接続されるようにＩＴＯから
なる画素電極を形成し、前記第２導電層は、前記第１導
電層とは異なる材料で形成するとともに前記画素電極と
の接続抵抗が低く、前記第２導電層は、ＭｏＳｉ ２ 、Ｔ
ｉＳｉ ２ 、ＷＳｉ ２ 、ＴａＳｉ ２ 、Ｔｉ、Ｗ、Ｔａ、Ｔ
ｉＮのうちのいずれかの材料からなり、ＩＴＯのエッチ
ング液に溶解しない材料で形成され、前記画素電極の端
部が、前記データ線の上方に位置することを特徴とす
る。
【０００７】
【作用】本発明の液晶表示装置において、前記第１のデ
−タ線及び第１の積み上げ電極層は低抵抗で、ソ−ス・
ドレインとオ−ミックコンタクト可能なアルミニウムの
ような材料を用いた上に前記第２のデ−タ線と前記第２
の積み上げ電極層は、画素電極のＩＴＯとの接続抵抗が
良好でかつＩＴＯのエッチング液に溶解されない材料を
用いていることによって、画素電極ＩＴＯと積み上げ電
極層との接続抵抗は低減され良好な表示品質を得ること
ができ、またデ−タ線もＩＴＯのエッチング液から保護
されるためデ−タ線の断線を防止することが可能であ
る。
【０００８】
【実施例】次に本発明の一実施例について添付図面を参
照して説明する。図１は本発明の実施例の液晶表示装置
における画素領域の構造断面図を示したものである。
【０００９】この画素領域には、第１のデ−タ線１３お
よび第２のデ−タ線１４が導通接続するソ−ス２、ゲ−
ト線が導通接続するゲ−ト７、および画素電極１８が第
１の積み上げ電極層１５および第２の積み上げ電極層１
６を介して導通接続するドレイン３によって、ＴＦＴ８
が形成されている。このＴＦＴの断面構造は、液晶表示
装置全体を支持する絶縁透明基板１の表面側に多結晶シ
リコン層４が形成されており、この多結晶シリコンに
は、真性の多結晶シリコン領域であるチャネル領域５を
除いて、ｎ型の不純物としてリンが導入されて（ｐ型を
形成する場合はボロン）、ソ−ス２およびドレイン３が
形成されている。ここでリンの導入は、多結晶シリコン
層４の表面側に形成されたゲ−ト酸化膜６上のゲ−ト７
をマスクとするイオン注入を利用することにより、ソ−
ス２およびドレイン３がセルフアラインとなるように行
われる。このＴＦＴ８の表面側には、シリコン酸化膜か
らなる第１の層間絶縁膜９が堆積されており、それには
第１の接続孔１１と第２の接続孔１２とが開口されてい
る。そのうち第１の接続孔を介して、アルミニウム層か
らなる第１のデ−タ線１３がソ−ス２に導通接続されて
いる。その第１のデ−タ線１３上に多層配線構造として
ＭｏＳｉ2層を堆積し、デ−タ線１３と同様にパタ−ニン
グあるいは被覆するようにパタ−ニングし、第２のデ−
タ線１４を形成する。一方、第２の接続孔を介して、第
１のデ−タ線１３と同一材料のアルミニウム層からなる
第１の積み上げ電極層１５がドレイン３に導通接続して
いる。更にその第１の積み上げ電極層１５上に多層配線
構造として、第２のデ−タ線１４と同一材料を用いて堆
積し、第１の積み上げ電極層１５と同様にパタ−ニング
あるいは被覆するようにパタ−ニングし、第２の積み上
げ電極層１６を形成する。この構造において、スル−プ
ット向上のため第１のデ−タ線１３と第１の積み上げ電
極層１５は同一材料（アルミニウム等）および第２のデ
−タ線１４と第２の積み上げ電極層１６も同一材料とす
ることが望ましい。更に第１の導電層（デ−タ線、積み
上げ電極層）と第２の導電層（デ−タ線、積み上げ電極
層）を連続工程で堆積し、エッチングも連続で行うとス
ル−プットが向上する。特に第２のデ−タ線１４と第２
の積み上げ電極層１６は画素電極ＩＴＯ１８との接続抵
抗が低く、ＩＴＯのエッチンク液に溶解しない材料が望
ましく、本実施例ではＭｏＳｉ2膜を使用したがＴｉＳｉ
2、ＷＳｉ2、ＴａＳｉ2、Ｔｉ、Ｗ、Ｔａ、ＴｉＮ等を用
いても同様な結果が得られる。
【００１０】従って、本液晶表示装置において、上記の
構造を用いることにより画素電極ＩＴＯとの接続抵抗が
低減し、デ−タ線の断線を防止することができるため表
示品質を向上させることが可能である。
【００１１】上述の実施例の液晶表示装置において前記
のとおり、下層側層間絶縁膜上に形成された、多層配線
構造のデータ線と同一材料を用いた画素電極と導通接続
している多層構造の積み上げ電極層が形成されているた
ことにより、以下の効果を奏する。
【００１２】従来画素電極ＩＴＯと導通接続していた
積み上げ電極層であるアルミニウム層上に新たにコンタ
クトメタルを形成することによって、積み上げ電極層を
多層構造とし、ＩＴＯとの接続抵抗を低減させることに
より表示品質を向上させることができる。
【００１３】デ−タ線も前記積み上げ電極層と同一構
造として、デ−タ線の２層目のデ−タ線はＩＴＯのエッ
チング液に溶解しない材料を使用し、上層側層間絶縁膜
の欠陥よりＩＴＯのエッチング液が染み込んでもデ−タ
線が断線するようなことがないため歩留まり向上に非常
に有効な手段である。
【００１４】デ−タ線が上層側層間絶縁膜によって埋
め込まれている構造のため、デ−タ線の電界の影響が少
なく、それによって液晶の配向を乱すことがないので表
示品質が向上する。
【００１５】
【発明の効果】本発明は上記構成要件を具備することに
より、以下に述べる如き顕著な効果を奏することができ
る。
（１）積み上げ電極の第１及び第２導電層を連続して堆
積し、同時にパターニングしているため電極層の成膜及
びフォト・エッチング工程を増加させずに多層の積み上
げ電極を形成することができる。
（２）データ線と画素電極を異なる面上に配置するの
で、同一平面上に配置する時に発生する画素電極とデー
タ線の短絡発生をなくすことが可能となり、また画素電
極とデータ線との間に所定の間隔を確保する必要がなく
なるので、開口率をより大きくすることが可能となる。
（３）ソース・ドレイン領域上の積み上げ電極を多層構
造の電極とするため多種の材料を効果的に組み合わせる
ことが可能となる。例えば、積み上げ電極の上層側の導
電層を画素電極のＩＴＯとの接続抵抗が小さい材質を選
ぶことにより良好な接続を可能とすることができる。ま
た、積み上げ電極の上層側を画素電極のエッチング液に
溶解しない材料とすると、積み上げ電極の上に形成され
ている第２層間絶縁膜の欠陥よるＩＴＯのエッチング液
の染み込みによる影響から電極を保護することができ
る。
（４）第２の接続孔と第３の接続孔を重ならないように
配置するので、第３の接続孔を積み上げ電極上の平坦性
のより良い位置に配置することが可能となり、積み上げ
電極と画素電極との接続品質を向上させることができ
る。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a technique for improving the display quality of a liquid crystal display device. 2. Description of the Related Art In a liquid crystal display device, a data line for supplying a pixel signal and a gate line for transmitting a scanning signal are arranged in a grid pattern, and each pixel region is defined. Liquid crystal is sealed between the transparent insulating substrate on one side and the transparent insulating substrate on the other side on which the common electrode is formed, and controls the potential applied between the common electrode and the pixel electrode in each pixel region. In addition, the alignment state of the liquid crystal in each pixel region is changed. For this reason, the general structure of a matrix array composed of each pixel area is composed of vertical data lines and
A source having a data line conductively connected to a pixel region defined by a horizontal gate line and a TFT having a gate having a gate line conductively connected thereto are formed. , The pixel electrodes are conductively connected via connection holes of an interlayer insulating film made of a silicon oxide film formed on the surface side. In the conventional liquid crystal display device, the data line is also formed on the same interlayer insulating film as the pixel electrode, and is electrically connected to the source through the connection hole. In this structure, lines, pixel electrodes, and data lines are easily short-circuited.
(FIG. 2 shows a cross-sectional view of a conventional structure in which a data line and a pixel electrode are formed on the same interlayer insulating film.) Therefore, in order to insulate and separate them, a pixel is required. It is necessary to secure a predetermined interval between the end of the electrode and the data line, and there is a problem that the area where the pixel electrode is formed becomes narrower and the aperture ratio is reduced corresponding to the interval. To solve this problem, the data lines and the pixel electrodes may be formed on different insulating films. This is because the data line electrically connected via the first connection hole of the lower interlayer insulating film and the stacked electrode layer electrically connected via the second connection hole of the lower interlayer insulating film are made of the same material. The pixel electrode whose end is located above the data line is conductively connected to the stacked electrode layer through a connection hole of the upper interlayer insulating film.
(FIG. 3 is a cross-sectional view showing a structure in which the pixel electrode and the data line are formed in different layers.) Therefore, the data line and the pixel electrode are formed in different layers, and thus there is a risk of short-circuit. Since there is no characteristic, the end of the pixel electrode can be arranged up to the position above the data line, so that the aperture ratio is increased and the display quality is improved. However, when low-resistance Al is used for the data line and the stacked electrode layer, the connection resistance between the pixel electrode and the ITO film is high, and the display quality is unstable. It causes a decline. Further, when the ITO film of the pixel electrode is patterned by wet etching, a hydrochloric acid-based solution is used. Therefore, in this structure in which the edge of the pixel electrode is arranged above the data line, The etchant infiltrates from a defect (pinhole) in the interlayer insulating film, causing a disconnection of the data line, which causes a reduction in yield. Accordingly, an object of the present invention is to reduce the connection resistance between the above-mentioned pixel electrode and the stacked electrode layer and to prevent a data line from being broken by an etching solution for an ITO film, thereby achieving display quality. An object of the present invention is to provide a liquid crystal display device that can be improved. According to the present invention, a gate electrode is formed on a silicon layer serving as a source / drain region of a thin film transistor via a gate insulating film, and a first interlayer insulating film is formed on the gate electrode. A film is formed, a first connection hole is formed on the source region of the first interlayer insulating film, and a second connection hole is formed on the drain region, so that the first connection hole is connected to the source region and the drain region. Forming a first conductive layer on the first conductive layer, continuously forming a second conductive layer on the first conductive layer, and simultaneously patterning the first conductive layer and the second conductive layer to be connected to the source region Forming a stacked electrode layer connected to the data line and the drain region, forming a second interlayer insulating film on the stacked electrode layer, and forming the second interlayer insulating film on the stacked electrode layer so as not to overlap the second connection hole in a plane; Third for interlayer insulating film
The connection hole is formed, and via the third connection hole, ITO film
Is patterned by wet etching
From ITO so as to be connected to the stacked electrode layer
The composed pixel electrode is formed, the second conductive layer, the low connection resistance between the pixel electrode and forming a different material than the first conductive <br/> conductive layer, the second conductive layer, MoSi 2 , T
iSi 2, WSi 2, TaSi 2 , Ti, W, Ta, T
made of any material of iN, it is formed of a material which does not dissolve in the etching solution ITO, an end of the pixel electrode
A portion is located above the data line . In the liquid crystal display device of the present invention, the first data line and the first stacked electrode layer have low resistance and have a low resistance.
A material such as aluminum capable of ohmic contact with the drain is used, and the second data line and the second
The stacked electrode layer is made of a material that has a good connection resistance between the pixel electrode and the ITO and is not dissolved in the etching solution of the ITO, so that the connection resistance between the pixel electrode ITO and the stacked electrode layer is reduced, resulting in a good display. Quality can be obtained, and the data lines are protected from the ITO etching solution, so that disconnection of the data lines can be prevented. Next, an embodiment of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a sectional view showing the structure of a pixel region in a liquid crystal display device according to an embodiment of the present invention. In this pixel area, a source 2 and a gate, to which a first data line 13 and a second data line 14 are electrically connected, are provided.
The gate 7 to which the gate line is conductively connected and the pixel electrode 18 are composed of the first stacked electrode layer 15 and the second stacked electrode layer 1.
The TFT 8 is electrically connected to the drain 3 through the TFT 8.
Is formed. The cross-sectional structure of this TFT is such that a polycrystalline silicon layer 4 is formed on the surface side of an insulating transparent substrate 1 that supports the entire liquid crystal display device. This polycrystalline silicon has a channel region that is an intrinsic polycrystalline silicon region. With the exception of 5, phosphorus is introduced as an n-type impurity (boron in the case of forming a p-type), so that a source 2 and a drain 3 are formed. Here, the introduction of phosphorus is performed by the gate 7 on the gate oxide film 6 formed on the surface side of the polycrystalline silicon layer 4.
By using ion implantation with the mask as a mask,
This is performed so that the source 2 and the drain 3 are self-aligned. A first interlayer insulating film 9 made of a silicon oxide film is deposited on the front side of the TFT 8, and a first connection hole 11 and a second connection hole 12 are opened in the first interlayer insulating film 9. The first data line 13 made of an aluminum layer is conductively connected to the source 2 through the first connection hole. A MoSi 2 layer is deposited on the first data line 13 as a multilayer wiring structure, and patterned or covered in the same manner as the data line 13 to form a second data line.
Forming a grid line 14; On the other hand, a first stacked electrode layer 15 made of the same aluminum layer as the first data line 13 is electrically connected to the drain 3 through the second connection hole. Further, a multilayer wiring structure is formed on the first stacked electrode layer 15 by using the same material as the second data line 14, and is patterned or covered in the same manner as the first stacked electrode layer 15. And a second stacked electrode layer 16 is formed. In this structure, the first data line 13 and the first stacked electrode layer 15 are made of the same material (aluminum or the like) and the second data line 14 and the second stacked electrode layer 16 for improving the throughput. It is desirable that the same material be used. Further, the first conductive layer (data line, stacked electrode layer) and the second conductive layer (data line, stacked electrode layer) are deposited in a continuous process, and the throughput is improved by continuously performing the etching. I do. In particular, the second data line 14 and the second
The stacked electrode layer 16 is preferably made of a material that has a low connection resistance with the pixel electrode ITO 18 and does not dissolve in the etching liquid of ITO. In this embodiment, the MoSi 2 film is used.
2, WSi 2, TaSi 2, Ti, W, Ta, similar results were also using TiN or the like is obtained. Therefore, in the present liquid crystal display device, by using the above structure, the connection resistance with the pixel electrode ITO can be reduced, and the disconnection of the data line can be prevented, so that the display quality can be improved. It is. In the liquid crystal display device of the above-described embodiment, as described above, the multi-layer structure having the same material as the data lines of the multi-layer wiring structure and formed on the lower interlayer insulating film and electrically connected to the pixel electrodes is used. The following effects are obtained by forming the stacked electrode layers. By newly forming a contact metal on the aluminum layer which is a stacked electrode layer which has been conductively connected to the pixel electrode ITO, the stacked electrode layer has a multi-layer structure to reduce the connection resistance with ITO. The display quality can be improved. The data line also has the same structure as the above-mentioned stacked electrode layer. The second data line of the data line uses a material which does not dissolve in the etching solution of ITO, and has a defect in the upper interlayer insulating film. This is a very effective means for improving the yield because the data line does not break even if the ITO etching solution permeates. Since the data lines are buried by the upper interlayer insulating film, the influence of the electric field of the data lines is small, and the alignment of the liquid crystal is not disturbed, so that the display quality is improved. According to the present invention, by satisfying the above constitutional requirements, the following remarkable effects can be obtained. (1) Since the first and second conductive layers of the stacked electrode are successively deposited and patterned at the same time, it is possible to form a multilayer stacked electrode without increasing the film formation of the electrode layer and the photo-etching process. it can. (2) Since the data line and the pixel electrode are arranged on different planes, it is possible to eliminate the occurrence of a short circuit between the pixel electrode and the data line that occurs when the data line and the pixel electrode are arranged on the same plane. Therefore, it is not necessary to secure a predetermined interval, so that the aperture ratio can be further increased. (3) Since the stacked electrodes on the source / drain regions are electrodes having a multilayer structure, various materials can be effectively combined. For example, a good connection can be made possible by selecting a material having a low connection resistance with the ITO of the pixel electrode for the conductive layer on the upper layer side of the stacked electrode. When the upper layer side of the stacked electrode is made of a material that does not dissolve in the etching solution of the pixel electrode, the electrode is protected from the influence of the penetration of the etching solution of ITO due to the defect of the second interlayer insulating film formed on the stacked electrode. be able to. (4) Since the second connection hole and the third connection hole are arranged so as not to overlap with each other, it is possible to arrange the third connection hole at a position with better flatness on the stacked electrodes, and the stacked connection electrodes and The connection quality with the pixel electrode can be improved.
【図面の簡単な説明】
【図１】本発明の一実施例を説明する図。
【図２】従来の液晶表示装置におけるマトリクスアレイ
の断面図その１。
【図３】従来の液晶表示装置におけるマトリクスアレイ
の断面図その２。
【符号の説明】
１ 透明絶縁基板
２ ソ−ス
３ ドレイン
４ 多結晶シリコン膜
５ チャネル
６ ゲ−ト酸化膜
７ ゲ−ト電極
８ ＴＦＴ
９ 下層側層間絶縁膜
１０ 上層側層間絶縁膜
１１ 接続孔１
１２ 接続孔２
１３ 第１のデ−タ線
１４ 第２のデ−タ線
１５ 第１の積み上げ電極層
１６ 第２の積み上げ電極層
１７ 接続孔
１８ 画素電極BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram illustrating an embodiment of the present invention. FIG. 2 is a sectional view 1 of a matrix array in a conventional liquid crystal display device. FIG. 3 is a second sectional view of a matrix array in a conventional liquid crystal display device. DESCRIPTION OF SYMBOLS 1 Transparent insulating substrate 2 Source 3 Drain 4 Polycrystalline silicon film 5 Channel 6 Gate oxide film 7 Gate electrode 8 TFT 9 Lower interlayer insulating film 10 Upper interlayer insulating film 11 Connection hole DESCRIPTION OF SYMBOLS 1 12 Connection hole 2 13 First data line 14 Second data line 15 First stacked electrode layer 16 Second stacked electrode layer 17 Connection hole 18 Pixel electrode
Claims (1)
域となるシリコン層上に、ゲート絶縁膜を介してゲート
電極を形成し、前記ゲート電極上に第１層間絶縁膜を形
成し、前記第１層間絶縁膜の前記ソース領域上に第１の
接続孔を、前記ドレイン領域上に第２の接続孔を形成
し、前記ソース領域及び前記ドレイン領域に接続される
ように第１導電層を形成し、前記第１導電層上に第２導
電層を連続して形成し、前記第１導電層と前記第２導電
層を同時にパターニングして前記ソース領域に接続され
るデータ線と前記ドレイン領域に接続される積み上げ電
極層とを形成し、前記積み上げ電極層上に第２層間絶縁
膜を形成し、前記第２の接続孔と平面的に重ならないよ
うに前記第２層間絶縁膜に第３の接続孔を形成し、前記
第３の接続孔を介し、ＩＴＯ膜をウェットエッチングす
ることによりパターニングして、前記積み上げ電極層に
接続されるようにＩＴＯからなる画素電極を形成し、前
記第２導電層は、前記第１導電層とは異なる材料で形成
するとともに前記画素電極との接続抵抗が低く、前記第
２導電層は、ＭｏＳｉ ２ 、ＴｉＳｉ ２ 、ＷＳｉ ２ 、Ｔａ
Ｓｉ ２ 、Ｔｉ、Ｗ、Ｔａ、ＴｉＮのうちのいずれかの材
料からなり、ＩＴＯのエッチング液に溶解しない材料で
形成され、前記画素電極の端部が、前記データ線の上方
に位置することを特徴とする液晶表示装置の製造方法。(57) Claims 1. A gate electrode is formed on a silicon layer serving as a source / drain region of a thin film transistor via a gate insulating film, and a first interlayer insulating film is formed on the gate electrode. Forming a first connection hole on the source region of the first interlayer insulating film, forming a second connection hole on the drain region, and connecting the first connection hole to the source region and the drain region. A data line connected to the source region by forming one conductive layer, continuously forming a second conductive layer on the first conductive layer, and patterning the first conductive layer and the second conductive layer simultaneously; And a stacked electrode layer connected to the drain region, a second interlayer insulating film is formed on the stacked electrode layer, and the second interlayer insulating film is formed so as not to overlap the second connection hole in a plane. Forming a third connection hole in the film, And through the third connection hole, to wet etching an ITO film
The pixel with patterned by Rukoto, the pixel electrode made of ITO is formed so as to be connected to a stacked electrode layer, the second conductive layer is formed of a different material than the first conductive layer low connection resistance between the electrode, the first
The two conductive layers are MoSi 2 , TiSi 2 , WSi 2 , Ta
Any material of Si 2 , Ti, W, Ta, TiN
Made of a material that does not dissolve in the ITO etching solution, and the end of the pixel electrode is located above the data line.
A method for manufacturing a liquid crystal display device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3523692A JP3491904B2 (en) | 1992-02-21 | 1992-02-21 | Manufacturing method of liquid crystal display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3523692A JP3491904B2 (en) | 1992-02-21 | 1992-02-21 | Manufacturing method of liquid crystal display device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2003317928A Division JP3622757B2 (en) | 2003-09-10 | 2003-09-10 | Liquid crystal display |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05235360A JPH05235360A (en) | 1993-09-10 |
| JP3491904B2 true JP3491904B2 (en) | 2004-02-03 |
Family
ID=12436211
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3523692A Expired - Lifetime JP3491904B2 (en) | 1992-02-21 | 1992-02-21 | Manufacturing method of liquid crystal display device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3491904B2 (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3587537B2 (en) | 1992-12-09 | 2004-11-10 | 株式会社半導体エネルギー研究所 | Semiconductor device |
| US6798023B1 (en) | 1993-12-02 | 2004-09-28 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device comprising first insulating film, second insulating film comprising organic resin on the first insulating film, and pixel electrode over the second insulating film |
| US6906383B1 (en) * | 1994-07-14 | 2005-06-14 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of manufacture thereof |
| JP3646311B2 (en) * | 1996-02-09 | 2005-05-11 | セイコーエプソン株式会社 | Multilayer wiring contact structure, active matrix substrate, and manufacturing method thereof |
| JP2850850B2 (en) * | 1996-05-16 | 1999-01-27 | 日本電気株式会社 | Method for manufacturing semiconductor device |
| KR100509221B1 (en) * | 1997-03-31 | 2005-12-09 | 세이코 엡슨 가부시키가이샤 | Display |
| TW531684B (en) | 1997-03-31 | 2003-05-11 | Seiko Epson Corporatoin | Display device and method for manufacturing the same |
| TW451447B (en) * | 1999-12-31 | 2001-08-21 | Samsung Electronics Co Ltd | Contact structures of wirings and methods for manufacturing the same, and thin film transistor array panels including the same and methods for manufacturing the same |
| JP4055764B2 (en) | 2004-01-26 | 2008-03-05 | セイコーエプソン株式会社 | Electro-optical device and electronic apparatus |
| KR101198127B1 (en) | 2005-09-30 | 2012-11-12 | 엘지디스플레이 주식회사 | LCD and Method of fabricating of the same |
| JP2006216936A (en) * | 2005-12-16 | 2006-08-17 | Mitsubishi Electric Corp | Liquid crystal display device, manufacturing method thereof the same and tft array substrate used therefor |
-
1992
- 1992-02-21 JP JP3523692A patent/JP3491904B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05235360A (en) | 1993-09-10 |
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