JP3478206B2 - Method for manufacturing field emission electron source - Google Patents

Method for manufacturing field emission electron source

Info

Publication number
JP3478206B2
JP3478206B2 JP29595799A JP29595799A JP3478206B2 JP 3478206 B2 JP3478206 B2 JP 3478206B2 JP 29595799 A JP29595799 A JP 29595799A JP 29595799 A JP29595799 A JP 29595799A JP 3478206 B2 JP3478206 B2 JP 3478206B2
Authority
JP
Japan
Prior art keywords
electric field
surface electrode
strong electric
layer
drift layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP29595799A
Other languages
Japanese (ja)
Other versions
JP2001118499A (en
Inventor
勉 櫟原
卓哉 菰田
浩一 相澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP29595799A priority Critical patent/JP3478206B2/en
Publication of JP2001118499A publication Critical patent/JP2001118499A/en
Application granted granted Critical
Publication of JP3478206B2 publication Critical patent/JP3478206B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、電界放射型電子源
の製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a field emission electron source.

【0002】[0002]

【従来の技術】本願発明者らは、多孔質多結晶半導体層
(例えば、多孔質化された多結晶シリコン層<ポーラス
ポリシリコン層>)を急速熱酸化(RTO)技術によっ
て急速熱酸化することによって、導電性基板と金属薄膜
(表面電極)との間に介在し導電性基板から注入された
電子がドリフトする強電界ドリフト層を形成した電界放
射型電子源を提案している。
2. Description of the Related Art The inventors of the present invention rapidly oxidize a porous polycrystalline semiconductor layer (for example, a porous polycrystalline silicon layer <porous polysilicon layer>) by a rapid thermal oxidation (RTO) technique. Proposes a field emission electron source in which a strong electric field drift layer, which is interposed between a conductive substrate and a metal thin film (surface electrode) and in which electrons injected from the conductive substrate drift, is formed.

【0003】この電界放射型電子源10’は、例えば、
図3に示すように、導電性基板たるn形シリコン基板1
の主表面側に酸化した多孔質多結晶シリコン層よりなる
強電界ドリフト層6が形成され、強電界ドリフト層6上
に金属薄膜よりなる表面電極7が形成され、n形シリコ
ン基板1の裏面にオーミック電極2が形成されている。
This field emission electron source 10 'is, for example,
As shown in FIG. 3, an n-type silicon substrate 1 which is a conductive substrate
A strong electric field drift layer 6 made of an oxidized porous polycrystalline silicon layer is formed on the main surface side of, and a surface electrode 7 made of a metal thin film is formed on the strong electric field drift layer 6, and the back surface of the n-type silicon substrate 1 is The ohmic electrode 2 is formed.

【0004】図3に示す構成の電界放射型電子源10’
では、図4に示すように、表面電極7を真空中に配置す
るとともに表面電極7に対向してコレクタ電極21を配
置し、表面電極7をn形シリコン基板1(オーミック電
極2)に対して正極として直流電圧Vpsを印加するとと
もに、コレクタ電極21を表面電極7に対して正極とし
て直流電圧Vcを印加することにより、n形シリコン基
板1から注入された電子が強電界ドリフト層6をドリフ
トし表面電極7を通して放出される(なお、図4中の一
点鎖線は表面電極7を通して放出された電子e-の流れ
を示す)。したがって、表面電極7としては、仕事関数
の小さな材料を用いることが望ましい。ここにおいて、
表面電極7とオーミック電極2との間に流れる電流をダ
イオード電流Ipsと称し、コレクタ電極21と表面電極
7との間に流れる電流を放出電子電流Ieと称し、ダイ
オード電流Ipsに対する放出電子電流Ieが大きい(Ie
/Ipsが大きい)ほど電子放出効率が高くなる。なお、
この電界放射型電子源10’では、表面電極7とオーミ
ック電極2との間に印加する直流電圧Vpsを10〜20
V程度の低電圧としても電子を放出させることができ
る。
A field emission type electron source 10 'having the structure shown in FIG.
Then, as shown in FIG. 4, the surface electrode 7 is arranged in a vacuum, and the collector electrode 21 is arranged so as to face the surface electrode 7, and the surface electrode 7 is arranged with respect to the n-type silicon substrate 1 (ohmic electrode 2). Electrons injected from the n-type silicon substrate 1 drift in the strong electric field drift layer 6 by applying the DC voltage Vps as the positive electrode and applying the DC voltage Vc as the positive electrode to the surface electrode 7 with the collector electrode 21. The electrons are emitted through the surface electrode 7 (note that the alternate long and short dash line in FIG. 4 shows the flow of the electrons e emitted through the surface electrode 7). Therefore, it is desirable to use a material having a small work function for the surface electrode 7. put it here,
The current flowing between the surface electrode 7 and the ohmic electrode 2 is referred to as a diode current Ips, and the current flowing between the collector electrode 21 and the surface electrode 7 is referred to as an emission electron current Ie. Big (Ie
/ Ips is larger), the higher the electron emission efficiency. In addition,
In this field emission electron source 10 ', the DC voltage Vps applied between the surface electrode 7 and the ohmic electrode 2 is 10 to 20.
Electrons can be emitted even at a low voltage of about V.

【0005】この電界放射型電子源10’では、電子放
出特性の真空度依存性が小さく且つ電子放出時にポッピ
ング現象が発生せず安定して電子を高い電子放出効率で
放出することができる。ここにおいて、強電界ドリフト
層6は、図5に示すように、少なくとも、柱状の多結晶
シリコン51(グレイン)と、多結晶シリコン51の表
面に形成された薄いシリコン酸化膜52と、多結晶シリ
コン51間に介在するナノメータオーダの微結晶シリコ
ン層63と、微結晶シリコン層63の表面に形成され当
該微結晶シリコン層63の結晶粒径よりも小さな膜厚の
絶縁層であるシリコン酸化膜64とから構成されると考
えられる。
In the field emission type electron source 10 ', the vacuum degree dependence of the electron emission characteristic is small, and the popping phenomenon does not occur during electron emission, and electrons can be emitted stably with high electron emission efficiency. Here, the strong electric field drift layer 6 is, as shown in FIG. 5, at least a columnar polycrystalline silicon 51 (grain), a thin silicon oxide film 52 formed on the surface of the polycrystalline silicon 51, and the polycrystalline silicon 51. A nanometer-order microcrystalline silicon layer 63 interposed between 51 and a silicon oxide film 64, which is an insulating layer formed on the surface of the microcrystalline silicon layer 63 and having a film thickness smaller than the crystal grain size of the microcrystalline silicon layer 63. It is considered to be composed of

【0006】すなわち、強電界ドリフト層6は、各グレ
インの表面が多孔質化し各グレインの中心部分では結晶
状態が維持されていると考えられる。したがって、強電
界ドリフト層6に印加された電界はほとんどシリコン酸
化膜64にかかるから、注入された電子はシリコン酸化
膜64にかかっている強電界により加速され多結晶シリ
コン51間を表面に向かって図5中の矢印Aの向きへ
(図5中の上方向へ向かって)ドリフトするので、電子
放出効率を向上させることができる。なお、強電界ドリ
フト層6の表面に到達した電子はホットエレクトロンで
あると考えられ、表面電極7を容易にトンネルし真空中
に放出される。なお、表面電極7の膜厚は10nmない
し15nm程度に設定されている。
That is, in the strong electric field drift layer 6, it is considered that the surface of each grain is made porous and the crystalline state is maintained in the central portion of each grain. Therefore, most of the electric field applied to the strong electric field drift layer 6 is applied to the silicon oxide film 64, so that the injected electrons are accelerated by the strong electric field applied to the silicon oxide film 64 and are directed toward the surface between the polycrystalline silicon 51. Since it drifts in the direction of arrow A in FIG. 5 (upward in FIG. 5), the electron emission efficiency can be improved. The electrons that have reached the surface of the strong electric field drift layer 6 are considered to be hot electrons, and easily tunnel through the surface electrode 7 and are emitted into a vacuum. The thickness of the surface electrode 7 is set to about 10 nm to 15 nm.

【0007】[0007]

【発明が解決しようとする課題】ところで、上記の構成
において、絶縁層たるシリコン酸化膜64にかかる電界
によるドリフトで電子を加速して放出させる場合、シリ
コン酸化膜64の欠陥により効率が低下する、或いは絶
縁耐圧が低下するという問題があった。一方急速昇温酸
化法(RTO)等でシリコン酸化膜64を形成した場
合、ストレス等の原因により微結晶シリコン層63とシ
リコン酸化膜64との界面やシリコン酸化膜に多くの欠
陥を生じることになり、上記の効率低下は免れなかっ
た。
By the way, in the above structure, when electrons are accelerated and emitted by the drift due to the electric field applied to the silicon oxide film 64 which is the insulating layer, the efficiency is lowered due to the defect of the silicon oxide film 64. Alternatively, there is a problem that the withstand voltage decreases. On the other hand, when the silicon oxide film 64 is formed by the rapid temperature rising oxidation method (RTO) or the like, many defects are caused in the interface between the microcrystalline silicon layer 63 and the silicon oxide film 64 or in the silicon oxide film due to stress or the like. As a result, the above decrease in efficiency was inevitable.

【0008】本発明は上記の問題点に鑑みて為されたも
のであり、その目的とするところは、電子放出効率を向
上させ、且つ電気的耐圧も向上させることができる電界
放射型電子源の製造方法を提供することにある。
The present invention has been made in view of the above problems, and an object thereof is to provide a field emission type electron source capable of improving electron emission efficiency and electric withstand voltage. It is to provide a manufacturing method.

【0009】[0009]

【課題を解決するための手段】上記目的を達成するため
に、請求項1の発明では、導電性基板と、該導電性基板
の表面側に形成された多孔質半導体層よりなる強電界ド
リフト層と、該強電界ドリフト層上に形成された表面電
極とを備え、該表面電極を上記導電性基板に対して高電
位側として電圧を印加することにより上記導電性基板か
ら注入された電子が上記強電界ドリフト層をドリフトし
上記表面電極を通して放出される電界放射型電子源の製
造方法において、上記強電界ドリフト層上に触媒作用を
持つ材料により上記表面電極を形成し、該表面電極を形
成した後、高温、酸素雰囲気中で上記表面電極の触媒作
用により上記強電界ドリフト層の酸化膜からなる絶縁層
の酸化膜質改善処理を施すことを特徴とする
In order to achieve the above object, the invention of claim 1 provides a conductive substrate and the conductive substrate.
A strong electric field drift layer made of a porous semiconductor layer formed on the surface side of the electric field and a surface electrode formed on the strong electric field drift layer, and the surface electrode is set to a high potential side with respect to the conductive substrate. In the method of manufacturing a field emission electron source in which electrons injected from the conductive substrate by applying a voltage drift in the strong electric field drift layer and are emitted through the surface electrode, a catalytic action is exerted on the strong electric field drift layer. the surface electrode is formed of a material having a, after forming the surface electrodes, high temperature, in an oxygen atmosphere by the catalytic action of the surface electrode oxide film quality improvement process of the insulating layer made of an oxide film of the strong electric field drift layer It is characterized by applying .

【0010】 請求項2の発明では、導電性基板と、該
導電性基板の表面側に形成された多孔質半導体層よりな
る強電界ドリフト層と、該強電界ドリフト層上に形成さ
れた表面電極とを備え、該表面電極を上記導電性基板に
対して高電位側として電圧を印加することにより上記導
電性基板から注入された電子が上記強電界ドリフト層を
ドリフトし上記表面電極を通して放出される電界放射型
電子源の製造方法において、上記多孔質半導体層の表面
に触媒作用を持つ材料により上記表面電極を形成し、該
表面電極を形成した後、高温、酸素雰囲気中で上記表面
電極の触媒作用により上記多孔質半導体層を酸化して上
記強電界ドリフト層を形成し、更に該強電界ドリフト層
に形成された酸化膜からなる絶縁層の上記表面電極の触
媒作用で該絶縁層の酸化膜質改善処理を施すことを特徴
とする。
According to the invention of claim 2, a conductive substrate,
A strong electric field drift layer formed of a porous semiconductor layer formed on the surface side of the conductive substrate and a surface electrode formed on the strong electric field drift layer are provided, and the surface electrode is higher than the conductive substrate. Electrons injected from the conductive substrate by applying a voltage on the potential side drift in the strong electric field drift layer and are emitted through the surface electrode. a material having a catalytic action on the surface to form the surface electrode, after forming the surface electrodes, the high temperature, the strong electric field drift layer by oxidizing the porous semiconductor layer by the catalytic action of the surface electrode in an oxygen atmosphere And further the strong electric field drift layer
And characterized by applying an oxidation film quality improvement process of the insulating layer in the catalysis of the insulating layer above table surface electrode consisting of a formed oxide film.

【0011】請求項3の発明では、請求項1又は2の発
明において、上記絶縁層をシリコン酸化膜により形成し
たことを特徴とする。
A third aspect of the invention is characterized in that, in the first or second aspect of the invention, the insulating layer is formed of a silicon oxide film.

【0012】請求項4の発明では、請求項1乃至3の何
れかの発明において、上記表面電極をPtにより形成し
たことを特徴とする。
The invention of claim 4 is characterized in that, in any of the inventions of claims 1 to 3, the surface electrode is formed of Pt.

【0013】請求項5の発明では、請求項1乃至4の何
れかの発明において、上記強電界ドリフト層を多孔質多
結晶シリコン層により形成したことを特徴とする。
A fifth aspect of the invention is characterized in that, in any one of the first to fourth aspects of the invention, the strong electric field drift layer is formed of a porous polycrystalline silicon layer.

【0014】[0014]

【発明の実施の形態】以下本発明を実施形態により説明
する。
BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described below with reference to embodiments.

【0015】(実施形態1)本実施形態は、請求項1の
発明に対応する実施形態であって、図1はその製造プロ
セスの概略構成を示す。
(Embodiment 1) This embodiment is an embodiment corresponding to the invention of claim 1, and FIG. 1 shows a schematic configuration of a manufacturing process thereof.

【0016】本実施形態の製造方法で得られる電界放射
型電子源10の構成は、上述した電界放射型電子源1
0’の構成と基本的に同じであって、導電性基板たるn
形シリコン基板1の主表面側に酸化した多孔質多結晶シ
リコン層<ポーラスポリシリコン層>よりなる強電界ド
リフト層6が形成され、強電界ドリフト層6上に金属薄
膜よりなる表面電極7が形成され、n形シリコン基板1
の裏面にオーミック電極2が形成されている。
The structure of the field emission electron source 10 obtained by the manufacturing method of this embodiment is the same as the field emission electron source 1 described above.
The structure is basically the same as that of 0 ', and n is a conductive substrate.
A strong electric field drift layer 6 made of an oxidized porous polycrystalline silicon layer <porous polysilicon layer> is formed on the main surface side of the shaped silicon substrate 1, and a surface electrode 7 made of a metal thin film is formed on the strong electric field drift layer 6. N-type silicon substrate 1
The ohmic electrode 2 is formed on the back surface of the.

【0017】以下、製造方法について図1を参照しなが
ら説明する。
The manufacturing method will be described below with reference to FIG.

【0018】まず、n形シリコン基板1の裏面にオーミ
ック電極2を形成した後、n形シリコン基板1の表面に
所定膜厚(例えば、1.5μm)の半導体層たるノンド
ープの多結晶シリコン層3を形成(成膜)することによ
り図1(a)に示すような構造が得られる。なお、多結
晶シリコン層3の成膜は、例えばLPCVD法やスパッ
タ法により行ってもよいし、あるいはプラズマCVD法
によってアモルファスシリコンを成膜した後にアニール
処理を行うことにより結晶化させて成膜してもよい。
First, after the ohmic electrode 2 is formed on the back surface of the n-type silicon substrate 1, the non-doped polycrystalline silicon layer 3 which is a semiconductor layer having a predetermined thickness (for example, 1.5 μm) is formed on the front surface of the n-type silicon substrate 1. By forming (depositing), a structure as shown in FIG. 1 (a) is obtained. The polycrystalline silicon layer 3 may be formed by, for example, the LPCVD method or the sputtering method, or the amorphous silicon may be formed by the plasma CVD method and then annealed to crystallize the film. May be.

【0019】ノンドープの多結晶シリコン層3を形成し
た後、55wt%のフッ化水素水溶液とエタノールとを
略1:1で混合した混合液よりなる電解液の入った陽極
酸化処理槽を利用し、白金電極(図示せず)を負極、n
形シリコン基板1(オーミック電極2)を正極として、
多結晶シリコン層3に光照射を行いながら所定の条件で
陽極酸化処理を行うことによって、多孔質多結晶シリコ
ン層4が図1(b)に示すように形成される。
After forming the non-doped polycrystalline silicon layer 3, an anodizing treatment tank containing an electrolytic solution made of a mixed solution of 55 wt% hydrogen fluoride aqueous solution and ethanol at a ratio of about 1: 1 is used. Platinum electrode (not shown) is the negative electrode, n
Using the silicon substrate 1 (ohmic electrode 2) as a positive electrode,
Porous polycrystalline silicon layer 4 is formed as shown in FIG. 1B by performing anodizing treatment under predetermined conditions while irradiating polycrystalline silicon layer 3 with light.

【0020】上述の陽極酸化処理が終了した後、多孔質
多結晶シリコン層4の最表面に結合している水素原子を
熱処理により脱離させてから、多孔質多結晶シリコン層
4を、例えば急速昇温酸化法(RTO)によって酸化す
ることにより強電界ドリフト層6が形成され、図1
(c)に示す構造が得られる。要するに、本実施形態で
は、多孔質多結晶シリコン層4を陽極酸化処理により形
成した際に多孔質多結晶シリコン層4のシリコン原子を
終端している水素原子を、上記熱処理により脱離させた
後、多孔質多結晶シリコン層4をアニールによって酸化
している。
After the above-mentioned anodic oxidation treatment is completed, hydrogen atoms bonded to the outermost surface of the porous polycrystalline silicon layer 4 are desorbed by heat treatment, and then the porous polycrystalline silicon layer 4 is rapidly removed. The strong electric field drift layer 6 is formed by oxidation by the temperature rising oxidation method (RTO).
The structure shown in (c) is obtained. In short, in this embodiment, after the hydrogen atoms terminating the silicon atoms of the porous polycrystalline silicon layer 4 when the porous polycrystalline silicon layer 4 is formed by the anodic oxidation treatment are desorbed by the above heat treatment, , The porous polycrystalline silicon layer 4 is oxidized by annealing.

【0021】強電界ドリフト層6は図5にて説明したよ
うに、少なくとも、柱状の多結晶シリコン51(グレイ
ン)と、多結晶シリコン51の表面に形成された薄いシ
リコン酸化膜52と、多結晶シリコン51間に介在する
ナノメータオーダの微結晶シリコン層63と、微結晶シ
リコン層63の表面に形成され当該微結晶シリコン層6
3の結晶粒径よりも小さな膜厚の絶縁層であるシリコン
酸化膜64とから構成される。
As described with reference to FIG. 5, the strong electric field drift layer 6 has at least columnar polycrystalline silicon 51 (grains), a thin silicon oxide film 52 formed on the surface of the polycrystalline silicon 51, and the polycrystalline silicon 51. A nanometer-order microcrystalline silicon layer 63 interposed between the silicon 51 and the microcrystalline silicon layer 6 formed on the surface of the microcrystalline silicon layer 63.
3 is a silicon oxide film 64 which is an insulating layer having a film thickness smaller than the crystal grain size.

【0022】しかる後に強電界ドリフト層6上に触媒作
用を持つ材料、例えばPt用いた導電性薄膜からなる表
面電極7を例えば図1(d)に示す蒸着等により形成す
る。
Then, a surface electrode 7 made of a material having a catalytic action, for example, a conductive thin film using Pt is formed on the strong electric field drift layer 6 by vapor deposition shown in FIG. 1D, for example.

【0023】このままではシリコン酸化膜64中に欠陥
を生じさせたままの電界放射型電子源であるが、表面電
極7の形成後、更に高温、酸素雰囲気中に於いて酸化膜
質改善処理を行う(図1(e))。この場合、Ptの触
媒作用の効果を発揮させることができる温度が略200
℃程度であるので、上記の酸化膜質改善処理プロセスの
温度を200℃程度とし、デバイス形成のプロセスとの
マッチングを図る。
Although the field emission type electron source is as it is, the defects are still generated in the silicon oxide film 64, but after the surface electrode 7 is formed, the oxide film quality improving process is further performed in a high temperature and oxygen atmosphere ( FIG. 1E). In this case, the temperature at which the catalytic effect of Pt can be exerted is about 200.
Since the temperature is about 0 ° C., the temperature of the oxide film quality improving process is set to about 200 ° C. to match the device forming process.

【0024】さてこのプロセスでは表面電極7を構成す
るPtの触媒作用により雰囲気中の酸素がイオンに分解
され、シリコン酸化膜64の欠陥を補償をすることにな
るのである。特に強電界ドリフト層6が多孔質であるた
め酸素イオンによって高い欠陥補償効果が期待できる。
In this process, oxygen in the atmosphere is decomposed into ions by the catalytic action of Pt forming the surface electrode 7, and the defects of the silicon oxide film 64 are compensated. In particular, since the strong electric field drift layer 6 is porous, a high defect compensation effect can be expected by oxygen ions.

【0025】このようにして酸化膜質改善処理のプロセ
スを経ることにより、シリコン酸化膜64の欠陥補償が
行われ、その結果電子放出効率が向上し、また電気的耐
圧も向上した電界放射型電子源10が得られることにな
る。
By thus undergoing the oxide film quality improving process, the defect compensation of the silicon oxide film 64 is performed, and as a result, the electron emission efficiency is improved and the electric breakdown voltage is also improved. 10 will be obtained.

【0026】尚表面電極7の材料として触媒作用を持
つ、アルミナやマグネシウムなどの材料を用いてもよ
い。
As the material of the surface electrode 7, a material having a catalytic action such as alumina or magnesium may be used.

【0027】(実施形態2)上記実施形態1では酸化膜
形成後、表面電極7の形成、酸化膜質改善処理のプロセ
スを順次経ているが、本実施形態では請求項2の発明に
対応し、シリコン酸化膜形成と、酸化膜質改善処理とを
同時に行うようにする点に特徴がある。
(Embodiment 2) In the first embodiment, after the oxide film is formed, the surface electrode 7 is formed and the oxide film quality improving process is sequentially performed. In this embodiment, the silicon film corresponds to the invention of claim 2. It is characterized in that the oxide film formation and the oxide film quality improvement treatment are performed simultaneously.

【0028】つまり本実施形態では、まず図2(a)に
示すようにn形シリコン基板1の裏面にオーミック電極
2を形成した後、n形シリコン基板1の表面に所定膜厚
(例えば、1.5μm)の半導体層たるノンドープの多
結晶シリコン層3を形成(成膜)し、この多結晶シリコ
ン層3を形成した後、55wt%のフッ化水素水溶液と
エタノールとを略1:1で混合した混合液よりなる電解
液の入った陽極酸化処理槽を利用し、白金電極(図示せ
ず)を負極、n形シリコン基板1(オーミック電極2)
を正極として、多結晶シリコン層3に光照射を行いなが
ら所定の条件で陽極酸化処理を行うことによって、多孔
質多結晶シリコン層4を図2(b)に示すように形成さ
れる。これまでのプロセスは実施形態1と同じである。
That is, in the present embodiment, first, as shown in FIG. 2A, after forming the ohmic electrode 2 on the back surface of the n-type silicon substrate 1, a predetermined film thickness (for example, 1 A non-doped polycrystalline silicon layer 3 which is a semiconductor layer having a thickness of 0.5 μm) is formed (formed), the polycrystalline silicon layer 3 is formed, and then 55 wt% hydrogen fluoride aqueous solution and ethanol are mixed at a ratio of about 1: 1. Using an anodic oxidation treatment tank containing an electrolytic solution composed of the mixed solution, a platinum electrode (not shown) is used as a negative electrode, and an n-type silicon substrate 1 (ohmic electrode 2) is used.
As a positive electrode, the polycrystalline silicon layer 3 is anodized under a predetermined condition while being irradiated with light, whereby the porous polycrystalline silicon layer 4 is formed as shown in FIG. 2 (b). The process so far is the same as that of the first embodiment.

【0029】そして本実施形態では、陽極酸化処理が終
了した後、多孔質多結晶シリコン層4の最表面に、例え
ばPt、アルミナ、マグネシウム等の触媒作用を持つ材
料により表面電極7を蒸着などにより形成し(図2
(c))する。
In this embodiment, after the anodic oxidation treatment is completed, the surface electrode 7 is deposited on the outermost surface of the porous polycrystalline silicon layer 4 by using a material having a catalytic action such as Pt, alumina or magnesium by vapor deposition or the like. Formed (Fig. 2
(C))

【0030】この表面電極7の形成後、高温、酸素雰囲
気によって、多孔質多結晶シリコン層4を酸化すること
により強電界ドリフト層6を形成すると同時に、強電界
ドリフト層6のシリコン酸化膜64の欠陥を表面電極7
の材料の触媒作用によって実施形態1の場合と同様に欠
陥補償を行うのである。
After the surface electrode 7 is formed, the porous polycrystalline silicon layer 4 is oxidized at a high temperature in an oxygen atmosphere to form the strong electric field drift layer 6, and at the same time, the silicon oxide film 64 of the strong electric field drift layer 6 is formed. Defect 7 on the surface electrode
As in the case of the first embodiment, the defect compensation is performed by the catalytic action of the above material.

【0031】つまり本実施形態では酸化膜形成と同じプ
ロセスにより同時に酸化膜質改善処理が行え、実施形態
1に比べてプロセスの簡便化と歩留まりの向上、製造コ
ストの低減化が図れるのである。
That is, in the present embodiment, the oxide film quality improving process can be performed at the same time by the same process as the oxide film formation, so that the process can be simplified, the yield can be improved, and the manufacturing cost can be reduced as compared with the first embodiment.

【0032】尚表面電極7を表面に形成した強電界ドリ
フト層6の製造方法及び材料は上記実施形態に特に限定
されるものではなく、他の製造方法及び材料によって得
られるものでも良い。
The manufacturing method and material of the strong electric field drift layer 6 having the surface electrode 7 formed on the surface thereof are not particularly limited to those in the above-mentioned embodiment, and may be obtained by other manufacturing methods and materials.

【0033】[0033]

【発明の効果】請求項1の発明は、導電性基板と、該導
電性基板の表面側に形成された多孔質半導体層よりなる
強電界ドリフト層と、該強電界ドリフト層上に形成され
た表面電極とを備え、該表面電極を上記導電性基板に対
して高電位側として電圧を印加することにより上記導電
性基板から注入された電子が上記強電界ドリフト層をド
リフトし上記表面電極を通して放出される電界放射型電
子源の製造方法において、上記強電界ドリフト層上に触
媒作用を持つ材料により上記表面電極を形成し、該表面
電極を形成した後、高温、酸素雰囲気中で上記表面電極
の触媒作用により上記強電界ドリフト層の酸化膜からな
る絶縁層の酸化膜質改善処理を施すので、表面電極の材
料の触媒作用により発生する酸素イオンによって酸化膜
からなる絶縁層の欠陥補償が図れ、その結果電子放出の
効率が向上し且つ電気的耐圧が向上した電界放射型電子
源を得られるという効果がある。
According to the invention of claim 1, a conductive substrate and the conductive substrate are provided.
A strong electric field drift layer made of a porous semiconductor layer formed on the surface side of the conductive substrate and a surface electrode formed on the strong electric field drift layer are provided, and the surface electrode is higher than the conductive substrate. In the method of manufacturing a field emission electron source, electrons injected from the conductive substrate drift on the strong electric field drift layer and are emitted through the surface electrode when a voltage is applied on the strong electric field drift layer. to a material having a catalytic action to form the surface electrode, after forming the surface electrodes, high temperature, oxidation film quality of the insulating layer made of an oxide film in an oxygen atmosphere the strong electric field drift layer by the catalytic action of the surface electrode Since the improvement treatment is performed, oxygen ions generated by the catalytic action of the material of the surface electrode can compensate for defects in the insulating layer made of an oxide film, and as a result, the efficiency of electron emission can be improved. There is an effect of obtaining the field emission electron source gas withstand voltage is improved.

【0034】 請求項2の発明は、導電性基板と、該導
電性基板の表面側に形成された多孔質半導体層よりなる
強電界ドリフト層と、該強電界ドリフト層上に形成され
た表面電極とを備え、該表面電極を上記導電性基板に対
して高電位側として電圧を印加することにより上記導電
性基板から注入された電子が上記強電界ドリフト層をド
リフトし上記表面電極を通して放出される電界放射型電
子源の製造方法において、上記多孔質半導体層の表面に
触媒作用を持つ材料により上記表面電極を形成し、該表
面電極を形成した後、高温、酸素雰囲気中で上記表面電
極の触媒作用により上記多孔質半導体層を酸化して上記
強電界ドリフト層を形成し、更に該強電界ドリフト層に
形成された酸化膜からなる絶縁層の上記表面電極の触媒
作用で該絶縁層の酸化膜質改善処理を施すので、表面電
極の材料の触媒作用により発生する酸素イオンによって
酸化膜からなる絶縁層の欠陥補償が図れ、その結果電子
放出の効率が向上し且つ電気的耐圧が向上した電界放射
型電子源を得られる上に、プロセスの簡便化と歩留まり
の向上、更には製造コストの低減が図れるという効果が
ある。
According to a second aspect of the present invention, there is provided a conductive substrate and the conductive substrate.
A strong electric field drift layer of the multi-porous semiconductor layer formed on a surface side of the conductive substrate, and a surface electrode formed on said strong electric field drift layer, said surface electrode against the conductive substrate In the method of manufacturing a field emission electron source, electrons injected from the conductive substrate drift on the strong electric field drift layer and are emitted through the surface electrode by applying a voltage on the high potential side, in the porous semiconductor layer. the surface electrode is formed on the surface of a material having a catalytic action, after forming the surface electrodes, the high temperature, the strength and oxidizing the porous semiconductor layer by the catalytic action of the surface electrode in an oxygen atmosphere field drift Layer, and further to the strong electric field drift layer
Since catalysis of the surface electrodes made of formed oxide film insulating layer subjected to oxidation film quality improvement process of the insulating layer, defects in the insulating layer made of an oxide film by oxygen ions generated by the catalytic action of the surface electrode material The effect that the field emission electron source can be compensated, and as a result, the efficiency of electron emission is improved and the electric breakdown voltage is improved, the process can be simplified, the yield can be improved, and the manufacturing cost can be reduced. There is.

【0035】請求項3の発明では、請求項1又は2の発
明において、上記絶縁層をシリコン酸化膜により形成し
たので、欠陥補償の効果が高い。
According to the invention of claim 3, in the invention of claim 1 or 2, since the insulating layer is formed of a silicon oxide film, the effect of defect compensation is high.

【0036】請求項4の発明では、請求項1乃至3の何
れかの発明において、上記表面電極をPtにより形成し
たので、酸化膜質改善処理の温度をデバイス形成プロセ
スにマッチングさせることができる。
According to the invention of claim 4, in any one of the inventions of claims 1 to 3, since the surface electrode is formed of Pt, the temperature of the oxide film quality improving treatment can be matched with the device forming process.

【0037】請求項5の発明では、請求項1乃至4の何
れかの発明において、上記強電界ドリフト層を多孔質多
結晶シリコン層により形成したので、酸素イオンによる
欠陥補償効果がより高くなる。
According to a fifth aspect of the invention, in any one of the first to fourth aspects of the invention, since the strong electric field drift layer is formed of the porous polycrystalline silicon layer, the defect compensation effect by oxygen ions becomes higher.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施形態1のプロセス説明図である。FIG. 1 is a process explanatory diagram according to a first embodiment of the present invention.

【図2】本発明の実施形態2のプロセス説明図である。FIG. 2 is a process explanatory diagram according to the second embodiment of the present invention.

【図3】基本となる電界放射型電子源の概略断面図であ
る。
FIG. 3 is a schematic sectional view of a basic field emission electron source.

【図4】同上の特性原理説明図である。FIG. 4 is an explanatory view of a characteristic principle of the above.

【図5】同上の電子放出機構の説明図である。FIG. 5 is an explanatory diagram of an electron emission mechanism of the above.

【符号の説明】[Explanation of symbols]

1 n形シリコン基板 2 オーミック電極 3 多結晶シリコン層 4 多孔質多結晶シリコン層 6 強電界ドリフト層 7 表面電極 10 電界放射型電子源 1 n-type silicon substrate 2 Ohmic electrodes 3 Polycrystalline silicon layer 4 Porous polycrystalline silicon layer 6 Strong electric field drift layer 7 Surface electrode 10 Field emission electron source

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平10−326557(JP,A) 特開 平9−45679(JP,A) 特開 平9−259795(JP,A) 特開 平8−250766(JP,A) (58)調査した分野(Int.Cl.7,DB名) H01J 9/02 H01J 1/30 H01J 31/12 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-10-326557 (JP, A) JP-A-9-45679 (JP, A) JP-A-9-259795 (JP, A) JP-A-8- 250766 (JP, A) (58) Fields surveyed (Int.Cl. 7 , DB name) H01J 9/02 H01J 1/30 H01J 31/12

Claims (5)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】導電性基板と、該導電性基板の表面側に形
成された多孔質半導体層よりなる強電界ドリフト層と、
該強電界ドリフト層上に形成された表面電極とを備え、
該表面電極を上記導電性基板に対して高電位側として電
圧を印加することにより上記導電性基板から注入された
電子が上記強電界ドリフト層をドリフトし上記表面電極
を通して放出される電界放射型電子源の製造方法におい
て、上記強電界ドリフト層上に触媒作用を持つ材料によ
上記表面電極を形成し、該表面電極を形成した後、高
温、酸素雰囲気中で上記表面電極の触媒作用により上記
強電界ドリフト層の酸化膜からなる絶縁層の酸化膜質改
善処理を施すことを特徴とする電界放射型電子源の製造
方法。
1. A conductive substrate and a shape on the surface side of the conductive substrate.
A strong electric field drift layer formed of a porous semiconductor layer ,
A surface electrode formed on the strong electric field drift layer,
A field emission electron in which electrons injected from the conductive substrate drift in the strong electric field drift layer and are emitted through the surface electrode by applying a voltage with the surface electrode on the high potential side of the conductive substrate. the method of manufacturing a source, a material having a catalytic action in the strong electric field drift layer to form the surface electrode, the strong electric field after the formation of the surface electrodes, high temperature, in an oxygen atmosphere by the catalytic action of said surface electrode A method of manufacturing a field emission electron source, characterized by performing an oxide film quality improving process on an insulating layer made of an oxide film of a drift layer.
【請求項2】導電性基板と、該導電性基板の表面側に形
成された多孔質半導体層よりなる強電界ドリフト層と、
該強電界ドリフト層上に形成された表面電極とを備え、
該表面電極を上記導電性基板に対して高電位側として電
圧を印加することにより上記導電性基板から注入された
電子が上記強電界ドリフト層をドリフトし上記表面電極
を通して放出される電界放射型電子源の製造方法におい
て、上記多孔質半導体層の表面に触媒作用を持つ材料に
より上記表面電極を形成し、該表面電極を形成した後、
高温、酸素雰囲気中で上記表面電極の触媒作用により
記多孔質半導体層を酸化して上記強電界ドリフト層を形
し、更に該強電界ドリフト層に形成された酸化膜から
なる絶縁層の上記表面電極の触媒作用で該絶縁層の酸化
膜質改善処理を施すことを特徴とする電界放射型電子源
の製造方法。
2. A conductive substrate and a shape on the surface side of the conductive substrate.
A strong electric field drift layer formed of a porous semiconductor layer ,
A surface electrode formed on the strong electric field drift layer,
A field emission electron in which electrons injected from the conductive substrate drift in the strong electric field drift layer and are emitted through the surface electrode by applying a voltage with the surface electrode on the high potential side of the conductive substrate. the method of manufacturing a source, a material having a catalytic effect on the surface of the porous semiconductor layer to form the surface electrode, after forming the surface electrodes,
High temperature, above by the catalytic action of the surface electrode in an oxygen atmosphere
Oxidizing the porous semiconductor layer to form the strong electric field drift layer, and further improving the oxide film quality of the insulating layer by the catalytic action of the surface electrode of the insulating layer formed of the oxide film formed on the strong electric field drift layer. A method of manufacturing a field emission electron source, which comprises:
【請求項3】上記絶縁層をシリコン酸化膜により形成し
たことを特徴とする請求項1又は2記載の電界放射型電
子源の製造方法。
3. The method of manufacturing a field emission electron source according to claim 1, wherein the insulating layer is formed of a silicon oxide film.
【請求項4】上記表面電極をPtにより形成したことを
特徴とする請求項1乃至3の何れか記載の電界放射型電
子源の製造方法。
4. The method for manufacturing a field emission type electron source according to claim 1, wherein the surface electrode is formed of Pt.
【請求項5】上記強電界ドリフト層を多孔質多結晶シリ
コン層により形成したことを特徴とする請求項1乃至4
の何れか記載の電界放射型電子源の製造方法。
5. The strong electric field drift layer is formed of a porous polycrystalline silicon layer.
5. A method for manufacturing a field emission electron source according to any one of 1.
JP29595799A 1999-10-18 1999-10-18 Method for manufacturing field emission electron source Expired - Fee Related JP3478206B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29595799A JP3478206B2 (en) 1999-10-18 1999-10-18 Method for manufacturing field emission electron source

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29595799A JP3478206B2 (en) 1999-10-18 1999-10-18 Method for manufacturing field emission electron source

Publications (2)

Publication Number Publication Date
JP2001118499A JP2001118499A (en) 2001-04-27
JP3478206B2 true JP3478206B2 (en) 2003-12-15

Family

ID=17827295

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29595799A Expired - Fee Related JP3478206B2 (en) 1999-10-18 1999-10-18 Method for manufacturing field emission electron source

Country Status (1)

Country Link
JP (1) JP3478206B2 (en)

Also Published As

Publication number Publication date
JP2001118499A (en) 2001-04-27

Similar Documents

Publication Publication Date Title
US6720717B2 (en) Field emission-type electron source
WO2002089166A1 (en) Field emission electron source and production method thereof
TW588389B (en) Quantum device
JP3478206B2 (en) Method for manufacturing field emission electron source
JP3969057B2 (en) Insulating thin film forming method, insulating thin film forming apparatus, field emission electron source, and MOSFET
JP3508652B2 (en) Field emission type electron source and method of manufacturing the same
JP3508651B2 (en) Field emission type electron source and method of manufacturing the same
JP3465657B2 (en) Field emission type electron source and manufacturing method thereof
JP4321009B2 (en) Manufacturing method of field emission electron source
JP4616538B2 (en) Manufacturing method of field emission electron source
JP2003187688A (en) Field emission type electron source and manufacturing method of the same
JP3648599B2 (en) Manufacturing method of field emission electron source
JP3687520B2 (en) Field emission electron source and manufacturing method thereof
JP3551862B2 (en) Method for manufacturing field emission electron source
JP3591511B2 (en) Method for manufacturing field emission electron source
JP3648603B2 (en) Manufacturing method of field emission electron source
JP3648602B2 (en) Manufacturing method of field emission electron source
JP3480464B2 (en) Method for manufacturing field emission electron source
JP3809808B2 (en) Manufacturing method of field emission electron source
JP3531643B2 (en) Field emission type electron source and method of manufacturing the same
JP2003229050A (en) Manufacturing method for field emission type electron source, and field emission type electron source
JP3478279B2 (en) Method for manufacturing field emission electron source
JP2003100201A (en) Field emission electron source and manufacturing method thereof
JP3963121B2 (en) Anodic oxidation method, electrochemical oxidation method, field emission electron source and method for producing the same
JP4543716B2 (en) Electron source and manufacturing method thereof

Legal Events

Date Code Title Description
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20030902

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20071003

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20081003

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20081003

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091003

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091003

Year of fee payment: 6

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091003

Year of fee payment: 6

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101003

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101003

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111003

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111003

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121003

Year of fee payment: 9

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131003

Year of fee payment: 10

LAPS Cancellation because of no payment of annual fees