JP3471473B2 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JP3471473B2 JP3471473B2 JP07202695A JP7202695A JP3471473B2 JP 3471473 B2 JP3471473 B2 JP 3471473B2 JP 07202695 A JP07202695 A JP 07202695A JP 7202695 A JP7202695 A JP 7202695A JP 3471473 B2 JP3471473 B2 JP 3471473B2
- Authority
- JP
- Japan
- Prior art keywords
- trench
- layer
- semiconductor
- oxide film
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
【０００１】[0001]
【産業上の利用分野】この発明は半導体装置、例えば、
絶縁ゲート型電界効果トランジスタ、とりわけ大電力用
の縦型ＭＯＳＦＥＴに関する。BACKGROUND OF THE INVENTION The present invention relates to a semiconductor device, for example,
The present invention relates to an insulated gate field effect transistor, and more particularly to a vertical MOSFET for high power.
【０００２】[0002]
【従来の技術】近年、電力用トランジスタとしてシリコ
ン単結晶材料を使用して作製される縦型パワーＭＯＳＦ
ＥＴが多用されている。電力用トランジスタの損失を低
減するためにはオン抵抗の低減が必要であり、効果的に
オン抵抗低減が可能な素子構造として図１２に示すトレ
ンチゲート型パワーＭＯＳＦＥＴ（例えば、特開昭５９
−８３７４号公報）が提案されている。トレンチゲート
型パワーＭＯＳＦＥＴはｎ型半導体基板２０上にｎ型エ
ピタキシャル層２１が形成され、ｎ型エピタキシャル層
２１上にｐ型拡散層２２が形成され、さらに、ｐ型拡散
層２２の所定領域にｎ型拡散層２３が形成されている。
又、ｎ型拡散層２３とｐ型拡散層２２を貫通してｎ型エ
ピタキシャル層２１に達するトレンチ２４が形成され、
トレンチ２４内にはゲート酸化膜層２５を介してポリシ
リコン層２６が充填されている。ポリシリコン層２６の
上面には酸化膜層２７が形成され、酸化膜層２７上を含
むｎ型拡散層２３上にはアルミ層２８が形成されてい
る。2. Description of the Related Art In recent years, a vertical power MOSF manufactured by using a silicon single crystal material as a power transistor.
ET is heavily used. In order to reduce the loss of the power transistor, it is necessary to reduce the on-resistance, and as a device structure capable of effectively reducing the on-resistance, the trench gate type power MOSFET shown in FIG.
No. 8374) has been proposed. In the trench gate type power MOSFET, an n-type epitaxial layer 21 is formed on an n-type semiconductor substrate 20, a p-type diffusion layer 22 is formed on the n-type epitaxial layer 21, and an n-type epitaxial layer 21 is formed on a predetermined region of the p-type diffusion layer 22. The mold diffusion layer 23 is formed.
Further, a trench 24 penetrating the n-type diffusion layer 23 and the p-type diffusion layer 22 to reach the n-type epitaxial layer 21 is formed,
A polysilicon layer 26 is filled in the trench 24 via a gate oxide film layer 25. An oxide film layer 27 is formed on the upper surface of the polysilicon layer 26, and an aluminum layer 28 is formed on the n-type diffusion layer 23 including the oxide film layer 27.
【０００３】ここで、トレンチゲート部はトレンチ２４
の形成後、熱酸化によりトレンチ２４の内面を酸化して
ゲート酸化膜層２５を側部と底部に形成し、その後ゲー
ト電極（ポリシリコン層２６）を形成してトレンチゲー
トの基本構造を完成する。前記トレンチ２４の表面を酸
化する工程において、ゲート閾電圧を低く設定するため
にトレンチ２４の側部の酸化膜の厚さを薄く（例えば５
０ｎｍ）する必要がある。酸化速度の面方向依存性が少
ないシリコンにおいては、トレンチ２４の側部と同時に
形成されたトレンチ２４の底部の酸化膜の厚さもトレン
チ２４の側部と同等に薄くなる。従って、低電位のゲー
ト電極と高電位のドレイン層に挟まれたトレンチ２４の
底部の薄い酸化膜は絶縁破壊を起こし易く、高耐圧のト
レンチゲート型パワーＭＯＳＦＥＴを作製することが困
難であった。Here, the trench gate portion is the trench 24.
After the formation, the inner surface of the trench 24 is oxidized by thermal oxidation to form the gate oxide film layer 25 on the side portion and the bottom portion, and then the gate electrode (polysilicon layer 26) is formed to complete the basic structure of the trench gate. . In the step of oxidizing the surface of the trench 24, in order to set the gate threshold voltage low, the thickness of the oxide film on the side of the trench 24 is made thin (for example, 5
0 nm). In the case of silicon in which the surface direction dependence of the oxidation rate is small, the thickness of the oxide film at the bottom of the trench 24, which is formed at the same time as the side portion of the trench 24, is also thin as in the side portion of the trench 24. Therefore, the thin oxide film at the bottom of the trench 24 sandwiched between the low-potential gate electrode and the high-potential drain layer easily causes dielectric breakdown, and it is difficult to manufacture a high breakdown voltage trench gate type power MOSFET.
【０００４】この問題を解決する公知技術が、例えば特
開平２−１０２５７９号公報にて開示されている。この
方法は、複数回の酸化膜を形成する工程とトレンチ側面
に耐酸化性マスクを形成する工程を含む工程により、酸
化膜の厚さをトレンチ側面では薄く、底面では厚くして
低いゲート閾電圧と高い耐圧を両立したトレンチゲート
型パワーＭＯＳＦＥＴを作製するものである。この方法
の工程を図１３〜図２１を参照して、詳細に説明する。A known technique for solving this problem is disclosed in, for example, Japanese Patent Application Laid-Open No. 2-102579. This method consists of forming the oxide film multiple times and forming an oxidation resistant mask on the side surface of the trench. And a trench gate type power MOSFET having both a high withstand voltage. The steps of this method will be described in detail with reference to FIGS.
【０００５】まず、図１３に示すように、低抵抗のｎ+
型半導体基板３０上に、ｎ型エピタキシャル層３１を形
成し、このｎ型エピタキシャル層３１上に、ｐ型拡散層
３２を形成する。その後、熱酸化法によりｐ型拡散層３
２上に、第１酸化膜層３３を形成する。次に、図１４に
示すように、ホトリソグラフィーにより第１酸化膜層３
３をパターニングして一定幅を除去した後、第１酸化膜
層３３をマスクとして、反応性イオンエッチング（ＲＩ
Ｅ）法により、ｐ型拡散層３２を貫通しｎ型エピタキシ
ャル層３１に達するトレンチ３４を形成する。First, as shown in FIG. 13, low resistance n +
An n-type epitaxial layer 31 is formed on the type semiconductor substrate 30, and a p-type diffusion layer 32 is formed on the n-type epitaxial layer 31. After that, the p-type diffusion layer 3 is formed by the thermal oxidation method.
A first oxide film layer 33 is formed on the second layer 2. Next, as shown in FIG. 14, the first oxide film layer 3 is formed by photolithography.
3 is patterned to remove a certain width, and then reactive ion etching (RI) is performed using the first oxide film layer 33 as a mask.
By the E) method, a trench 34 that penetrates the p-type diffusion layer 32 and reaches the n-type epitaxial layer 31 is formed.
【０００６】続いて、図１５に示すように、第１酸化膜
層３３を除去後、熱酸化法によりｐ型拡散層３２の上面
及びトレンチ３４の内面に、第２酸化膜層３５を形成す
る。更に、第２酸化膜層３５上に、窒化シリコン層３６
と第３酸化膜層３７とを順次形成する。Subsequently, as shown in FIG. 15, after removing the first oxide film layer 33, a second oxide film layer 35 is formed on the upper surface of the p-type diffusion layer 32 and the inner surface of the trench 34 by a thermal oxidation method. . Further, a silicon nitride layer 36 is formed on the second oxide film layer 35.
And the third oxide film layer 37 are sequentially formed.
【０００７】その後、図１６に示すように、ＲＩＥ法に
より第３酸化膜層３７、窒化シリコン層３６及び第２酸
化膜層３５を順次異方性エッチングし、トレンチ３４の
側壁部に第２酸化膜層３５、窒化シリコン層３６及び第
３酸化膜層３７をサイドウォールとして残し、その他の
部分を全て除去する。After that, as shown in FIG. 16, the third oxide film layer 37, the silicon nitride layer 36 and the second oxide film layer 35 are anisotropically etched in order by the RIE method so that the sidewalls of the trench 34 are subjected to the second oxidation. The film layer 35, the silicon nitride layer 36, and the third oxide film layer 37 are left as sidewalls, and all other portions are removed.
【０００８】そして、図１７に示すように、加熱リン酸
によりトレンチ３４の底部のコーナー部３４ａの窒化シ
リコン層３６をエッチング除去する。続いて、図１８に
示すように、フッ酸により第３酸化膜層３７を除去した
後、熱酸化法により第４酸化膜層３８を、窒化シリコン
層３６の配置部分を除くトレンチ３４の内面及びｐ型拡
散層３２上に形成する。Then, as shown in FIG. 17, the silicon nitride layer 36 at the corner portion 34a at the bottom of the trench 34 is removed by etching with hot phosphoric acid. Subsequently, as shown in FIG. 18, after removing the third oxide film layer 37 by hydrofluoric acid, the fourth oxide film layer 38 is formed by a thermal oxidation method on the inner surface of the trench 34 excluding the portion where the silicon nitride layer 36 is disposed and It is formed on the p-type diffusion layer 32.
【０００９】その後、図１９に示すように、加熱リン酸
により窒化シリコン層３６を除去した後、この部分に熱
酸化法によりゲート酸化膜層３９を形成する。続いて、
図２０に示すように、トレンチ３４内を、第１及び第２
ポリシリコン層４０、４１により順次埋め戻す。After that, as shown in FIG. 19, the silicon nitride layer 36 is removed by hot phosphoric acid, and then a gate oxide film layer 39 is formed on this portion by a thermal oxidation method. continue,
As shown in FIG. 20, inside the trench 34, the first and second trenches are formed.
The polysilicon layers 40 and 41 are sequentially backfilled.
【００１０】しかる後、図２１に示すように、ｐ型拡散
層３２上の第４酸化膜層３８をエッチング除去した後、
ｐ型拡散層３２内に、低抵抗のｎ+ 型拡散層４２を形成
する。その後、第１及び第２ポリシリコン層４０、４１
上に、熱酸化法により第５酸化膜層４３を形成し、この
第５酸化膜層４３及びｎ+ 型拡散層４２上に、アルミ層
４４を形成し、縦型ＭＯＳＦＥＴを完成する。Then, as shown in FIG. 21, after the fourth oxide film layer 38 on the p-type diffusion layer 32 is removed by etching,
A low resistance n + type diffusion layer 42 is formed in the p type diffusion layer 32. Then, the first and second polysilicon layers 40 and 41 are formed.
A fifth oxide film layer 43 is formed thereon by a thermal oxidation method, and an aluminum layer 44 is formed on the fifth oxide film layer 43 and the n + type diffusion layer 42 to complete the vertical MOSFET.
【００１１】かくして、ｎ+ 型半導体基板３０上に、順
次積層形成されたｐ型拡散層３２及びｎ+ 型拡散層４２
に貫通するトレンチ３４が設けられ、このトレンチ３４
におけるｐ型拡散層３２の側面部に、薄いゲート酸化膜
層３９が形成されるとともに、トレンチ３４のコーナー
部３４ａを含むその他の部分に、厚い第４酸化膜層３８
が形成され、更には、トレンチ３４内部に、ポリシリコ
ン層４０、４１が埋設され、最上層にアルミ層４４が堆
積形成された縦型ＭＯＳＦＥＴが得られる。Thus, the p + diffusion layer 32 and the n + diffusion layer 42, which are sequentially laminated on the n + type semiconductor substrate 30, are formed.
A trench 34 penetrating into the
A thin gate oxide film layer 39 is formed on the side surface portion of the p-type diffusion layer 32 in the above, and a thick fourth oxide film layer 38 is formed on the other portion including the corner portion 34a of the trench 34.
Further, the vertical MOSFET in which the polysilicon layers 40 and 41 are buried inside the trench 34 and the aluminum layer 44 is deposited and formed on the uppermost layer is obtained.
【００１２】以上説明した従来の方法により、トレンチ
３４の底部コーナー部を除く側面部の絶縁膜層を薄く形
成するとともに、トレンチ３４のコーナー部を含む底面
部の絶縁膜層を厚く形成したので、閾電圧が低くでき、
しかも耐圧劣化が防止でき高耐圧化を可能にしていた。According to the conventional method described above, the insulating film layer on the side surface portion excluding the bottom corner portion of the trench 34 is formed thin and the insulating film layer on the bottom surface portion including the corner portion of the trench 34 is formed thick. Threshold voltage can be lowered,
Moreover, deterioration of withstand voltage can be prevented and high withstand voltage can be achieved.
【００１３】[0013]
【発明が解決しようとする課題】しかし、閾電圧が低
く、耐圧が高いトレンチゲート型パワーＭＯＳＦＥＴを
上述した従来方法により作製しようとすると、半導体材
料にシリコンを使用し、トレンチ３４の内部に形成する
絶縁膜層の厚さを側部では薄く、底部では厚くするため
に、複数回の酸化工程と耐酸化性膜の形成を含む複雑な
作製工程を必要とした。このため、製造コストが高く、
製造歩留りが低いという問題点があった。However, when a trench gate type power MOSFET having a low threshold voltage and a high breakdown voltage is to be manufactured by the above-mentioned conventional method, silicon is used as a semiconductor material and is formed inside the trench 34. In order to make the thickness of the insulating film layer thin on the side portion and thick on the bottom portion, a complicated fabrication process including a plurality of oxidation processes and formation of an oxidation resistant film was required. Therefore, the manufacturing cost is high,
There is a problem that the manufacturing yield is low.
【００１４】そこで、この発明の目的は、トレンチの内
部で酸化膜厚さが異なる半導体装置においてその製造が
容易な半導体装置及びその製造方法を提供することにあ
る。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having a different oxide film thickness inside the trench, which can be easily manufactured, and a manufacturing method thereof.
【００１５】[0015]
【課題を解決するための手段】請求項１に記載の発明
は、表面の面方位が（０００１）カーボン面である六方
晶系の単結晶炭化珪素と、前記単結晶炭化珪素に形成さ
れ、側部および底部を有するトレンチと、前記トレンチ
の側部および底部に形成され、かつトレンチの側部での
膜厚に比べトレンチの底部での膜厚の方が厚い熱酸化膜
とを備えた半導体装置をその要旨とする。According to a first aspect of the present invention, there is provided a hexagonal single crystal silicon carbide having a (0001) carbon surface as a surface orientation, and a side formed on the single crystal silicon carbide. Device having a trench having a bottom and a bottom, and a thermal oxide film formed on the sides and the bottom of the trench and having a thicker film at the bottom of the trench than at the side of the trench Is the gist.
【００１６】請求項２に記載の発明は、第１導電型の低
抵抗層と当該低抵抗層上に形成された第１導電型の高抵
抗層の二層にて構成され、かつ前記高抵抗層の表面の面
方位が（０００１）カーボン面である六方晶系の単結晶
炭化珪素よりなる半導体基板と、前記半導体基板の表面
上に形成され、表面の面方位が（０００１）カーボン面
である六方晶系の単結晶炭化珪素よりなる第２導電型の
半導体層と、前記半導体層内の所定領域に形成された第
１導電型の半導体領域と、前記半導体領域と半導体層を
貫通し前記半導体基板に達し、側部および底部を有する
トレンチと、前記トレンチの側部および底部に形成さ
れ、かつトレンチの側部での膜厚に比べトレンチの底部
での膜厚の方が厚いゲート絶縁膜としてのゲート熱酸化
膜と、前記トレンチ内における前記ゲート熱酸化膜の内
側に形成されたゲート電極層と、少なくとも前記半導体
領域表面に形成された第１の電極層と、前記半導体基板
の裏面側に形成された第２の電極層とを備えた半導体装
置をその要旨とする。According to a second aspect of the present invention, there is provided a two-layer structure including a first-conductivity-type low-resistance layer and a first-conductivity-type high-resistance layer formed on the low-resistance layer, and the high-resistance A semiconductor substrate made of hexagonal single-crystal silicon carbide having a (0001) carbon surface in the surface orientation of the layer, and a surface orientation of the (0001) carbon surface formed on the surface of the semiconductor substrate. A second conductivity type semiconductor layer made of hexagonal single crystal silicon carbide, a first conductivity type semiconductor region formed in a predetermined region in the semiconductor layer, and the semiconductor region and the semiconductor layer penetrating the semiconductor layer. As a trench reaching the substrate, having a side and a bottom, and a gate insulating film formed at the side and bottom of the trench and having a thicker film at the bottom of the trench than at the side of the trench. Gate thermal oxide film and the trench A gate electrode layer formed inside the gate thermal oxide film, a first electrode layer formed at least on the surface of the semiconductor region, and a second electrode layer formed on the back surface side of the semiconductor substrate. The semiconductor device provided is the gist.
【００１７】請求項３に記載の発明は、請求項１に記載
の発明における前記単結晶炭化珪素の表面と前記トレン
チの側部とは４５°〜９０°の角度をなす半導体装置を
その要旨とする。According to a third aspect of the present invention, the gist of the semiconductor device is that the surface of the single crystal silicon carbide in the first aspect of the invention and the side portion of the trench form an angle of 45 ° to 90 °. To do.
【００１８】請求項４に記載の発明は、請求項２に記載
の発明における前記半導体層の表面と前記トレンチの側
部とは４５°〜９０°の角度をなす半導体装置をその要
旨とする。A fourth aspect of the present invention is summarized as a semiconductor device according to the second aspect, wherein the surface of the semiconductor layer and a side portion of the trench form an angle of 45 ° to 90 °.
【００１９】請求項５に記載の発明は、請求項１に記載
の発明における前記トレンチの底部は前記単結晶炭化珪
素の表面に平行である半導体装置をその要旨とする。請
求項６に記載の発明は、請求項２に記載の発明における
前記トレンチの底部は前記半導体層の表面に平行である
半導体装置をその要旨とする。A fifth aspect of the present invention has as its gist a semiconductor device in which the bottom of the trench in the first aspect of the invention is parallel to the surface of the single crystal silicon carbide. A sixth aspect of the present invention has as its gist a semiconductor device in which the bottom of the trench in the second aspect of the invention is parallel to the surface of the semiconductor layer.
【００２０】請求項７に記載の発明は、請求項１または
２に記載の発明における前記トレンチの側部での熱酸化
膜の膜厚「１」に対し底部での熱酸化膜の膜厚が「２」
以上の比率である半導体装置をその要旨とする。According to a seventh aspect of the present invention, the film thickness of the thermal oxide film at the bottom is "1" in comparison with the film thickness "1" of the thermal oxide film at the side of the trench in the invention according to the first or second aspect. "2"
The gist of the semiconductor device is the above ratio.
【００２１】請求項８に記載の発明は、請求項１または
２に記載の発明における前記トレンチの側部での熱酸化
膜の膜厚は１０〜１００ｎｍである半導体装置をその要
旨とする。The gist of the invention described in claim 8 is a semiconductor device in which the film thickness of the thermal oxide film on the side portion of the trench in the invention described in claim 1 or 2 is 10 to 100 nm.
【００２２】請求項９に記載の発明は、六方晶系の単結
晶炭化珪素よりなる第１導電型の低抵抗層の上に、六方
晶系の単結晶炭化珪素よりなる第１導電型の高抵抗層を
積層して当該高抵抗層の表面の面方位が（０００１）カ
ーボン面である半導体基板を形成する第１工程と、前記
半導体基板の表面上に、表面の面方位が（０００１）カ
ーボン面である六方晶系の単結晶炭化珪素よりなる第２
導電型の半導体層を形成するとともに、この半導体層内
の所定領域に第１導電型の半導体領域を形成する第２工
程と、前記半導体領域と半導体層を貫通し前記半導体基
板に達し、側部および底部を有するトレンチを形成する
第３工程と、前記トレンチの内壁を熱酸化することによ
りトレンチの側部での膜厚に比べトレンチの底部での膜
厚の方が厚いゲート絶縁膜としてのゲート熱酸化膜を形
成する第４工程と、前記トレンチ内における前記ゲート
熱酸化膜の内側にゲート電極層を、前記半導体層表面お
よび半導体領域表面に第１の電極層を、前記半導体基板
の裏面側に第２の電極層を、それぞれ形成する第５工程
とを備えた半導体装置の製造方法をその要旨とする。According to a ninth aspect of the present invention, a first-conductivity-type high resistance layer made of hexagonal single-crystal silicon carbide is formed on a first-conductivity-type low resistance layer made of hexagonal single-crystal silicon carbide. A first step of laminating a resistance layer to form a semiconductor substrate in which the surface orientation of the high resistance layer is a (0001) carbon surface; and a surface orientation of the surface of the semiconductor substrate is a (0001) carbon surface. The second surface is composed of hexagonal single crystal silicon carbide
A second step of forming a conductive type semiconductor layer and forming a first conductive type semiconductor region in a predetermined region in the semiconductor layer, and penetrating the semiconductor region and the semiconductor layer to reach the semiconductor substrate, and a side portion. And a third step of forming a trench having a bottom, and a gate as a gate insulating film in which the film thickness at the bottom of the trench is thicker than that at the side of the trench by thermally oxidizing the inner wall of the trench. A fourth step of forming a thermal oxide film, a gate electrode layer inside the gate thermal oxide film in the trench, a first electrode layer on the semiconductor layer surface and a semiconductor region surface, and a back surface side of the semiconductor substrate. The gist is a method of manufacturing a semiconductor device, which includes a fifth step of forming the second electrode layers respectively.
【００２３】[0023]
【作用】請求項１，７，８に記載の発明によれば、酸化
速度が速い六方晶系単結晶炭化珪素の（０００１）カー
ボン面をトレンチの底部とし、この（０００１）カーボ
ン面に対して酸化速度が遅い面をトレンチの側部とした
ので一度の熱酸化工程によりトレンチの側部と底部で厚
さが異なる熱酸化膜を形成できる。According to the present invention, the (0001) carbon surface of hexagonal single crystal silicon carbide having a high oxidation rate is used as the bottom of the trench, and the (0001) carbon surface is Since the surface having a slow oxidation rate is the side portion of the trench, a thermal oxide film having different thicknesses on the side portion and the bottom portion of the trench can be formed by one thermal oxidation step.
【００２４】請求項２に記載の発明によれば、トレンチ
側部での第２導電型の半導体層の表面がチャネルとなっ
て、ソース・ドレイン間に電流が流れる。この際、ゲー
ト絶縁膜としてのゲート熱酸化膜はトレンチの側部での
膜厚に比べトレンチの底部での膜厚の方が厚くなってい
るので、閾電圧が低く、かつゲート・ドレイン間の耐圧
が高くなる。According to the second aspect of the invention, the surface of the second-conductivity-type semiconductor layer on the side of the trench serves as a channel, and a current flows between the source and the drain. At this time, since the gate thermal oxide film as the gate insulating film is thicker at the bottom of the trench than at the side of the trench, the threshold voltage is low and the gate-drain Withstand voltage increases.
【００２５】又、酸化速度が速い六方晶系単結晶炭化珪
素の（０００１）カーボン面をトレンチの底部とし、こ
の（０００１）カーボン面に対して酸化速度が遅い面を
トレンチの側部としたので一度の熱酸化工程によりトレ
ンチの側部と底部で厚さが異なるゲート熱酸化膜を形成
できる。Further, the (0001) carbon surface of hexagonal single crystal silicon carbide having a high oxidation rate is the bottom of the trench, and the surface of which the oxidation rate is slower than the (0001) carbon surface is the side portion of the trench. A single thermal oxidation process can form a gate thermal oxide film having different thicknesses on the side and bottom portions of the trench.
【００２６】請求項３に記載の発明によれば、請求項１
に記載の発明の作用に加え、単結晶炭化珪素の表面とト
レンチの側部とは４５°〜９０°の角度をなしているの
で、トレンチの側部と底部で厚さが大きく異なる熱酸化
膜を形成できる。According to the invention of claim 3, claim 1
In addition to the effect of the invention described in (1), since the surface of the single crystal silicon carbide and the side portion of the trench form an angle of 45 ° to 90 °, the thermal oxide film having a great difference in thickness between the side portion and the bottom portion of the trench. Can be formed.
【００２７】請求項４に記載の発明によれば、請求項２
に記載の発明の作用に加え、半導体層の表面とトレンチ
の側部とは４５°〜９０°の角度をなしているので、ト
レンチの側部と底部で厚さが大きく異なる熱酸化膜を形
成できる。According to the invention of claim 4, claim 2
In addition to the effect of the invention described in (1), since the surface of the semiconductor layer and the side of the trench form an angle of 45 ° to 90 °, a thermal oxide film having a greatly different thickness is formed on the side and the bottom of the trench. it can.
【００２８】請求項５に記載の発明によれば、請求項１
に記載の発明の作用に加え、トレンチの底部は単結晶炭
化珪素の表面に平行であるので、トレンチの側部と底部
で厚さが大きく異なる熱酸化膜を形成できる。According to the invention of claim 5, claim 1
In addition to the effect of the invention described in (1), since the bottom of the trench is parallel to the surface of the single crystal silicon carbide, it is possible to form a thermal oxide film having a great difference in thickness between the side and the bottom of the trench.
【００２９】請求項６に記載の発明によれば、請求項２
に記載の発明の作用に加え、トレンチの底部は半導体層
の表面に平行であるので、トレンチの側部と底部で厚さ
が大きく異なる熱酸化膜を形成できる。According to the invention of claim 6, claim 2
In addition to the effect of the invention described in (1), since the bottom of the trench is parallel to the surface of the semiconductor layer, it is possible to form a thermal oxide film having a thickness greatly different between the side and bottom of the trench.
【００３０】請求項９に記載の発明によれば、第１工程
により、六方晶系の単結晶炭化珪素よりなる第１導電型
の低抵抗層の上に、六方晶系の単結晶炭化珪素よりなる
第１導電型の高抵抗層を積層して当該高抵抗層の表面の
面方位が（０００１）カーボン面である半導体基板が形
成される。そして、第２工程により、半導体基板の表面
上に、表面の面方位が（０００１）カーボン面である六
方晶系の単結晶炭化珪素よりなる第２導電型の半導体層
が形成されるとともに、この半導体層内の所定領域に第
１導電型の半導体領域が形成される。さらに、第３工程
により、半導体領域と半導体層を貫通し半導体基板に達
し、側部および底部を有するトレンチが形成される。引
き続き、第４工程により、トレンチの内壁を熱酸化する
ことによりトレンチの側部での膜厚に比べトレンチの底
部での膜厚の方が厚いゲート絶縁膜としてのゲート熱酸
化膜が形成される。そして、第５工程により、トレンチ
内におけるゲート熱酸化膜の内側にゲート電極層が、半
導体層表面および半導体領域表面に第１の電極層が、半
導体基板の裏面側に第２の電極層が、それぞれ形成され
る。According to the ninth aspect of the present invention, in the first step, the hexagonal single crystal silicon carbide is formed on the first conductivity type low resistance layer made of the hexagonal single crystal silicon carbide. By laminating the first-conductivity-type high resistance layer, the semiconductor substrate is formed in which the surface orientation of the high resistance layer is the (0001) carbon surface. Then, in the second step, a second conductivity type semiconductor layer made of hexagonal single-crystal silicon carbide having a (0001) carbon plane is formed on the surface of the semiconductor substrate, and A first conductivity type semiconductor region is formed in a predetermined region in the semiconductor layer. Further, in the third step, a trench penetrating the semiconductor region and the semiconductor layer to reach the semiconductor substrate and having side portions and a bottom portion is formed. Subsequently, in the fourth step, the inner wall of the trench is thermally oxidized to form a gate thermal oxide film as a gate insulating film having a thicker film at the bottom of the trench than at the side of the trench. . Then, in the fifth step, the gate electrode layer is formed inside the gate thermal oxide film in the trench, the first electrode layer is formed on the semiconductor layer surface and the semiconductor region surface, and the second electrode layer is formed on the back surface side of the semiconductor substrate. Formed respectively.
【００３１】その結果、請求項２に記載の半導体装置が
製造される。As a result, the semiconductor device according to the second aspect is manufactured.
【００３２】[0032]
【実施例】以下、この発明を具体化した一実施例を図面
に従って説明する。図１に本実施例のトレンチゲート型
パワーＭＯＳＦＥＴ（縦型パワーＭＯＳＦＥＴ）の断面
図を示す。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a sectional view of a trench gate type power MOSFET (vertical power MOSFET) of this embodiment.
【００３３】低抵抗層としてのｎ+ 型単結晶ＳｉＣ基板
１は、六方晶系ＳｉＣ（０００１）カーボン面を表面と
し、かつ低抵抗でキャリア密度が５×１０18ｃｍ-3程度
である。このｎ+ 型単結晶ＳｉＣ基板１上に、高抵抗層
としてのｎ型エピタキシャル層２と半導体層としてのｐ
型エピタキシャル層３が順次積層されている。ｎ型エピ
タキシャル層２は、キャリア密度が１×１０16ｃｍ-3程
度で厚さが１０μｍ程度となっている。又、ｐ型エピタ
キシャル層３は、キャリア密度が１×１０17ｃｍ-3程度
で厚さが２μｍ程度となっており、該ｐ型エピタキシャ
ル層３の表面４が素子表面となっている。The n + type single crystal SiC substrate 1 as a low resistance layer has a hexagonal SiC (0001) carbon surface as a surface, has a low resistance and a carrier density of about 5 × 10 18 cm -3 . On the n + -type single crystal SiC substrate 1, an n-type epitaxial layer 2 as a high resistance layer and a p-type semiconductor layer as a semiconductor layer.
The type epitaxial layers 3 are sequentially stacked. The n-type epitaxial layer 2 has a carrier density of about 1 × 10 16 cm −3 and a thickness of about 10 μm. The p-type epitaxial layer 3 has a carrier density of about 1 × 10 17 cm −3 and a thickness of about 2 μm, and the surface 4 of the p-type epitaxial layer 3 serves as an element surface.
【００３４】本実施例では、ｎ+ 型単結晶ＳｉＣ基板１
とｎ型エピタキシャル層２とから半導体基板１４が構成
されている。ｐ型エピタキシャル層３の表面４における
所定領域には、半導体領域としてのｎ+ ソース領域５が
形成され、ｎ+ ソース領域５はキャリア濃度が１×１０
19ｃｍ-3程度で接合深さが０．５μｍ程度となってい
る。又、ｐ型エピタキシャル層３の表面４の所定位置に
トレンチ６が形成されている。このトレンチ６は、ｎ+
ソース領域５とｐ型エピタキシャル層３を貫通しｎ型エ
ピタキシャル層２に達し、ｐ型エピタキシャル層３の表
面に垂直な側面（側部）６ａおよびｐ型エピタキシャル
層３の表面に平行な底面（底部）６ｂを有する。In this embodiment, an n + type single crystal SiC substrate 1 is used.
And the n-type epitaxial layer 2 form a semiconductor substrate 14. An n + source region 5 as a semiconductor region is formed in a predetermined region on the surface 4 of the p-type epitaxial layer 3, and the n + source region 5 has a carrier concentration of 1 × 10 5.
The junction depth is about 0.5 μm at about 19 cm −3 . A trench 6 is formed at a predetermined position on the surface 4 of the p-type epitaxial layer 3. This trench 6 is n +
A side surface (side portion) 6a penetrating the source region 5 and the p-type epitaxial layer 3 to reach the n-type epitaxial layer 2 and perpendicular to the surface of the p-type epitaxial layer 3 and a bottom surface (bottom portion) parallel to the surface of the p-type epitaxial layer 3 ) 6b.
【００３５】トレンチ６の内部には、ゲート絶縁膜とし
てのゲート熱酸化膜７を介してゲート電極層８が配置さ
れている。ここで、ゲート熱酸化膜７は１１００℃で５
時間程度の一度の熱酸化工程により形成され、トレンチ
６の側面６ａに位置する厚さが５０ｎｍ程度の薄いゲー
ト熱酸化膜７ａと、トレンチ６の底面６ｂに位置する厚
さが３００ｎｍ程度の厚いゲート熱酸化膜７ｂからな
る。さらに、ゲート熱酸化膜７はｎ+ ソース領域５上に
も形成され、この領域におけるゲート熱酸化膜７ｃも厚
さが３００ｎｍ程度に厚くなっている。Inside the trench 6, a gate electrode layer 8 is arranged with a gate thermal oxide film 7 as a gate insulating film interposed. Here, the gate thermal oxide film 7 is 5 at 1100 ° C.
A thin gate thermal oxide film 7a having a thickness of about 50 nm located on the side surface 6a of the trench 6 and a thick gate having a thickness of about 300 nm located on the bottom surface 6b of the trench 6, which are formed by a single thermal oxidation process for about an hour. The thermal oxide film 7b is used. Further, the gate thermal oxide film 7 is also formed on the n + source region 5, and the gate thermal oxide film 7c in this region is also thickened to about 300 nm.
【００３６】又、ゲート電極層８は、ゲート熱酸化膜７
に接しリンをドープした第１のポリシリコン層８ａと第
２のポリシリコン層８ｂからなる。ゲート電極層８上に
は、厚さが１μｍ程度の層間絶縁膜９が配置されてい
る。さらに、層間絶縁膜９上を含めたｎ+ ソース領域５
の表面およびｐ型エピタキシャル層３の表面には、第１
の電極層としてのソース電極層１０が配置され、このソ
ース電極層１０はｎ+ ソース領域５とｐ型エピタキシャ
ル層３に共に接している。ｎ+ 型単結晶ＳｉＣ基板１の
裏面には、同基板１に接する第２の電極層としてのドレ
イン電極層１１が設けられている。The gate electrode layer 8 is the gate thermal oxide film 7
Of the first polysilicon layer 8a and the second polysilicon layer 8b which are in contact with each other and are doped with phosphorus. An interlayer insulating film 9 having a thickness of about 1 μm is arranged on the gate electrode layer 8. Furthermore, the n + source region 5 including the interlayer insulating film 9 is also included.
On the surface of p-type epitaxial layer 3 and the surface of p-type epitaxial layer 3.
A source electrode layer 10 is disposed as an electrode layer of, and the source electrode layer 10 is in contact with both the n + source region 5 and the p-type epitaxial layer 3. On the back surface of the n + -type single crystal SiC substrate 1, a drain electrode layer 11 as a second electrode layer that is in contact with the substrate 1 is provided.
【００３７】このトレンチゲート型パワーＭＯＳＦＥＴ
によれば、トレンチ６の側面６ａのゲート熱酸化膜７ａ
は薄いために閾電圧を低くでき（例えば２Ｖ）、しかも
トレンチ６の底面６ｂのゲート熱酸化膜７ｂは厚いため
にゲート・ドレイン間の耐圧を高く（例えば５００Ｖ以
上）できる。This trench gate type power MOSFET
According to the above, the gate thermal oxide film 7a on the side surface 6a of the trench 6 is formed.
Is thin, the threshold voltage can be lowered (for example, 2 V), and the gate thermal oxide film 7b on the bottom surface 6b of the trench 6 is thick, so that the breakdown voltage between the gate and the drain can be increased (for example, 500 V or more).
【００３８】このトレンチゲート型パワーＭＯＳＦＥＴ
の製造工程を、図２〜６を用いて、詳細に説明する。ま
ず、図２に示すように、表面の面方位が（０００１）カ
ーボン面である低抵抗のｎ+ 型単結晶ＳｉＣ基板１を用
意する。そして、そのｎ+ 型単結晶ＳｉＣ基板１の表面
に、キャリア密度が１×１０16ｃｍ-3程度で厚さが１０
μｍ程度のｎ型エピタキシャル層２と、キャリア密度が
１×１０17ｃｍ-3程度で厚さが２μｍ程度のｐ型エピタ
キシャル層３を順次積層する。This trench gate type power MOSFET
The manufacturing process of will be described in detail with reference to FIGS. First, as shown in FIG. 2, a low-resistance n + -type single-crystal SiC substrate 1 whose surface plane orientation is a (0001) carbon face is prepared. Then, on the surface of the n + type single crystal SiC substrate 1, the carrier density is about 1 × 10 16 cm −3 and the thickness is 10 × 10 16 cm −3.
An n-type epitaxial layer 2 having a thickness of about μm and a p-type epitaxial layer 3 having a carrier density of about 1 × 10 17 cm −3 and a thickness of about 2 μm are sequentially laminated.
【００３９】このようにして、ｎ+ 型単結晶ＳｉＣ基板
１とｎ型エピタキシャル層２とからなる半導体基板１４
を形成する。続いて、図３に示すように、ｐ型エピタキ
シャル層３に対しマスク材１２を用いてイオン注入法に
より表面のキャリア濃度が１×１０19ｃｍ-3程度で接合
深さが０．５μｍ程度のｎ+ ソース領域５を形成する。Thus, the semiconductor substrate 14 composed of the n + type single crystal SiC substrate 1 and the n type epitaxial layer 2 is formed.
To form. Subsequently, as shown in FIG. 3, a mask material 12 is used for the p-type epitaxial layer 3 by an ion implantation method so that the carrier concentration on the surface is about 1 × 10 19 cm −3 and the junction depth is about 0.5 μm. The n + source region 5 is formed.
【００４０】次に、図４に示すように、マスク材１３を
用いて反応性イオンエッチング（ＲＩＥ）法により、ｎ
+ ソース領域５とｐ型エピタキシャル層３を貫通しｎ型
エピタキシャル層２に達するトレンチ６を形成する。こ
のトレンチ６は、ｐ型エピタキシャル層３の表面に垂直
な側面（側部）６ａおよびｐ型エピタキシャル層３の表
面に平行な底面（底部）６ｂを有する。Next, as shown in FIG. 4, n is formed by reactive ion etching (RIE) using the mask material 13.
A trench 6 penetrating the source region 5 and the p-type epitaxial layer 3 and reaching the n-type epitaxial layer 2 is formed. The trench 6 has a side surface (side portion) 6 a perpendicular to the surface of the p-type epitaxial layer 3 and a bottom surface (bottom portion) 6 b parallel to the surface of the p-type epitaxial layer 3.
【００４１】続いて、図５に示すように、マスク材１３
を除去した後、熱酸化法によりゲート熱酸化膜７を１１
００℃で５時間程度の一度の熱酸化工程により形成す
る、この熱酸化によりトレンチ６の側面６ａに位置する
厚さが５０ｎｍ程度の薄いゲート熱酸化膜７ａと、トレ
ンチ６の底面６ｂに位置する厚さが３００ｎｍ程度の厚
いゲート熱酸化膜７ｂが形成される。さらに、ｎ+ ソー
ス領域５上には厚さが３００ｎｍ程度の厚いゲート熱酸
化膜７ｃが形成される。Subsequently, as shown in FIG. 5, the mask material 13
After removing the film, the gate thermal oxide film 7 is removed by thermal oxidation.
It is formed by a single thermal oxidation process at 00 ° C. for about 5 hours. Due to this thermal oxidation, a thin gate thermal oxide film 7a with a thickness of about 50 nm located on the side surface 6a of the trench 6 and a bottom surface 6b of the trench 6 are formed. A thick gate thermal oxide film 7b having a thickness of about 300 nm is formed. Further, a thick gate thermal oxide film 7c having a thickness of about 300 nm is formed on n + source region 5.
【００４２】続いて、図６に示すように、トレンチ６内
を、第１及び第２ポリシリコン層８ａ，８ｂにより順次
埋め戻す。しかる後、図１に示すように、第１及び第２
ポリシリコン層８ａ，８ｂ上を含めたゲート熱酸化膜７
上に、ＣＶＤ法により層間絶縁層９を形成し、ソースコ
ンタクト予定位置のｎ+ ソース領域５とｐ型エピタキシ
ャル層３の表面上にあるゲート熱酸化膜７と層間絶縁層
９を除去する。その後、ｎ+ ソース領域５とｐ型エピタ
キシャル層３及び層間絶縁層９上にソース電極層１０を
形成するとともに、ｎ+ 型単結晶ＳｉＣ基板１の裏面に
ドレイン電極層１１を形成し、トレンチゲート型ＳｉＣ
パワーＭＯＳＦＥＴを完成する。Then, as shown in FIG. 6, the trench 6 is sequentially backfilled with the first and second polysilicon layers 8a and 8b. Then, as shown in FIG. 1, the first and second
Gate thermal oxide film 7 including on the polysilicon layers 8a and 8b
An interlayer insulating layer 9 is formed thereon by the CVD method, and the gate thermal oxide film 7 and the interlayer insulating layer 9 on the surface of the n + source region 5 at the planned source contact position and the p-type epitaxial layer 3 are removed. Then, the source electrode layer 10 is formed on the n + source region 5, the p-type epitaxial layer 3 and the interlayer insulating layer 9, and the drain electrode layer 11 is formed on the back surface of the n + -type single crystal SiC substrate 1 to form a trench gate. Type SiC
Complete the power MOSFET.
【００４３】このように本実施例のトレンチゲート型パ
ワーＭＯＳＦＥＴでは、ｎ+ 型単結晶ＳｉＣ基板１（第
１導電型の低抵抗層）とｎ+ 型単結晶ＳｉＣ基板１上に
形成されたｎ型エピタキシャル層２（第１導電型の高抵
抗層）の二層にて構成され、かつｎ型エピタキシャル層
２の表面の面方位が（０００１）カーボン面である六方
晶系の単結晶炭化珪素よりなる半導体基板１４と、半導
体基板１４の表面上に形成され、表面の面方位が（００
０１）カーボン面である六方晶系の単結晶炭化珪素より
なるｐ型エピタキシャル層３（第２導電型の半導体層）
と、ｐ型エピタキシャル層３内の所定領域に形成された
ｎ+ ソース領域５（第１導電型の半導体領域）と、ｎ+
ソース領域５とｐ型エピタキシャル層３を貫通し半導体
基板１４に達し、ｐ型エピタキシャル層３の表面に垂直
な側面（側部）６ａおよびｐ型エピタキシャル層３の表
面に平行な底面（底部）６ｂを有するトレンチ６と、ト
レンチ６の側面６ａおよび底面６ｂに形成され、かつト
レンチ６の側面６ａでの膜厚に比べトレンチ６の底面６
ｂでの膜厚の方が厚いゲート絶縁膜としてのゲート熱酸
化膜７と、トレンチ６内におけるゲート熱酸化膜７の内
側に形成されたゲート電極層８と、ｐ型エピタキシャル
層３表面およびｎ+ ソース領域５表面に形成されたソー
ス電極層１０（第１の電極層）と、半導体基板１４の裏
面側に形成されたドレイン電極層１１（第２の電極層）
とを備えている。As described above, in the trench gate type power MOSFET of this embodiment, the n + type single crystal SiC substrate 1 (first conductivity type low resistance layer) and the n + type single crystal SiC substrate 1 are formed. From a hexagonal single-crystal silicon carbide having two layers of the n-type epitaxial layer 2 (first-conductivity-type high-resistance layer), and the surface orientation of the n-type epitaxial layer 2 is the (0001) carbon face. Formed on the surface of the semiconductor substrate 14, and the surface orientation of the surface is (00
01) p type epitaxial layer 3 (second conductivity type semiconductor layer) made of hexagonal single crystal silicon carbide which is a carbon surface
When, n + source region formed in a predetermined region of the p-type epitaxial layer 35 (the semiconductor region of the first conductivity type), n +
A side surface (side portion) 6a penetrating the source region 5 and the p-type epitaxial layer 3 to reach the semiconductor substrate 14 and perpendicular to the surface of the p-type epitaxial layer 3 and a bottom surface (bottom portion) 6b parallel to the surface of the p-type epitaxial layer 3. And the bottom surface 6 of the trench 6 which is formed on the side surface 6a and the bottom surface 6b of the trench 6 and has a thickness smaller than that of the side surface 6a of the trench 6.
The gate thermal oxide film 7 serving as a gate insulating film having a larger thickness at b, the gate electrode layer 8 formed inside the gate thermal oxide film 7 in the trench 6, the surface of the p-type epitaxial layer 3 and the n-type + Source electrode layer 10 (first electrode layer) formed on the surface of the source region 5 and drain electrode layer 11 (second electrode layer) formed on the back surface side of the semiconductor substrate 14.
It has and.
【００４４】よって、トレンチ６の側面６ａでのｐ型エ
ピタキシャル層３の表面がチャネルとなって、ソース・
ドレイン間に電流が流れる。この際、ゲート絶縁膜とし
てのゲート熱酸化膜７はトレンチ６の側面６ａでの膜厚
に比べトレンチ６の底面６ｂでの膜厚の方が厚くなって
いるので、閾電圧が低く、かつゲート・ドレイン間の耐
圧が高くなる。つまり、トレンチ６の側面６ａのゲート
熱酸化膜７ａは薄いために閾電圧を低くでき（例えば２
Ｖ）、しかもトレンチ６の底面６ｂのゲート熱酸化膜７
ｂは厚いためにゲート・ドレイン間の耐圧を高く（例え
ば５００Ｖ以上）できるとともに寄生容量が低減でき高
速動作が可能になる。又、素子表面の酸化膜７ｃが厚い
ため、ソース・ゲート間の耐圧が向上する。さらに、ト
レンチ構造を採用しているのでオン抵抗を低くできる。
又、酸化速度が速い六方晶系単結晶炭化珪素の（０００
１）カーボン面をトレンチ６の底面６ｂとし、この（０
００１）カーボン面に垂直で酸化速度が遅い面をトレン
チ６の側面６ａとしたので一度の熱酸化工程によりトレ
ンチ６の側面６ａと底面６ｂで厚さが大きく異なる熱酸
化膜７を形成できる。即ち、ゲート酸化膜の膜厚分布を
一度の熱酸化工程により達成することができる。その結
果、製造コストを低くできるとともに製造歩留りを向上
させることができる。Therefore, the surface of the p-type epitaxial layer 3 on the side surface 6a of the trench 6 becomes a channel,
Current flows between the drains. At this time, since the gate thermal oxide film 7 as the gate insulating film is thicker on the bottom surface 6b of the trench 6 than on the side surface 6a of the trench 6, the threshold voltage is low and・ High breakdown voltage between drains. That is, since the gate thermal oxide film 7a on the side surface 6a of the trench 6 is thin, the threshold voltage can be lowered (for example, 2
V) and the gate thermal oxide film 7 on the bottom surface 6b of the trench 6
Since b is thick, the breakdown voltage between the gate and the drain can be increased (for example, 500 V or more), the parasitic capacitance can be reduced, and high speed operation can be performed. Further, since the oxide film 7c on the element surface is thick, the breakdown voltage between the source and gate is improved. Further, since the trench structure is adopted, the on resistance can be lowered.
In addition, hexagonal single crystal silicon carbide (000
1) The carbon surface is used as the bottom surface 6b of the trench 6, and this (0
001) Since the side face 6a of the trench 6 is perpendicular to the carbon face and has a slow oxidation rate, the side face 6a of the trench 6 and the bottom face 6b of the trench 6 can have a greatly different thermal oxide film 7 formed by a single thermal oxidation process. That is, the film thickness distribution of the gate oxide film can be achieved by one thermal oxidation step. As a result, the manufacturing cost can be reduced and the manufacturing yield can be improved.
【００４５】又、六方晶系の単結晶炭化珪素よりなるｎ
+ 型単結晶ＳｉＣ基板１（第１導電型の低抵抗層）の上
に、六方晶系の単結晶炭化珪素よりなるｎ型エピタキシ
ャル層２（第１導電型の高抵抗層）を積層してｎ型エピ
タキシャル層２の表面の面方位が（０００１）カーボン
面である半導体基板１４を形成し（第１工程）、半導体
基板１４の表面上に、表面の面方位が（０００１）カー
ボン面である六方晶系の単結晶炭化珪素よりなるｐ型エ
ピタキシャル層３（第２導電型の半導体層）を形成する
とともに、このｐ型エピタキシャル層３内の所定領域に
ｎ+ ソース領域５（第１導電型の半導体領域）を形成し
（第２工程）、ｎ+ ソース領域５とｐ型エピタキシャル
層３を貫通し半導体基板１４に達し、かつｐ型エピタキ
シャル層３の表面に垂直な側面６ａおよびｐ型エピタキ
シャル層３の表面に平行な底面６ｂを有するトレンチ６
を形成し（第３工程）、トレンチ６の内壁を熱酸化する
ことによりトレンチ６の側面６ａでの膜厚に比べトレン
チ６の底面６ｂでの膜厚の方が厚いゲート絶縁膜として
のゲート熱酸化膜７を形成し（第４工程）、トレンチ６
内におけるゲート熱酸化膜７の内側にゲート電極層８
を、ｐ型エピタキシャル層３表面およびｎ+ ソース領域
５表面にソース電極層１０（第１の電極層）を、半導体
基板１４の裏面側にドレイン電極層１１（第２の電極
層）を、それぞれ形成した（第５工程）。Further, n made of hexagonal single crystal silicon carbide
An n-type epitaxial layer 2 (first conductivity type high resistance layer) made of hexagonal single crystal silicon carbide is laminated on a + type single crystal SiC substrate 1 (first conductivity type low resistance layer). A semiconductor substrate 14 in which the surface orientation of the n-type epitaxial layer 2 is the (0001) carbon surface is formed (first step), and the surface orientation of the surface is the (0001) carbon surface on the surface of the semiconductor substrate 14. A p-type epitaxial layer 3 (second conductivity type semiconductor layer) made of hexagonal single crystal silicon carbide is formed, and an n + source region 5 (first conductivity type) is formed in a predetermined region in the p-type epitaxial layer 3. (Second semiconductor region) is formed (second step), penetrates the n + source region 5 and the p-type epitaxial layer 3, reaches the semiconductor substrate 14, and is perpendicular to the surface of the p-type epitaxial layer 3 and the p-type epitaxial layer 3 is formed. On the surface of layer 3 Trench 6 having a row bottom surface 6b
Is formed (third step), and the inner wall of the trench 6 is thermally oxidized, so that the film thickness on the bottom surface 6b of the trench 6 is larger than that on the side surface 6a of the trench 6 as a gate insulating film. The oxide film 7 is formed (fourth step), and the trench 6 is formed.
The gate electrode layer 8 is formed inside the gate thermal oxide film 7 inside.
The source electrode layer 10 (first electrode layer) is provided on the surface of the p-type epitaxial layer 3 and the n + source region 5, and the drain electrode layer 11 (second electrode layer) is provided on the back surface side of the semiconductor substrate 14, respectively. Formed (fifth step).
【００４６】その結果、上述したトレンチゲート型パワ
ーＭＯＳＦＥＴが製造される。尚、この発明は上記実施
例に限定されるものではなく、例えば、ｎチャネル型の
みについて説明したが、半導体型のｎとｐを入れ換えた
ｐチャネル型においても同じ効果が得られることは言う
までもない。また、トレンチにおける熱酸化膜の膜厚
も、実施例中で用いた膜厚（側面を５０ｎｍ程度、底面
を３００ｎｍ程度）に限定されるものではなく、トレン
チ側部の膜厚よりもトレンチ底部の膜厚の方が厚い構成
であればどのような構成でも良い。As a result, the above-mentioned trench gate type power MOSFET is manufactured. The present invention is not limited to the above-described embodiment, and for example, only the n-channel type has been described, but it goes without saying that the same effect can be obtained also in the p-channel type in which semiconductor type n and p are exchanged. . Further, the film thickness of the thermal oxide film in the trench is not limited to the film thickness used in the example (side surface is about 50 nm, bottom surface is about 300 nm), and the film thickness of the trench bottom portion is larger than that of the trench side portion. Any structure may be used as long as the film thickness is thicker.
【００４７】また、トレンチ６の側面（側部）６ａは
（０００１）カーボン面に垂直である必要はなく、図７
や図８のように、斜状となっていてもよい。又、トレン
チ６の底面（底部）６ｂも（０００１）カーボン面に平
行である必要はなく、例えば、図８や図９のように、丸
みを持った底部としてもよい。Further, the side surface (side portion) 6a of the trench 6 does not need to be perpendicular to the (0001) carbon surface, as shown in FIG.
As shown in FIG. 8 and FIG. Further, the bottom surface (bottom portion) 6b of the trench 6 does not have to be parallel to the (0001) carbon surface, and may have a rounded bottom portion as shown in FIGS. 8 and 9, for example.
【００４８】図１０には、トレンチ６の側面（側部）６
ａと（０００１）カーボン面とでなす角度θを変えた場
合における酸化膜の膜厚Ｔoxを測定した結果の一例を示
す。つまり、図１１で示したように、（０００１）カー
ボン面とでなす角度θを有する側面での酸化膜の厚さを
調べたものである。この図１０により、側面の角度θは
４５°〜９０°とすることが望ましく、さらに詳しく
は、側面の角度θを６０°〜９０°とすることがさらに
好ましいことが分かる。即ち、（０００１）カーボン面
には約３１０ｎｍの膜厚の酸化膜が形成されるのに対
し、角度θ＝４５〜９０°とすることにより側面の酸化
膜の膜厚を１００ｎｍ以下に薄くでき、（０００１）カ
ーボン面での膜厚と側面での膜厚の差を大きくとること
ができる。さらに、角度θ＝６０〜９０°とすることに
より側面の酸化膜の膜厚を７０ｎｍ程度に薄くでき、
（０００１）カーボン面での膜厚と側面での膜厚の差を
更に大きくとることができる。FIG. 10 shows the side surface (side portion) 6 of the trench 6.
An example of the result of measuring the film thickness Tox of the oxide film when the angle θ formed between a and the (0001) carbon surface is changed is shown. That is, as shown in FIG. 11, the thickness of the oxide film on the side surface having the angle θ with the (0001) carbon surface was examined. From FIG. 10, it is understood that the side surface angle θ is preferably 45 ° to 90 °, and more specifically, the side surface angle θ is more preferably 60 ° to 90 °. That is, while an oxide film having a film thickness of about 310 nm is formed on the (0001) carbon surface, the film thickness of the oxide film on the side surface can be reduced to 100 nm or less by setting the angle θ = 45 to 90 °. It is possible to make a large difference between the film thickness on the (0001) carbon surface and the film thickness on the side surface. Further, by setting the angle θ = 60 to 90 °, the thickness of the oxide film on the side surface can be reduced to about 70 nm,
The difference between the film thickness on the (0001) carbon surface and the film thickness on the side surface can be further increased.
【００４９】さらに、トレンチ６の側面６ａと（０００
１）カーボン面とでなす角度θを調整することにより、
トレンチ６の側面６ａでの熱酸化膜の膜厚「１」に対し
て底面６ｂでの熱酸化膜の膜厚が「２」以上となる比率
にするようにしてもよい（（底面６ｂでの熱酸化膜の膜
厚／側面６ａでの熱酸化膜の膜厚）≧２）。Further, the side surfaces 6a of the trench 6 and (000
1) By adjusting the angle θ formed with the carbon surface,
The thickness of the thermal oxide film on the side surface 6a of the trench 6 may be set to be "2" or more with respect to the thickness "1" of the thermal oxide film on the side surface 6a ((on the bottom surface 6b). Thickness of thermal oxide film / thickness of thermal oxide film on side surface 6a) ≧ 2).
【００５０】又、トレンチ６の側面（側部）６ａでの熱
酸化膜の膜厚は１０〜１００ｎｍとするのが好ましい。
又、ソース電極層１０は、ｎ+ ソース領域５とｐ型エピ
タキシャル層３の両方に接する必要はなく、少なくとも
ｎ+ ソース領域５上に形成されればよい。The thickness of the thermal oxide film on the side surface (side portion) 6a of the trench 6 is preferably 10 to 100 nm.
Further, the source electrode layer 10 does not have to be in contact with both the n + source region 5 and the p-type epitaxial layer 3, and may be formed at least on the n + source region 5.
【００５１】[0051]
【発明の効果】以上詳述したように 請求項１，７，８
に記載の発明によれば、製造が容易で、トレンチの内部
で酸化膜厚さが異なる半導体装置を提供できる。As described in detail above, the present invention can be applied to any one of claims 1, 7, and 8.
According to the invention described in (1), it is possible to provide a semiconductor device which is easy to manufacture and has different oxide film thicknesses inside the trench.
【００５２】請求項２，９に記載の発明によれば、請求
項１に記載の発明の効果に加え、閾電圧が低く、耐圧が
高い半導体装置及びその製造方法を提供できる。請求項
３，５に記載の発明によれば、請求項１に記載の発明の
効果に加え、トレンチの側部と底部で厚さが大きく異な
る熱酸化膜を形成することができる。According to the invention described in claims 2 and 9, in addition to the effect of the invention described in claim 1, it is possible to provide a semiconductor device having a low threshold voltage and a high breakdown voltage, and a manufacturing method thereof. According to the invention described in claims 3 and 5, in addition to the effect of the invention described in claim 1, it is possible to form a thermal oxide film having a greatly different thickness between the side portion and the bottom portion of the trench.
【００５３】請求項４，６に記載の発明によれば、請求
項２に記載の発明の効果に加え、トレンチの側部と底部
で厚さが大きく異なる熱酸化膜を形成することができ
る。According to the fourth and sixth aspects of the invention, in addition to the effect of the second aspect of the invention, it is possible to form a thermal oxide film having a great difference in thickness between the side portion and the bottom portion of the trench.
【図１】実施例の半導体装置の断面図。FIG. 1 is a sectional view of a semiconductor device according to an embodiment.
【図２】実施例の半導体装置の製造工程を説明するため
の断面図。FIG. 2 is a cross-sectional view for explaining the manufacturing process of the semiconductor device of the example.
【図３】実施例の半導体装置の製造工程を説明するため
の断面図。FIG. 3 is a cross-sectional view for explaining the manufacturing process of the semiconductor device of the example.
【図４】実施例の半導体装置の製造工程を説明するため
の断面図。FIG. 4 is a cross-sectional view for explaining the manufacturing process of the semiconductor device of the example.
【図５】実施例の半導体装置の製造工程を説明するため
の断面図。FIG. 5 is a cross-sectional view for explaining the manufacturing process of the semiconductor device of the example.
【図６】実施例の半導体装置の製造工程を説明するため
の断面図。FIG. 6 is a cross-sectional view for explaining the manufacturing process of the semiconductor device of the example.
【図７】応用例の半導体装置の断面図。FIG. 7 is a cross-sectional view of a semiconductor device of an application example.
【図８】応用例の半導体装置の断面図。FIG. 8 is a cross-sectional view of a semiconductor device of an application example.
【図９】応用例の半導体装置の断面図。FIG. 9 is a cross-sectional view of a semiconductor device of an application example.
【図１０】側面形成角度に対する酸化膜の膜厚を測定し
た結果を示すグラフ。FIG. 10 is a graph showing the results of measuring the thickness of an oxide film with respect to the side surface formation angle.
【図１１】測定条件を説明するための説明図。FIG. 11 is an explanatory diagram for explaining measurement conditions.
【図１２】従来の半導体装置の断面図。FIG. 12 is a sectional view of a conventional semiconductor device.
【図１３】従来の半導体装置の製造工程を説明するため
の断面図。FIG. 13 is a cross-sectional view for explaining a conventional semiconductor device manufacturing process.
【図１４】従来の半導体装置の製造工程を説明するため
の断面図。FIG. 14 is a cross-sectional view for explaining the conventional manufacturing process of the semiconductor device.
【図１５】従来の半導体装置の製造工程を説明するため
の断面図。FIG. 15 is a cross-sectional view for explaining the conventional manufacturing process of the semiconductor device.
【図１６】従来の半導体装置の製造工程を説明するため
の断面図。FIG. 16 is a cross-sectional view for explaining a conventional semiconductor device manufacturing process.
【図１７】従来の半導体装置の製造工程を説明するため
の断面図。FIG. 17 is a cross-sectional view for explaining a conventional semiconductor device manufacturing process.
【図１８】従来の半導体装置の製造工程を説明するため
の断面図。FIG. 18 is a cross-sectional view for explaining the manufacturing process of the conventional semiconductor device.
【図１９】従来の半導体装置の製造工程を説明するため
の断面図。FIG. 19 is a cross-sectional view for explaining the conventional manufacturing process of the semiconductor device.
【図２０】従来の半導体装置の製造工程を説明するため
の断面図。FIG. 20 is a cross-sectional view for explaining a conventional semiconductor device manufacturing process.
【図２１】従来の半導体装置の製造工程を説明するため
の断面図。FIG. 21 is a cross-sectional view for explaining the manufacturing process of the conventional semiconductor device.
１…低抵抗層としてのｎ+ 型単結晶ＳｉＣ基板、２…高
抵抗層としてのｎ型エピタキシャル層、３…半導体層と
してのｐ型エピタキシャル層、５…半導体領域としての
ｎ+ ソース領域、６…トレンチ、６ａ…側面（側部）、
６ｂ…底面（底部）、７…ゲート熱酸化膜、８…ゲート
電極層、１０…第１の電極層としてのソース電極層、１
１…第２の電極層としてのドレイン電極層、１４…半導
体基板DESCRIPTION OF SYMBOLS 1 ... n + type single crystal SiC substrate as a low resistance layer, 2 ... n type epitaxial layer as a high resistance layer, 3 ... p type epitaxial layer as a semiconductor layer, 5 ... n + source region as a semiconductor region, 6 ... Trench, 6a ... Side (side),
6b ... Bottom (bottom), 7 ... Gate thermal oxide film, 8 ... Gate electrode layer, 10 ... Source electrode layer as first electrode layer, 1
1 ... Drain electrode layer as second electrode layer, 14 ... Semiconductor substrate
フロントページの続き (72)発明者 宮嶋 健 愛知県刈谷市昭和町１丁目１番地 日本 電装 株式会社 内 (72)発明者 夫馬 弘雄 愛知県愛知郡長久手町大字長湫字横道41 番地の１株式会社 豊田中央研究所 内 (72)発明者 加納 浩之 愛知県愛知郡長久手町大字長湫字横道41 番地の１株式会社 豊田中央研究所 内 (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 29/78 Front page continuation (72) Ken Miyajima, 1-1, Showa-cho, Kariya city, Aichi Prefecture, Nihon Denso Co., Ltd. Central Research Laboratory (72) Inventor Hiroyuki Kano 1 Nagatoge-cho, Aichi-gun, Aichi-gun, Nagakage 41 Yokomichi 1 Toyota Corporation Central Research Laboratory (58) Fields investigated (Int.Cl. 7 , DB name) H01L 29 / 78
Claims (9)
である六方晶系の単結晶炭化珪素と、 前記単結晶炭化珪素に形成され、側部および底部を有す
るトレンチと、 前記トレンチの側部および底部に形成され、かつトレン
チの側部での膜厚に比べトレンチの底部での膜厚の方が
厚い熱酸化膜とを備えたことを特徴とする半導体装置。1. A hexagonal single crystal silicon carbide having a (0001) carbon surface as a surface orientation, a trench formed in the single crystal silicon carbide and having a side portion and a bottom portion, and a side portion of the trench. And a thermal oxide film which is formed on the bottom and is thicker at the bottom of the trench than at the side of the trench.
に形成された第１導電型の高抵抗層の二層にて構成さ
れ、かつ前記高抵抗層の表面の面方位が（０００１）カ
ーボン面である六方晶系の単結晶炭化珪素よりなる半導
体基板と、 前記半導体基板の表面上に形成され、表面の面方位が
（０００１）カーボン面である六方晶系の単結晶炭化珪
素よりなる第２導電型の半導体層と、 前記半導体層内の所定領域に形成された第１導電型の半
導体領域と、 前記半導体領域と半導体層を貫通し前記半導体基板に達
し、側部および底部を有するトレンチと、 前記トレンチの側部および底部に形成され、かつトレン
チの側部での膜厚に比べトレンチの底部での膜厚の方が
厚いゲート絶縁膜としてのゲート熱酸化膜と、 前記トレンチ内における前記ゲート熱酸化膜の内側に形
成されたゲート電極層と、 少なくとも前記半導体領域表面に形成された第１の電極
層と、 前記半導体基板の裏面側に形成された第２の電極層とを
備えたことを特徴とする半導体装置。2. A low resistance layer of the first conductivity type and a high resistance layer of the first conductivity type formed on the low resistance layer, and the surface orientation of the surface of the high resistance layer is A semiconductor substrate made of hexagonal single-crystal silicon carbide having a (0001) carbon face, and a hexagonal single-crystal carbon having a (0001) carbon face formed on the surface of the semiconductor substrate. A second conductivity type semiconductor layer made of silicon; a first conductivity type semiconductor region formed in a predetermined region in the semiconductor layer; a semiconductor region penetrating the semiconductor region and the semiconductor layer to reach the semiconductor substrate; A trench having a bottom portion, and a gate thermal oxide film as a gate insulating film formed on the side portion and the bottom portion of the trench and having a thicker film thickness at the bottom portion of the trench than at the side portion of the trench, The gate in the trench A gate electrode layer formed inside the oxide film; a first electrode layer formed at least on the surface of the semiconductor region; and a second electrode layer formed on the back surface side of the semiconductor substrate. Characteristic semiconductor device.
チの側部とは４５°〜９０°の角度をなす請求項１に記
載の半導体装置。3. The semiconductor device according to claim 1, wherein a surface of the single crystal silicon carbide and a side portion of the trench form an angle of 45 ° to 90 °.
部とは４５°〜９０°の角度をなす請求項２に記載の半
導体装置。4. The semiconductor device according to claim 2, wherein a surface of the semiconductor layer and a side portion of the trench form an angle of 45 ° to 90 °.
素の表面に平行である請求項１に記載の半導体装置。5. The semiconductor device according to claim 1, wherein the bottom of the trench is parallel to the surface of the single crystal silicon carbide.
面に平行である請求項２に記載の半導体装置。6. The semiconductor device according to claim 2, wherein the bottom of the trench is parallel to the surface of the semiconductor layer.
「１」に対し底部での熱酸化膜の膜厚が「２」以上の比
率である請求項１または２に記載の半導体装置。7. The semiconductor according to claim 1, wherein the film thickness of the thermal oxide film at the side of the trench is “1” and the film thickness of the thermal oxide film at the bottom is “2” or more. apparatus.
は１０〜１００ｎｍである請求項１または２に記載の半
導体装置。8. The semiconductor device according to claim 1, wherein the thermal oxide film on the side of the trench has a film thickness of 10 to 100 nm.
導電型の低抵抗層の上に、六方晶系の単結晶炭化珪素よ
りなる第１導電型の高抵抗層を積層して当該高抵抗層の
表面の面方位が（０００１）カーボン面である半導体基
板を形成する第１工程と、 前記半導体基板の表面上に、表面の面方位が（０００
１）カーボン面である六方晶系の単結晶炭化珪素よりな
る第２導電型の半導体層を形成するとともに、この半導
体層内の所定領域に第１導電型の半導体領域を形成する
第２工程と、 前記半導体領域と半導体層を貫通し前記半導体基板に達
し、側部および底部を有するトレンチを形成する第３工
程と、 前記トレンチの内壁を熱酸化することによりトレンチの
側部での膜厚に比べトレンチの底部での膜厚の方が厚い
ゲート絶縁膜としてのゲート熱酸化膜を形成する第４工
程と、 前記トレンチ内における前記ゲート熱酸化膜の内側にゲ
ート電極層を、前記半導体層表面および半導体領域表面
に第１の電極層を、前記半導体基板の裏面側に第２の電
極層を、それぞれ形成する第５工程とを備えたことを特
徴とする半導体装置の製造方法。9. A first hexagonal single crystal silicon carbide
A semiconductor in which a first conductivity type high resistance layer made of hexagonal single-crystal silicon carbide is laminated on a conductivity type low resistance layer, and the surface orientation of the high resistance layer is a (0001) carbon plane. A first step of forming a substrate, and a surface orientation of the surface is (000
1) A second step of forming a second conductivity type semiconductor layer made of hexagonal single crystal silicon carbide which is a carbon surface, and forming a first conductivity type semiconductor region in a predetermined region in the semiconductor layer. A third step of penetrating the semiconductor region and the semiconductor layer to reach the semiconductor substrate and forming a trench having side portions and a bottom portion; and thermal oxidation of an inner wall of the trench to obtain a film thickness at a side portion of the trench. A fourth step of forming a gate thermal oxide film as a gate insulating film having a thicker film thickness at the bottom of the trench, and a gate electrode layer inside the gate thermal oxide film in the trench, and a semiconductor layer surface. And a fifth step of forming a first electrode layer on the front surface of the semiconductor region and a second electrode layer on the back surface side of the semiconductor substrate, respectively.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP07202695A JP3471473B2 (en) | 1994-04-06 | 1995-03-29 | Semiconductor device and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6879094 | 1994-04-06 | ||
| JP6-68790 | 1994-04-06 | ||
| JP07202695A JP3471473B2 (en) | 1994-04-06 | 1995-03-29 | Semiconductor device and manufacturing method thereof |
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| Publication Number | Publication Date |
|---|---|
| JPH07326755A JPH07326755A (en) | 1995-12-12 |
| JP3471473B2 true JP3471473B2 (en) | 2003-12-02 |
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