JP3424572B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP3424572B2 JP3424572B2 JP31948198A JP31948198A JP3424572B2 JP 3424572 B2 JP3424572 B2 JP 3424572B2 JP 31948198 A JP31948198 A JP 31948198A JP 31948198 A JP31948198 A JP 31948198A JP 3424572 B2 JP3424572 B2 JP 3424572B2
- Authority
- JP
- Japan
- Prior art keywords
- gate
- region
- source
- trench
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 20
- 210000000746 body region Anatomy 0.000 claims description 18
- 150000004767 nitrides Chemical class 0.000 description 8
- 239000000758 substrate Substances 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thyristors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置、特にト
レンチゲート型半導体装置の構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to the structure of a trench gate type semiconductor device.
【０００２】[0002]
【従来の技術】従来より、トレンチゲート型の半導体が
知られている。2. Description of the Related Art Conventionally, a trench gate type semiconductor has been known.
【０００３】図３には、従来のトレンチゲート型ＩＧＢ
Ｔ（Insulated Gate Bipolar Transister）の断面図
（ａ）及び平面図（ｂ）が示されている。なお、（ｂ）
の平面図は説明の都合上、上部のソース電極及び絶縁膜
を取り去った状態を示している。FIG. 3 shows a conventional trench gate type IGB.
A sectional view (a) and a plan view (b) of a T (Insulated Gate Bipolar Transister) are shown. Note that (b)
For convenience of explanation, the plan view of 1 shows a state in which the upper source electrode and the insulating film are removed.
【０００４】図において、ドレイン電極１０の上部にｐ
＋基板１２が設けられ、ｐ＋基板１２の上部にｎドリフ
ト領域１４が設けられる。ｎドリフト領域１４の上部に
はチャネルが形成されるｐボディ領域２０が設けられ、
ｐボディ領域２０を挟むようにトレンチ内にゲート電極
１８が形成される。ゲート電極１８はゲート酸化膜１６
で絶縁されている。また、ｐボディ領域１４の一部にｎ
＋ソース領域２２が設けられ、上部の絶縁膜２４にはこ
のｎ＋ソース領域２２に電圧を印加するためのコンタク
ト開口部が形成されている。コンタクト開口部の開口幅
はｄ１である。In the drawing, p is formed on the drain electrode 10.
A + substrate 12 is provided, and an n drift region 14 is provided on the p + substrate 12. A p body region 20 in which a channel is formed is provided on the n drift region 14,
Gate electrode 18 is formed in the trench so as to sandwich p body region 20. The gate electrode 18 is the gate oxide film 16
Is insulated with. In addition, in a part of the p body region 14, n
A + source region 22 is provided, and a contact opening for applying a voltage to the n + source region 22 is formed in the upper insulating film 24. The opening width of the contact opening is d1.
【０００５】ここで、（ｂ）の平面図に示すように、ｎ
＋ソース領域２２のみならずｐボディ領域２０も素子の
表面まで延在させているが、これは両領域にまたがる金
属層を被着することによりソースとボディを短絡させ、
素子の動作中に寄生バイポーラトランジスタがオンする
のを防ぐためである。Here, as shown in the plan view of FIG.
Not only the + source region 22 but also the p body region 20 are extended to the surface of the device, which short-circuits the source and the body by depositing a metal layer extending over both regions,
This is to prevent the parasitic bipolar transistor from turning on during the operation of the device.
【０００６】なお、特開平９−１０２６０６号公報に
も、上述した半導体素子に類似したトレンチ型ＭＯＳＦ
ＥＴが記載されている。Incidentally, Japanese Patent Laid-Open No. 9-102606 also discloses a trench type MOSF similar to the above-mentioned semiconductor element.
ET is described.
【０００７】[0007]
【発明が解決しようとする課題】しかしながら、上記従
来の半導体装置では、ｐボディ領域内のｎ＋ソース領域
に確実にコンタクトするために開口幅ｄ１をゲート間隔
ｄ２より小さくしなければならず（開口幅ｄ１を大きく
すると、ゲート電極１８の上部まで達してしまい動作不
能となる）、逆に言えばゲート間隔ｄ２を開口幅ｄ１以
下に設定することができないため、トランジスタのセル
幅ｄ３も増大し、トランジスタ密度を向上させることが
困難となる問題があった。However, in the above conventional semiconductor device, the opening width d1 must be smaller than the gate spacing d2 in order to surely contact the n + source region in the p body region (opening width). If d1 is increased, it reaches the upper portion of the gate electrode 18 and becomes inoperable.) Conversely, since the gate interval d2 cannot be set to be equal to or smaller than the opening width d1, the cell width d3 of the transistor also increases, and There is a problem that it is difficult to improve the density.
【０００８】本発明は、上記従来技術の有する課題に鑑
みなされたものであり、その目的は、ゲート間隔を縮小
でき、これにより素子セル幅も縮小して素子密度を向上
させることができる装置を提供することにある。The present invention has been made in view of the above problems of the prior art, and an object of the present invention is to provide an apparatus capable of reducing the gate spacing, thereby reducing the element cell width and improving the element density. To provide.
【０００９】[0009]
【課題を解決するための手段】上記目的を達成するため
に、第１の発明は、トレンチゲート間にボディ領域及び
ソース領域を備えた半導体装置において、トレンチゲー
ト側部から上部にわたって前記ボディ領域及びソース領
域をそれぞれ延長した延長領域を有することを特徴とす
る。トレンチゲート側部から上部にわたる延長領域を形
成することで、ゲート間隔によらず確実にコンタクトを
とることができるようになり、ゲート間隔を従来以上に
縮小することができる。To achieve the above object, according to the Invention The first invention is a semiconductor device having a body region and a source region between the trench gate, the body region and across the top of the trench gate side It is characterized in that each of the source regions has an extension region. By forming the extended region extending from the side portion of the trench gate to the upper portion, contact can be surely made irrespective of the gate interval, and the gate interval can be reduced more than ever before.
【００１０】また、第２の発明は、第１の発明におい
て、前記トレンチゲート上部に形成されたゲート絶縁膜
の厚さが前記トレンチゲート側部に形成されたゲート絶
縁膜の厚さ以上であることを特徴とする。ゲート絶縁膜
の上部を厚くすることで、ソース領域を延長した延長領
域を介してソース電圧が印加される際にもゲート電極の
絶縁性を維持することができ、半導体装置を確実に動作
させることができる。In a second aspect based on the first aspect, the thickness of the gate insulating film formed on the upper portion of the trench gate is equal to or more than the thickness of the gate insulating film formed on the side portion of the trench gate. It is characterized by By thickening the upper part of the gate insulating film, the insulating property of the gate electrode can be maintained even when the source voltage is applied through the extended region extending the source region, and the semiconductor device can be operated reliably. You can
【００１１】また、第３の発明は、第１、第２の発明に
おいて、前記半導体装置の上部に、前記延長領域に電極
を接続するための開口部を有する絶縁膜を有し、前記ト
レンチゲートのゲート間隔が前記開口部の幅以下である
ことを特徴とする。ゲート間隔を開口部の幅以下とする
ことで、半導体素子幅も縮小でき、素子密度を向上させ
ることができる。A third aspect of the present invention is the semiconductor device according to the first or second aspect, further comprising an insulating film having an opening for connecting an electrode to the extension region, the insulating film being provided above the semiconductor device. The gate spacing is less than or equal to the width of the opening. By setting the gate interval to be equal to or less than the width of the opening, the semiconductor element width can be reduced and the element density can be improved.
【００１２】[0012]
【発明の実施の形態】以下、図面に基づき本発明の実施
形態について説明する。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.
【００１３】図１には、本実施形態におけるトレンチゲ
ート型ＩＧＢＴの断面図（ａ）及び平面図（ｂ）が示さ
れている。なお、図３に示される従来技術と同一もしく
は対応する部材には同一符号が付されている。また、
（ｂ）の平面図は説明の都合上、ソース電極を取り去っ
た状態を示している。FIG. 1 shows a sectional view (a) and a plan view (b) of a trench gate type IGBT according to this embodiment. The same or corresponding members as those of the conventional technique shown in FIG. 3 are designated by the same reference numerals. Also,
For convenience of explanation, the plan view of (b) shows a state in which the source electrode is removed.
【００１４】図において、ドレイン電極１０の上部にｐ
＋基板１２を設け、さらにｎ＋ドリフト領域１４を設け
る。そして、ｎ＋ドリフト領域１４の上部にｐボディ領
域２０を形成し、このｐボディ領域２０を挟むようにト
レンチ内にゲート電極１８を形成する。ゲート電極１８
は従来と同様にゲート酸化膜（ゲート絶縁膜）１６で絶
縁されているが、ゲート電極１８の側部に形成されたゲ
ート酸化膜１６の厚さとゲート電極１８の上部に形成さ
れたゲート酸化膜１６の厚さとを比較すると、図に示さ
れるように（上部の厚さ）≧（側部の厚さ）となってい
る。また、ｐボディ領域２０の上部にｎ＋ソース領域２
２が設けられ、このｎ＋ソース領域２２の上部に、ゲー
ト電極１８の側部から上部にわたる断面形状Ｔ字型のｎ
＋延長領域１００が形成される。このｎ＋延長領域１０
０とゲート電極１８とは、上記のゲート酸化膜１６で互
いに絶縁されており、特にゲート電極１８の上部とｎ＋
延長領域１００とは厚いゲート酸化膜１６で互いに絶縁
されている。なお、ｎ＋延長領域１００は、ｎ＋ソース
領域２２が形成されている箇所のみに形成され、ｎ＋ソ
ース領域２２が形成されていない箇所のｐボディ領域２
０上には（ｂ）に示すようにｐ＋延長領域１０２（この
ｐ＋延長領域１０２も断面形状Ｔ字型である）が形成さ
れる。したがって、（ｂ）の平面図に示すように、ｎ＋
延長領域１００（ｎ＋ソース領域２２に接続されてい
る）とｐ＋延長領域１０２（ｐボディ領域２０に接続さ
れている）は交互に配列することになる。ｐ＋延長領域
１０２の機能は、表面まで延在させた従来のｐボディ領
域２０と同様にソースとボディを短絡させて寄生トラン
ジスタのオン動作を防止するためである。そして、ｎ＋
延長領域１００の上部にはｎ＋延長領域１００を介して
ｎ＋ソース領域２２に電圧を印加するためのコンタクト
開口部を有する絶縁膜２６が設けられる。コンタクト開
口部の開口幅はｃ１である。なお、ソース領域及びボデ
ィ領域の配置は上記実施形態に限定されるものではな
く、図３（ｂ）に示すような従来の装置、すなわちゲー
ト電極側にｎ＋ソース領域、ゲート間中央部にｐ＋ボデ
ィ領域を配置する等、ｎ＋領域、ｐ＋領域に分けた多様
な配置を選択可能である。In the figure, p is formed on the drain electrode 10.
A + substrate 12 is provided, and an n + drift region 14 is further provided. Then, the p body region 20 is formed on the n + drift region 14, and the gate electrode 18 is formed in the trench so as to sandwich the p body region 20. Gate electrode 18
Is insulated by a gate oxide film (gate insulating film) 16 as in the conventional case, but the thickness of the gate oxide film 16 formed on the side of the gate electrode 18 and the gate oxide film formed on the gate electrode 18 are When compared with the thickness of No. 16, as shown in the figure, (upper thickness) ≧ (side thickness). In addition, the n + source region 2 is formed on the p body region 20.
2 is provided on the n + source region 22 and has a T-shaped n-shaped cross section extending from the side portion of the gate electrode 18 to the upper portion thereof.
A + extension region 100 is formed. This n + extension area 10
0 and the gate electrode 18 are insulated from each other by the gate oxide film 16 described above.
The extension region 100 is insulated from each other by the thick gate oxide film 16. It should be noted that the n + extension region 100 is formed only in the portion where the n + source region 22 is formed, and is the p body region 2 where the n + source region 22 is not formed.
As shown in (b), a p + extension region 102 (this p + extension region 102 also has a T-shaped cross section) is formed on 0. Therefore, as shown in the plan view of FIG.
The extension regions 100 (connected to the n + source region 22) and the p + extension regions 102 (connected to the p body region 20) will be arranged alternately. The function of the p + extension region 102 is to prevent the ON operation of the parasitic transistor by short-circuiting the source and the body like the conventional p body region 20 extended to the surface. And n +
An insulating film 26 having a contact opening for applying a voltage to the n + source region 22 through the n + extension region 100 is provided on the extension region 100. The opening width of the contact opening is c1. The arrangement of the source region and the body region is not limited to the above-described embodiment, but the conventional device as shown in FIG. 3B, that is, the n + source region on the gate electrode side and the p + body on the center portion between the gates. It is possible to select various arrangements divided into an n + area and a p + area, such as arranging areas.
【００１５】本実施形態のトレンチ型ＩＧＢＴはこのよ
うな構成であり、動作時には従来と同様に電流がトレン
チの側部に隣接するチャネルに沿って垂直に流れること
になるが、断面形状Ｔ字型のｎ＋延長領域１００をｎ＋
ソース領域２２上に積層し（実質的にはｎ＋ソース領域
を断面形状Ｔ字型に延在させたことと等価）、かつ、ｎ
＋延長領域１００とゲート電極１８との間にはゲート酸
化膜１６が介在しているため、ゲート間隔ｃ２以上に開
口幅ｃ１を増大させることができ、逆に言えば、ゲート
間隔ｃ２を開口幅ｃ１以下に設定することが可能とな
る。The trench type IGBT of the present embodiment has such a structure, and during operation, a current flows vertically along the channel adjacent to the side portion of the trench as in the conventional case, but the sectional shape is T-shaped. N + extension region 100 of n +
Stacked on the source region 22 (substantially equivalent to extending the n + source region in a T-shaped cross section), and n
Since the gate oxide film 16 is interposed between the + extension region 100 and the gate electrode 18, it is possible to increase the opening width c1 beyond the gate distance c2. It is possible to set it to c1 or less.
【００１６】したがって、従来においては、ゲート間隔
ｄ２はコンタクトの開口幅ｄ１にコンタクトのアライメ
ント余裕を足した値となり、コンタクトの開口幅ｄ１を
製造条件から規定される最小幅に設定できたとしてもゲ
ート間隔ｄ２はそれより大きくなってしまう（ｄ２＞ｄ
１）が、本実施形態ではゲート間隔ｃ２をコンタクトの
開口幅ｃ１以下に設定でき（ｃ２≦ｃ１）、ゲート間隔
ｃ２自体を製造条件から規定される最小幅に設定するこ
とも可能となる。結果として、本実施形態ではトランジ
スタのセル幅ｃ３も従来以上に縮小することが可能とな
り、トランジスタ密度を向上させてオン電圧を低減する
ことができる。Therefore, in the prior art, the gate distance d2 has a value obtained by adding the contact alignment margin to the contact opening width d1, and even if the contact opening width d1 can be set to the minimum width defined by the manufacturing conditions. The interval d2 becomes larger than that (d2> d
However, in this embodiment, the gate spacing c2 can be set to be equal to or smaller than the contact opening width c1 (c2 ≦ c1), and the gate spacing c2 itself can be set to the minimum width defined by the manufacturing conditions. As a result, in this embodiment, the cell width c3 of the transistor can be reduced more than ever, and the transistor density can be improved and the on-voltage can be reduced.
【００１７】なお、本実施形態のトレンチ型ＩＧＢＴで
は、ｎ＋延長領域１００上にコンタクト（ソースコンタ
クト）開口を形成するため従来以上にコンタクト面積を
大きくとれるので、コンタクト抵抗を大幅に低減するこ
とも可能である。In the trench type IGBT of the present embodiment, since the contact (source contact) opening is formed on the n + extension region 100, the contact area can be made larger than before, so that the contact resistance can be greatly reduced. Is.
【００１８】また、ｎ＋延長領域１００の抵抗を調整す
る（具体的には、ｎ＋延長領域１００の材料又は不純物
濃度を適宜選択すればよい）ことで、適切なソース抵抗
を形成することができるので、ソース電圧によるソース
電流へのフィードバックによりトランジスタセル間の電
流バランスを自動調整することも可能となる。すなわ
ち、あるトランジスタのソース電流が大きくなると、適
宜調整したソース抵抗によりソース電圧が上昇し、ゲー
ト・ソース間電圧が低下するためソース電流が減少する
という負のフィードバックが作用し、そのトランジスタ
の電流値を自動調整できる。Further, by adjusting the resistance of the n + extension region 100 (specifically, the material or impurity concentration of the n + extension region 100 may be appropriately selected), an appropriate source resistance can be formed. It is also possible to automatically adjust the current balance between the transistor cells by feeding back the source current according to the source voltage. That is, when the source current of a certain transistor increases, the source voltage increases due to the appropriately adjusted source resistance, and the source current decreases because the gate-source voltage decreases, which acts as negative feedback, and the current value of that transistor decreases. Can be automatically adjusted.
【００１９】さらに、本実施形態では、ゲート間隔ｃ２
を開口幅ｃ１以下に設定しているが、ゲート間隔ｃ２を
開口幅ｃ１より小さく（ｃ２＜ｃ１）設定する方が素子
密度向上の観点から一層好ましいことは言うまでもな
い。Further, in this embodiment, the gate spacing c2
However, it is needless to say that it is more preferable to set the gate interval c2 smaller than the opening width c1 (c2 <c1) from the viewpoint of improving the element density.
【００２０】図２には、図１に示された半導体装置の製
造方法が示されている。まず、ｐ＋基板１２上にｎドリ
フト領域１４をエピタキシャル成長させる。その後、ｐ
ボディ領域２０（例えば４μｍ）とｎ＋ソース領域２２
（例えば１μｍ）をイオン注入と拡散によって順次形成
する（ａ）。次に、表面を熱酸化させて酸化膜２３（例
えば５０ｎｍ）を形成し、さらにＣＶＤ法により窒化膜
２５（例えば２００ｎｍ）及び酸化膜２７（例えば２０
０ｎｍ）を形成する（ｂ）。次に、フォトリソグラフィ
工程を用いてレジストマスクを作成し、このレジストマ
スクを用いて酸化膜２７、窒化膜２５及び酸化膜２３を
順次ドライエッチングする。レジストマスクを除去した
後、酸化膜２７、窒化膜２５、酸化膜２３をマスクとし
て用いてｎドリフト領域１４をドライエッチングし、ト
レンチ構造を形成する（ｃ）。FIG. 2 shows a method of manufacturing the semiconductor device shown in FIG. First, the n drift region 14 is epitaxially grown on the p + substrate 12. Then p
Body region 20 (for example, 4 μm) and n + source region 22
(For example, 1 μm) is sequentially formed by ion implantation and diffusion (a). Next, the surface is thermally oxidized to form an oxide film 23 (for example, 50 nm), and further, a nitride film 25 (for example, 200 nm) and an oxide film 27 (for example, 20 nm) are formed by a CVD method.
0 nm) is formed (b). Next, a resist mask is formed using a photolithography process, and the oxide film 27, the nitride film 25, and the oxide film 23 are sequentially dry-etched using this resist mask. After removing the resist mask, the n drift region 14 is dry-etched using the oxide film 27, the nitride film 25, and the oxide film 23 as a mask to form a trench structure (c).
【００２１】トレンチ構造を形成した後、トレンチの側
壁を熱酸化し（例えば５０ｎｍ）、ふっ酸にて除去す
る。さらにトレンチ側壁をケミカルドライエッチングに
てエッチング（例えば５０ｎｍ）する。その後、熱酸化
によりゲート酸化膜１６（例えば１００ｎｍ）を形成
し、多結晶シリコンでトレンチを埋めて窒化膜２５のと
ころまで全面エッチバックし、ゲート電極１８を形成す
る（ｄ）。次に、表面の酸化膜２７をドライエッチング
で除去する。このとき、ゲート酸化膜１６は窒化膜２５
とゲート電極１８に覆われているのでエッチングされる
ことはない。その後、熱酸化にてゲート電極１８の表面
（上部）を酸化して上部のゲート酸化膜１６（例えば４
００ｎｍ）を形成する（ｅ）。既述したように、この上
部のゲート酸化膜１６の膜厚は、側部のゲート酸化膜１
６よりも厚く形成される。これは、窒化膜２５の存在に
より可能となる（窒化膜２５の下部は酸化されない）。
そして、ドライエッチングにより窒化膜２５及び酸化膜
２３を除去する（ｆ）。After forming the trench structure, the sidewall of the trench is thermally oxidized (for example, 50 nm) and removed with hydrofluoric acid. Further, the side wall of the trench is etched (for example, 50 nm) by chemical dry etching. After that, the gate oxide film 16 (for example, 100 nm) is formed by thermal oxidation, the trench is filled with polycrystalline silicon, and the entire surface is etched back to the nitride film 25 to form the gate electrode 18 (d). Next, the oxide film 27 on the surface is removed by dry etching. At this time, the gate oxide film 16 is the nitride film 25.
Since it is covered with the gate electrode 18, it is not etched. After that, the surface (upper part) of the gate electrode 18 is oxidized by thermal oxidation and the upper gate oxide film 16 (for example, 4
00 nm) is formed (e). As described above, the film thickness of the upper gate oxide film 16 is equal to that of the side gate oxide film 1.
It is formed thicker than 6. This is possible due to the presence of the nitride film 25 (the lower part of the nitride film 25 is not oxidized).
Then, the nitride film 25 and the oxide film 23 are removed by dry etching (f).
【００２２】次に、ＣＶＤ法よりアモルファスシリコン
１０１を積層する（ｇ）。このアモルファスシリコン１
０１は、ｎ＋延長領域１００あるいはｐ＋延長領域１０
２となるものであり、積層した後に５５０度の熱処理に
て固相エピタキシャル成長させて単結晶化させてもよ
い。すなわち、ｎ＋延長領域１００あるいはｐ＋延長領
域は、アモルファスでも単結晶でもよい。また、ｎ＋延
長領域１００あるいはｐ＋延長領域１０２は多結晶半導
体で構成することも可能であり、すなわち、半導体であ
れば結晶性は問わない。アモルファスシリコン１０１を
積層した後、イオン注入、熱拡散を用いてｎ＋延長領域
１００（及びｐ＋延長領域１０２）を形成する（ｈ）。
ｎ＋延長領域１００については、例えばリンを拡散させ
ればよい。そして、ＣＶＤ法を用いて表面に酸化膜（絶
縁膜）２４を形成し、フォトリソグラフィ、ドライエッ
チング法を用いてゲート間隔ｃ２以上のコンタクト開口
ｃ１を形成する（ｉ）。Next, amorphous silicon 101 is laminated by the CVD method (g). This amorphous silicon 1
01 is the n + extension region 100 or the p + extension region 10
However, it may be a single crystal by solid phase epitaxial growth by heat treatment at 550 ° C. after stacking. That is, the n + extension region 100 or the p + extension region may be amorphous or single crystal. Further, the n + extension region 100 or the p + extension region 102 can be composed of a polycrystalline semiconductor, that is, the crystallinity does not matter as long as it is a semiconductor. After stacking the amorphous silicon 101, the n + extension region 100 (and the p + extension region 102) is formed by ion implantation and thermal diffusion (h).
For the n + extension region 100, phosphorus may be diffused, for example. Then, an oxide film (insulating film) 24 is formed on the surface by the CVD method, and a contact opening c1 having a gate interval c2 or more is formed by the photolithography or dry etching method (i).
【００２３】最後に、スパッタリングを用いて素子表面
（上部）にソース電極（Ａｌ）２６を形成してフォトリ
ソグラフィ及びエッチングにより所望の形状とし、同様
にスパッタリングを用いてドレイン電極１０（Ｔｉ／Ｎ
ｉ／Ａｕ）を形成する（ｊ）。Finally, the source electrode (Al) 26 is formed on the surface (upper part) of the device by sputtering and formed into a desired shape by photolithography and etching. Similarly, the drain electrode 10 (Ti / N) is formed by sputtering.
i / Au) is formed (j).
【００２４】以上、本実施形態についてＩＧＢＴを例に
とり説明したが、本発明はこれに限定されることはな
く、例えばＭＯＳＦＥＴやサイリスタ、ＳＩＴ等にも適
用することができる。なお、金属電極材料は上記に限定
されるものではなく、Ｗ、Ｍｏ等を含め、金属の単層、
多層膜なら何でもよい。Although the present embodiment has been described by taking the IGBT as an example, the present invention is not limited to this, and can be applied to, for example, MOSFET, thyristor, SIT and the like. The metal electrode material is not limited to the above, and a single layer of metal including W, Mo, etc.,
Any multi-layer film may be used.
【００２５】[0025]
【発明の効果】以上説明したように、本発明によればゲ
ート間隔を従来以上に縮小でき、これにより素子セル幅
も縮小して素子密度を向上させることができる。As described above, according to the present invention, the gate interval can be reduced more than ever, and the element cell width can be reduced to improve the element density.
【図１】 本発明の実施形態の断面図及び平面図であ
る。FIG. 1 is a sectional view and a plan view of an embodiment of the present invention.
【図２】 本発明の実施形態に係る半導体装置の製造方
法を示す説明図である。FIG. 2 is an explanatory view showing the method for manufacturing the semiconductor device according to the embodiment of the invention.
【図３】 従来の半導体装置の断面図及び平面図であ
る。FIG. 3 is a sectional view and a plan view of a conventional semiconductor device.
１０ ドレイン電極、１２ ｐ＋基板、１４ ｎドリフ
ト領域、１６ ゲート酸化膜（ゲート絶縁膜）、１８
ゲート電極、２０ ｐボディ領域、２２ ｎ＋ソース領
域、１００ ｎ＋延長領域、１０２ ｐ＋延長領域、２
４ 絶縁膜、２６ ソース電極。10 drain electrode, 12 p + substrate, 14 n drift region, 16 gate oxide film (gate insulating film), 18
Gate electrode, 20 p body region, 22 n + source region, 100 n + extension region, 102 p + extension region, 2
4 insulating film, 26 source electrode.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ Ｈ０１Ｌ 29/74 Ｈ０１Ｌ 29/74 ６０１Ｂ 29/749 29/78 ３０１Ｖ ─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. 7 Identification code FI H01L 29/74 H01L 29/74 601B 29/749 29/78 301V
Claims (3)
ス領域を備えた半導体装置において、 トレンチゲート側部から上部にわたって前記ボディ領域
及びソース領域をそれぞれ延長した延長領域を有するこ
とを特徴とする半導体装置。1. A semiconductor device having a body region and a source region between trench gates, wherein the body region extends from a side portion of the trench gate to an upper portion thereof.
And wherein a has an extension region extending respectively a source region.
さが前記トレンチゲート側部に形成されたゲート絶縁膜
の厚さ以上であることを特徴とする半導体装置。2. The device according to claim 1, wherein the thickness of the gate insulating film formed on the trench gate is equal to or more than the thickness of the gate insulating film formed on the side of the trench gate. Semiconductor device.
おいて、 前記半導体装置の上部に、前記延長領域に電極を接続す
るための開口部を有する絶縁膜を有し、 前記トレンチゲートのゲート間隔が前記開口部の幅以下
であることを特徴とする半導体装置。3. The device according to claim 1, further comprising an insulating film having an opening for connecting an electrode to the extension region, the insulating film being provided on an upper portion of the semiconductor device. A semiconductor device, wherein a gate interval is equal to or less than a width of the opening.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31948198A JP3424572B2 (en) | 1998-11-10 | 1998-11-10 | Semiconductor device |
| US09/435,766 US6855983B1 (en) | 1998-11-10 | 1999-11-08 | Semiconductor device having reduced on resistance |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31948198A JP3424572B2 (en) | 1998-11-10 | 1998-11-10 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000150872A JP2000150872A (en) | 2000-05-30 |
| JP3424572B2 true JP3424572B2 (en) | 2003-07-07 |
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ID=18110697
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| JP31948198A Expired - Fee Related JP3424572B2 (en) | 1998-11-10 | 1998-11-10 | Semiconductor device |
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|---|---|---|---|---|
| JP2004319808A (en) * | 2003-04-17 | 2004-11-11 | Takehide Shirato | Mis field effect transistor and its manufacturing method |
| JP2006128506A (en) * | 2004-10-29 | 2006-05-18 | Sharp Corp | Trench type mosfet and manufacturing method thereof |
| JP2007043123A (en) * | 2005-07-01 | 2007-02-15 | Toshiba Corp | Semiconductor device |
| JP4768557B2 (en) | 2006-09-15 | 2011-09-07 | 株式会社東芝 | Nonvolatile semiconductor memory device and manufacturing method thereof |
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