JPS63227059A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPS63227059A JPS63227059A JP6155487A JP6155487A JPS63227059A JP S63227059 A JPS63227059 A JP S63227059A JP 6155487 A JP6155487 A JP 6155487A JP 6155487 A JP6155487 A JP 6155487A JP S63227059 A JPS63227059 A JP S63227059A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- oxide film
- gate oxide
- main
- sub
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 230000003647 oxidation Effects 0.000 claims description 8
- 238000007254 oxidation reaction Methods 0.000 claims description 8
- 230000003064 anti-oxidating effect Effects 0.000 claims description 5
- 239000004020 conductor Substances 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 4
- 230000002265 prevention Effects 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 abstract description 7
- 230000000694 effects Effects 0.000 abstract description 3
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 20
- 238000000034 method Methods 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- 230000005684 electric field Effects 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000001947 vapour-phase growth Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置およびその製造方法に関し、特に超
ＬＳＩの構成要素であるＭＯＳＦＥＴ（電界効果トラン
ジスタ）に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device and a method for manufacturing the same, and in particular to a MOSFET (field effect transistor) that is a component of a very large scale integrated circuit.
従来の技術
高集積化の実現のため素子が縮小されているため、素子
内の電界強度が高くなり耐圧が低下している。これを改
善するため、ソース−ドレインを低・高濃度の２領域で
構成するＬＤＤ （ＬｉｇｈｔｌｙＤｏｐｅｄ Ｄｒａ
ｉｕ ）構造が提案され開発されている。ゲートを形成
したのち、低濃度領域（ｎ−）を形成するためのＰイオ
ンを１×１０ α 注入し、ゲート両端面にＳ ｉ０２
から成る側壁を気相成長十垂直ドライエッチで自己整合
的に形成し、そのＳｔ○２側壁をマスクとして高濃度（
ｎ＋）ソース・ドレインを４×１０ ｃｍ のＡｓ注入
で形成し、大体側壁の巾だけずれたｎ−・ｎ＋構造が形
成されている。Conventional technology As elements are reduced in size to achieve higher integration, the electric field strength within the element increases and the withstand voltage decreases. In order to improve this, LDD (Lightly Doped Dra
iu ) structure has been proposed and developed. After forming the gate, 1×10 α of P ions were implanted to form a low concentration region (n-), and Si02 was added to both end faces of the gate.
A sidewall consisting of St○2 is formed in a self-aligned manner by vapor phase growth and vertical dry etching, and a high concentration (
n+) sources and drains are formed by implanting 4×10 cm of As, and an n−/n+ structure is formed that is shifted by approximately the width of the sidewall.
発明が解決しようとする問題点
ｎ−の表面の大部分は絶縁膜である側壁に覆われていて
ゲートの影響力が及ばない。従ってｎ−の表面は外界の
影響を受けやすく素子特性が不安定である。Problems to be Solved by the Invention Most of the surface of n- is covered by the sidewalls, which are insulating films, and is not influenced by the gate. Therefore, the n- surface is easily influenced by the outside world and the device characteristics are unstable.
また、ゲート酸化膜は高集積化に伴なって薄くなってお
り、ゲートの形成時に、ゲート／酸化膜の選択エッチ比
が有限のため、薄いゲート酸化膜がゲート周辺ではさら
に薄くなり、後に気相成長膜で側壁を形成するもののそ
の膜質は熱酸化膜より劣るので耐圧低下が問題である。In addition, gate oxide films are becoming thinner with higher integration, and because the selective etch ratio of gate/oxide film is finite when forming gates, the thin gate oxide film becomes even thinner around the gate, and later becomes thinner. Although the sidewalls are formed using a phase-grown film, the quality of the film is inferior to that of a thermal oxide film, so a reduction in breakdown voltage is a problem.
本発明はこの様な従来例の問題点を解決するためになさ
れたものである。The present invention has been made to solve the problems of the conventional example.
問題点を解決するための手段
すなわち、本発明の半導体装置は、１導電型半導体基板
上に第１ゲート酸化膜を介して設けられた主ゲート、上
記基板上に第２ゲート酸化膜を介しかつ上記主ゲート両
側に接して設けられた副ゲート、上記主及び副ゲートに
より隔てられ上記基板表面に設けられた２導電型のソー
ス・ドレインを備え、上記第２ゲート酸化膜が第１ゲー
ト酸化膜と同等以上の厚みでしかも上記ソース・ドレイ
ンが低・高濃度の２領域から成っていて、上記低濃度領
域表面が主ゲートと副ゲートによりすべて覆われている
構造を有するものである。Means for Solving the Problems In other words, the semiconductor device of the present invention has a main gate provided on a single conductivity type semiconductor substrate via a first gate oxide film, a main gate provided on the substrate via a second gate oxide film, and A sub-gate provided in contact with both sides of the main gate, a dual conductivity type source/drain separated by the main and sub-gates and provided on the surface of the substrate, wherein the second gate oxide film is a first gate oxide film. It has a structure in which the source and drain are made up of two regions, a low concentration region and a high concentration region, and the surface of the low concentration region is completely covered by the main gate and the sub-gate.
そして、本発明の方法は、１導電型半導体基板上に第１
ゲート酸化膜を介して主ゲートを形成する工程、上記主
ゲート側壁を酸化防止被膜で覆う工程、熱酸化により上
記主ゲート直下以外の領域に上記第１ゲート酸化膜と同
等以上の厚みの第２ゲート酸化膜を形成する工程、上記
酸化防止被膜を除去し低濃度ソース・ドレインを上記主
ゲートをマスクとしてイオン注入で形成する工程、上記
主ゲート両側に接した導電性材料から成る側壁を形成す
る工程、上記導電性材料から成る側壁をマスクとして高
濃度ソース・ドレインをイオン注入で形成する工程とを
含んで成るものである。Then, in the method of the present invention, a first
a step of forming a main gate via a gate oxide film, a step of covering the side walls of the main gate with an anti-oxidation film, and a step of forming a second gate oxide film having a thickness equal to or greater than the first gate oxide film in a region other than directly under the main gate by thermal oxidation. a step of forming a gate oxide film, a step of removing the anti-oxidation film and forming a low concentration source/drain by ion implantation using the main gate as a mask, and forming side walls made of a conductive material in contact with both sides of the main gate. The method includes a step of forming highly doped sources and drains by ion implantation using the sidewalls made of the conductive material as a mask.
本発明を用いることにより、たとえばｎ一層の表面をも
ゲート電極で覆う。その際、ｎ一層上のゲート酸化膜は
チャネル部のそれと同等以上の厚みとする。この構造を
実現するため、主ゲート形成後、主ゲート側面を酸化防
膜で覆って主ゲート部以外の酸化膜を厚くしてのち、主
ゲート両側面に接し、電気的にも接続された副ゲートを
形成する。By using the present invention, for example, even the surface of an n layer can be covered with a gate electrode. At this time, the thickness of the gate oxide film on the nth layer is equal to or greater than that of the channel portion. In order to realize this structure, after forming the main gate, the side surfaces of the main gate are covered with an oxidation barrier film to thicken the oxide film in areas other than the main gate, and then a sub-oxide film is formed that is in contact with both sides of the main gate and is electrically connected. Form a gate.
作 用
本発明によれば、たとえばｎ一層上がゲートに覆われて
いるので、外界の影響がそれでしゃ断される。ゲート端
部でのゲート酸化膜厚の減少がないのでゲートの耐圧低
下はない。Function According to the present invention, for example, since the upper layer n is covered with a gate, the influence of the outside world is blocked thereby. Since there is no reduction in the gate oxide film thickness at the edge of the gate, there is no reduction in the breakdown voltage of the gate.
実施例
本発明の半導体装置の実施例としてＬＤＤＭＯＳトラン
ジスタ構造を第１図に示す。Ｐ型１０Ω、ｃＩｒＬ（１
００）面のシリコン半導体基板１に分離用の、辱い酸化
膜（１μｍ）２が選択的に形成され、厚さ８０ｍｍの第
１のゲート酸化膜３ａを介してポリシリコン（厚さ０．
３μｍ）の主ゲー）４ａおよびその両側面に接続しかつ
基板１上に第２のゲート酸化膜（厚さ１００人）ｓｂを
介して同じくポリシリコンの副ゲート４ａが形成されて
ゲート４を成している。主ゲート４ａをマスクとしたヱ
“注入によるｎ一層６，５′および副ゲート４ｂをマス
クとしたＡｓ 注入によるｎ 層６，６′が低・高濃
度のソース・ドレインを成しており、ｎ一層６，６′は
第２ゲート酸化膜３ｂを介して副ゲー）４ｂに覆われて
いる。ゲートが低い電圧でドレインが高い電圧のとき、
ｎ一層表面はゲートに覆われているので南空乏化される
。その分ｎ一層５，５′内にはドレイン電圧の増大に伴
ない空乏層が拡がりｎ７− Ｐ基板間接合での電界強度
が低下する。従って、従来例の絶縁膜側壁と同等の電界
強度で十分なら、ｎ″″層をより濃くする事が出来る。Embodiment FIG. 1 shows an LDDMOS transistor structure as an embodiment of the semiconductor device of the present invention. P type 10Ω, cIrL(1
An isolation oxide film (1 μm) 2 is selectively formed on a silicon semiconductor substrate 1 having a surface (0.00 mm), and polysilicon (0.
A sub-gate 4a, also made of polysilicon, is formed on the substrate 1 via a second gate oxide film (thickness 100 nm) sb, which is connected to the main gate 4a (3 μm) and both sides thereof, and forms the gate 4. are doing. The N layer 6, 5' formed by implantation using the main gate 4a as a mask and the N layer 6, 6' formed by As injection using the sub gate 4b as a mask form a source/drain with a low/high concentration, and The first layer 6, 6' is covered with the sub-gate 4b via the second gate oxide film 3b.When the gate voltage is low and the drain voltage is high,
Since the surface of the n layer is covered with a gate, it is depleted in the south. Accordingly, a depletion layer expands in the n-layers 5, 5' as the drain voltage increases, and the electric field strength at the n7-P substrate junction decreases. Therefore, if the electric field strength equivalent to that of the conventional insulating film sidewall is sufficient, the n'''' layer can be made denser.
ｎ一層は寄生抵抗を有しているので、本発明ではその寄
生抵抗が小さくできる。Since the n-layer has parasitic resistance, the parasitic resistance can be reduced in the present invention.
次に本発明の製造工程の一例について第２図に沿って述
べる。Next, an example of the manufacturing process of the present invention will be described with reference to FIG.
（５）基板１上に選択的に分離用酸化膜２を約１μｍ厚
に選択酸化法で成長せしめてのち、露出した基板１表面
に熱酸化で第１のゲート酸化膜３ａを約８ｎｍ厚に成長
せしめ引続きポリシリコン４ａを気相成長法で厚さ０．
３μｍになるよう堆積せしめてパターンを形成する。こ
のとき、露出したゲート酸化膜３ａ’はドライエツチン
グで一部除去され薄くなる。(5) After selectively growing an isolation oxide film 2 on the substrate 1 to a thickness of about 1 μm using a selective oxidation method, a first gate oxide film 3a is grown on the exposed surface of the substrate 1 to a thickness of about 8 nm by thermal oxidation. Subsequently, polysilicon 4a is grown to a thickness of 0.05 cm using a vapor phase growth method.
A pattern is formed by depositing it to a thickness of 3 μm. At this time, the exposed gate oxide film 3a' is partially removed by dry etching and becomes thin.
（Ｂ） ゲート４ａの側壁をシリコン窒化膜の様な酸
化防止膜７で覆い、ポリシリコン４ａの端部での酸化膜
の膨張を抑えつつ薄くなった酸化膜３ａ’を熱酸化で１
０ｎｍ厚まで厚くして第２ゲート酸化膜３ｂを成長せし
める。(B) The side wall of the gate 4a is covered with an oxidation prevention film 7 such as a silicon nitride film, and the thinned oxide film 3a' is thermally oxidized while suppressing the expansion of the oxide film at the edge of the polysilicon 4a.
The second gate oxide film 3b is grown to a thickness of 0 nm.
ｑ ゲート４ａをマスクとして、ｒをＩ Ｘ １０”
ｅｒａ−２注入してｎ一層５，６′を形成する。注入前
に酸化防止膜７を除去しておく。これは、ｎ一層６，６
′がゲー）４ａと必らず重なり部分を持つようにするた
めである。q Using gate 4a as a mask, r is I x 10”
Era-2 is implanted to form n-layers 5 and 6'. The anti-oxidation film 7 is removed before implantation. This is n one layer 6,6
This is to ensure that '' always has an overlapping portion with game)4a.
ｐ） ポリシリコンを堆積し、ドライエッチすることで
ゲート４ａの両側面に於て接したポリシリコンの副ゲー
ト４ｂが形成される。これをマスクとしてＡｓ＋を４×
１０１５１−２注入してｎ＋層６．６′が形成される。p) Polysilicon is deposited and dry etched to form polysilicon sub-gates 4b that are in contact with both sides of the gate 4a. Use this as a mask and add 4x As+
10151-2 implantation to form n+ layer 6.6'.
ｎ一層６，６′とｎ＋層６．ｅ′は接続されていてソー
ス・ドレインを成している。n layer 6, 6' and n+ layer 6. e' is connected and forms a source and drain.
発明の効果
本発明によれば、
（１）ｎ一層上がすべてゲートで覆われているので外界
の影響を受けず特性が安定している。Effects of the Invention According to the present invention, (1) Since the entire upper layer is covered with gates, the characteristics are stable without being influenced by the outside world.
（２） ゲート・ドレイン間電圧が直接印加される部
分のゲート酸化膜が薄くならないので耐圧低下がない。(2) Since the gate oxide film in the area where the gate-drain voltage is directly applied does not become thin, there is no drop in breakdown voltage.
（３） ゲート・ドレイン間電圧でｎ一層表面が空乏
化され易いのでドレイン・ソース耐圧は高い。(3) The drain-source breakdown voltage is high because the n-layer surface is easily depleted by the gate-drain voltage.
あるいは、耐圧を従来通り保てば、その分ｎ一層を高濃
度に出来るので寄生抵抗が低く、ドレイン電流が高い。Alternatively, if the breakdown voltage is maintained as before, the n layer can be made to have a higher concentration, resulting in lower parasitic resistance and higher drain current.
（４）副ゲート直下のゲート酸化膜を成長せしめる際、
主ゲート側面を酸化防止膜で覆うので、主ゲート直下の
ゲート酸化膜厚は影響を受けず、チャネルの電気特性は
維持されている。(4) When growing the gate oxide film directly under the sub-gate,
Since the side surface of the main gate is covered with an oxidation prevention film, the thickness of the gate oxide film directly under the main gate is not affected, and the electrical characteristics of the channel are maintained.
等の効果がもたらされ、ますます微細化が進むＭＯＳＦ
ＥＴの特性を向上させるものである。MOSFs are becoming increasingly finer due to the effects of
This improves the characteristics of ET.
第１図は本発明の実施例のＭＯＳ トランジスタの断面
図、第２図（８）〜ｑは本実施例のＭＯＳ トランジス
タの製造方法を示す工程断面図である。
１・・・・・・シリコン半導体基板、２・・・・・・酸
化物、３・・・・・・ゲート酸化膜、４・・・・・・ゲ
ート、４ａ・・・・・・主ゲート１．ａｂ・・・・・・
副ゲート、６，６′・・・・・・ｎ一層、６゜６′・・
・・・・ｎ＋層、７・・・・・・酸化防止膜。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名−′
１″” ＣＮ −ｃ″Ｊ
囚
−εFIG. 1 is a sectional view of a MOS transistor according to an embodiment of the present invention, and FIGS. 2(8) to 2(q) are process sectional views showing a method of manufacturing the MOS transistor of this embodiment. DESCRIPTION OF SYMBOLS 1... Silicon semiconductor substrate, 2... Oxide, 3... Gate oxide film, 4... Gate, 4a... Main gate 1. ab・・・・・・
Sub-gate, 6, 6'...n single layer, 6゜6'...
...N+ layer, 7...Anti-oxidation film. Name of agent: Patent attorney Toshio Nakao and 1 other person-'
1″” CN-c″J
Prisoner-ε
Claims (2)
て設けられた主ゲート、上記基板上に第２ゲート酸化膜
を介しかつ上記主ゲート両側に接して設けられた副ゲー
ト、上記主及び副ゲートにより隔てられ上記基板表面に
設けられた２導電型のソース・ドレインを備え、上記第
２ゲート酸化膜が第１ゲート酸化膜と同等以上の厚みで
しかも上記ソース・ドレインが低・高濃度の２領域から
成り、上記低濃度領域表面が主ゲートと副ゲートにより
すべて覆われている半導体装置。(1) A main gate provided on a first conductivity type semiconductor substrate via a first gate oxide film; a sub-gate provided on the substrate via a second gate oxide film in contact with both sides of the main gate; The second gate oxide film has a thickness equal to or greater than that of the first gate oxide film, and the source and drain have a low thickness. A semiconductor device consisting of two high concentration regions, the surface of the low concentration region being completely covered by a main gate and a sub gate.
て主ゲートを形成する工程、上記主ゲート側壁を酸化防
止被膜で覆う工程、熱酸化により上記主ゲート直下以外
の領域に上記第１ゲート酸化膜と同等以上の厚みの第２
ゲート酸化膜を形成する工程、上記酸化防止被膜を除去
し低濃度ソース・ドレインを上記主ゲートをマスクとし
てイオン注入で形成する工程、上記主ゲート両側に接し
た導電性材料から成る側壁を形成する工程、上記導電性
材料から成る側壁をマスクとして高濃度ソース・ドレイ
ンをイオン注入で形成する工程とを含んで成る半導体装
置の製造方法。(2) A step of forming a main gate on a first conductivity type semiconductor substrate via a first gate oxide film, a step of covering the side walls of the main gate with an oxidation prevention film, and a step of forming the main gate in a region other than directly under the main gate by thermal oxidation. The second gate oxide film has a thickness equal to or greater than that of the first gate oxide film.
a step of forming a gate oxide film, a step of removing the anti-oxidation film and forming a low concentration source/drain by ion implantation using the main gate as a mask, and forming side walls made of a conductive material in contact with both sides of the main gate. A method of manufacturing a semiconductor device, comprising the steps of: forming a highly doped source/drain by ion implantation using the sidewall made of the conductive material as a mask.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6155487A JPH0666326B2 (en) | 1987-03-17 | 1987-03-17 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6155487A JPH0666326B2 (en) | 1987-03-17 | 1987-03-17 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63227059A true JPS63227059A (en) | 1988-09-21 |
| JPH0666326B2 JPH0666326B2 (en) | 1994-08-24 |
Family
ID=13174445
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6155487A Expired - Lifetime JPH0666326B2 (en) | 1987-03-17 | 1987-03-17 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0666326B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02139937A (en) * | 1988-11-18 | 1990-05-29 | Nec Corp | Ldd structure mosfet |
| US5023679A (en) * | 1988-06-30 | 1991-06-11 | Kabushiki Kaisha Toshiba | Semiconductor device |
| JPH03157938A (en) * | 1989-11-03 | 1991-07-05 | Philips Gloeilampenfab:Nv | Method for manufacturing semiconductor device equipped with mis transistor |
| US5371391A (en) * | 1991-12-20 | 1994-12-06 | Nippon Steel Corporation | MOS semiconductor device and method of fabricating the same |
| KR100317642B1 (en) * | 1999-05-27 | 2001-12-22 | 구본준, 론 위라하디락사 | Method for manufacturing a Thin Film Transistor using a metal plating |
-
1987
- 1987-03-17 JP JP6155487A patent/JPH0666326B2/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5023679A (en) * | 1988-06-30 | 1991-06-11 | Kabushiki Kaisha Toshiba | Semiconductor device |
| JPH02139937A (en) * | 1988-11-18 | 1990-05-29 | Nec Corp | Ldd structure mosfet |
| JPH03157938A (en) * | 1989-11-03 | 1991-07-05 | Philips Gloeilampenfab:Nv | Method for manufacturing semiconductor device equipped with mis transistor |
| US5371391A (en) * | 1991-12-20 | 1994-12-06 | Nippon Steel Corporation | MOS semiconductor device and method of fabricating the same |
| KR100317642B1 (en) * | 1999-05-27 | 2001-12-22 | 구본준, 론 위라하디락사 | Method for manufacturing a Thin Film Transistor using a metal plating |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0666326B2 (en) | 1994-08-24 |
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