JP3368645B2 - LAMINATED ELECTRONIC COMPONENT, ITS MANUFACTURING METHOD AND ITS CHARACTERISTIC MEASUREMENT METHOD - Google Patents
LAMINATED ELECTRONIC COMPONENT, ITS MANUFACTURING METHOD AND ITS CHARACTERISTIC MEASUREMENT METHODInfo
- Publication number
- JP3368645B2 JP3368645B2 JP33185293A JP33185293A JP3368645B2 JP 3368645 B2 JP3368645 B2 JP 3368645B2 JP 33185293 A JP33185293 A JP 33185293A JP 33185293 A JP33185293 A JP 33185293A JP 3368645 B2 JP3368645 B2 JP 3368645B2
- Authority
- JP
- Japan
- Prior art keywords
- laminated
- mother
- internal circuit
- dividing
- laminated electronic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/403—Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof
Landscapes
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Ceramic Capacitors (AREA)
- Coils Or Transformers For Communication (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
【０００１】[0001]
【産業上の利用分野】この発明は、内部回路要素を内部
に配置した積層電子部品、その製造方法およびその特性
測定方法に関するもので、特に、積層電子部品における
外部電極の形成態様の改良に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laminated electronic component having internal circuit elements arranged therein, a method of manufacturing the same, and a characteristic measuring method thereof, and more particularly, to improvement of a mode of forming external electrodes in the laminated electronic component. Is.
【０００２】[0002]
【従来の技術】たとえば、積層コンデンサ、積層インダ
クタ、多層回路基板、多層複合電子部品で代表される積
層電子部品は、導電膜および／または抵抗膜のような内
部回路要素を介在させた状態で複数の絶縁性シートが積
層されてなる積層体を備える。絶縁性シートとしては、
典型的には、セラミックシートが用いられる。2. Description of the Related Art For example, a multilayer electronic component typified by a multilayer capacitor, a multilayer inductor, a multilayer circuit board, and a multilayer composite electronic component has a plurality of internal circuit elements such as a conductive film and / or a resistance film. And a laminated body formed by laminating the insulating sheets. As an insulating sheet,
Ceramic sheets are typically used.
【０００３】図５は、この発明にとって興味ある従来の
積層電子部品１の外観を示す斜視図である。積層電子部
品１は、内部回路要素（図示せず）を介在させた状態で
複数の絶縁性シートが積層されてなる積層体２を備え
る。積層体２のたとえば４つの側面には、内部回路要素
に電気的に接続された外部電極３が形成される。これら
外部電極３は、図５において想像線で示すように、スル
ーホール４を分割することによって与えられる。FIG. 5 is a perspective view showing the appearance of a conventional laminated electronic component 1 which is of interest to the present invention. The laminated electronic component 1 includes a laminated body 2 in which a plurality of insulating sheets are laminated with an internal circuit element (not shown) interposed. External electrodes 3 electrically connected to the internal circuit elements are formed on, for example, four side surfaces of the laminated body 2. These external electrodes 3 are provided by dividing the through holes 4 as shown by phantom lines in FIG.
【０００４】すなわち、所定の分割線に沿って分割する
ことにより複数の積層電子部品１が得られるように用意
されたマザー積層体５において、スルーホール４を形成
し、その内周面上に外部電極３となる導電材６を付与し
た後、このマザー積層体５が、スルーホール４を分割す
るように分割される。That is, in a mother laminated body 5 prepared so that a plurality of laminated electronic components 1 can be obtained by dividing along a predetermined dividing line, a through hole 4 is formed, and an external surface is formed on the inner peripheral surface thereof. After applying the conductive material 6 to be the electrodes 3, the mother laminated body 5 is divided so as to divide the through holes 4.
【０００５】このような積層電子部品１は、チップ状の
形態で、外部電極３を介して適宜の回路基板上に表面実
装される。Such a laminated electronic component 1 is surface-mounted in the form of a chip on an appropriate circuit board via the external electrodes 3.
【０００６】[0006]
【発明が解決しようとする課題】上述したスルーホール
４への導電材６の付与は、一般的に、導電ペーストを用
いて、これをスクリーン印刷することによって行なわれ
る。そのため、外部電極３を構成する導電材６は、スル
ーホール４の内周面上だけでなく、各一部がスルーホー
ル４の周縁部において、積層体２の各主面上にまで延び
るように付与される。その結果、外部電極３は、積層体
２の各主面上において張出し部７を形成する。The above-mentioned application of the conductive material 6 to the through hole 4 is generally carried out by screen printing the conductive material using a conductive paste. Therefore, the conductive material 6 forming the external electrode 3 extends not only on the inner peripheral surface of the through hole 4 but also on each peripheral surface of the through hole 4 so as to extend onto each main surface of the laminated body 2. Granted. As a result, the external electrode 3 forms the overhanging portion 7 on each main surface of the laminated body 2.
【０００７】このような張出し部７の存在は、次のよう
な問題を引起こす。すなわち、積層電子部品１の両主面
あるいはいずれかの主面に、別の部品を実装して複合化
を図ろうとする場合、このような別の部品の配置可能な
面積が制約される。また、外部電極３の配置ピッチを細
かくすることを妨げる。The presence of such an overhang 7 causes the following problems. That is, when another component is mounted on both main surfaces or one of the main surfaces of the laminated electronic component 1 to form a composite, the area where such another component can be placed is limited. Further, it prevents the arrangement pitch of the external electrodes 3 from being made fine.
【０００８】また、外部電極３となる導電材６が、たと
えば銀ペーストの付与および焼付けにより形成される場
合、通常、その上に、銀を保護するため、ニッケルめっ
きが施され、さらにその上に、半田付け性を良好なもの
とするため、錫めっきが施される。他方、スルーホール
４内に導電材６となる銀ペーストを付与するとき、それ
が過剰であると、スルーホール４の貫通性が阻害される
ことがある。ところが、このようにスルーホール４の貫
通性が阻害されると、上述したようなめっきを、スルー
ホール４の内部にまで及ぼすことが不可能となる。その
ため、スルーホール４を分割して外部電極３を露出させ
たとき、このような外部電極３上には所望のめっき膜が
形成されていない部分が生じてしまい、上述したような
めっきの機能が適正に発揮されない事態が生じる。When the conductive material 6 to be the external electrode 3 is formed by applying silver paste and baking, for example, nickel plating is usually applied on the conductive material 6 to protect the silver, and the conductive material 6 is further applied. In order to improve the solderability, tin plating is applied. On the other hand, when the silver paste to be the conductive material 6 is applied in the through holes 4, if the silver paste is excessive, the penetration of the through holes 4 may be hindered. However, if the penetrability of the through hole 4 is impeded in this way, it becomes impossible to apply the above-mentioned plating to the inside of the through hole 4. Therefore, when the external electrode 3 is exposed by dividing the through hole 4, a portion where a desired plating film is not formed is generated on the external electrode 3 and the above-described plating function is exerted. A situation occurs where it is not properly exhibited.
【０００９】また、積層電子部品１は、少なくとも出荷
する前に、その特性を測定しなければならない。しかし
ながら、積層電子部品１は、原則として、個々独立した
状態としてからでないと、特性を測定することができな
い。すなわち、マザー積層体５の段階では、個々の積層
電子部品１の特性を測定することができず、スルーホー
ル４を分割するようにマザー積層体５を分割した後に、
初めて特性の測定が可能となる。そのため、多数の積層
電子部品１の特性の測定を能率的に行なうことができな
い。Further, the laminated electronic component 1 must be measured for its characteristics at least before shipping. However, as a general rule, the laminated electronic component 1 cannot measure its characteristics unless it is in an independent state. That is, at the stage of the mother laminated body 5, the characteristics of the individual laminated electronic components 1 cannot be measured, and after dividing the mother laminated body 5 so as to divide the through holes 4,
For the first time, the characteristics can be measured. Therefore, the characteristics of many laminated electronic components 1 cannot be efficiently measured.
【００１０】それゆえに、この発明の目的は、その少な
くとも一方主面を、複合化のための他の部品の実装面と
して広く利用することができ、そのため、部品実装の高
密度化を図ることができるとともに、外部電極の配置ピ
ッチを細かくできる、積層電子部品およびその製造方法
を提供しようとすることである。Therefore, it is an object of the present invention that at least one main surface thereof can be widely used as a mounting surface of another component for compounding, so that high density mounting of components can be achieved. It is an object of the present invention to provide a laminated electronic component and a method for manufacturing the same, which can realize a fine arrangement pitch of external electrodes.
【００１１】この発明の他の目的は、複数の積層電子部
品の特性測定を能率的に行なうことができる特性測定方
法を提供しようとすることである。Another object of the present invention is to provide a characteristic measuring method capable of efficiently measuring the characteristic of a plurality of laminated electronic components.
【００１２】[0012]
【課題を解決するための手段】この発明による積層電子
部品は、内部回路要素を介在させた状態で複数の絶縁性
シートが積層されてなる積層体、および、前記内部回路
要素に電気的に接続されかつ前記積層体の外表面に形成
された外部電極を備え、積層体は、側面に段差を有し、
該段差の位置に対応する境界面によって２つの部分に区
分したとき、外部電極は一方の部分に形成されており、
かつ、複数の主面のうちの少なくとも外部電極が形成さ
れていない側の積層体の主面が電子部品の実装面を構成
することを特徴としている。A laminated electronic component according to the present invention is a laminated body in which a plurality of insulating sheets are laminated with an internal circuit element interposed, and electrically connected to the internal circuit element. And an external electrode formed on the outer surface of the laminated body, wherein the laminated body has a step on the side surface,
It is divided into two parts by the boundary surface corresponding to the position of the step.
When divided, the external electrode is formed on one side,
In addition, at least the external electrode of the plurality of main surfaces is formed.
The main surface of the laminated body that is not covered constitutes the mounting surface of the electronic component
It is characterized in that.
【００１３】この発明による積層電子部品の製造方法
は、所定の分割線に沿って分割することによって複数の
積層電子部品が得られるものであって、前記分割線によ
って区画される各領域に個々の前記積層電子部品のため
の内部回路要素を分布させるように、これら内部回路要
素を介在させた状態で複数のマザー絶縁シートが積層さ
れてなるものであり、前記分割線を通る位置に、貫通し
ない穴が設けられた、マザー積層体を準備する工程と、
穴内に、前記内部回路要素に電気的に接続させる導電材
を付与する工程と、複数の主面のうちの少なくともマザ
ー積層体の前記穴が設けられた側の主面に、前記穴内の
前記導電材を複数部分に分割して各部分を互いに電気的
に独立させるように、前記分割線に沿って溝を形成した
後、マザー積層体を前記分割線に沿って分割することに
より、前記複数の積層電子部品のそれぞれの側面の周囲
に段差を形成する工程とを備えている。In the method for manufacturing a laminated electronic component according to the present invention, a plurality of laminated electronic components can be obtained by dividing the laminated electronic component along a predetermined dividing line. A plurality of mother insulating sheets are laminated with the internal circuit elements interposed so as to distribute the internal circuit elements for the laminated electronic component, and do not penetrate at positions passing through the dividing lines. A step of preparing a mother laminated body provided with holes,
In the hole, the step of applying a conductive material to be electrically connected to the internal circuit element, at least on the main surface of the plurality of main surfaces of the mother laminate on the side where the hole is provided ,
The conductive material is divided into a plurality of parts, and the parts are electrically connected to each other.
So as to be independent of each other, a groove is formed along the dividing line, and then the mother laminated body is divided along the dividing line to form a step around each side surface of the plurality of laminated electronic components. And the process.
【００１４】この発明による積層電子部品の特性測定方
法は、所定の分割線に沿って分割することによって複数
の積層電子部品が得られるものであって、前記分割線に
よって区画される各領域に個々の積層電子部品のための
内部回路要素を分布させるように、これら内部回路要素
を介在させた状態で複数のマザー絶縁性シートが積層さ
れてなるものであり、前記分割線を通る位置には貫通し
ない穴が設けられ、穴内に、前記内部回路要素に電気的
に接続される導電材が付与された、マザー積層体を準備
する工程と、前記穴内の導電材を複数部分に分割して各
部分を互いに電気的に独立させるように、前記分割線に
沿って前記マザー積層体に溝を形成する工程と、分割さ
れた前記導電材の各部分を外部電極として個々の積層電
子部品の特性を測定する工程とを備えている。In the method for measuring the characteristics of a laminated electronic component according to the present invention, a plurality of laminated electronic components can be obtained by dividing along a predetermined dividing line, and each region divided by the dividing line is individually divided. In order to distribute the internal circuit elements for the laminated electronic component, the plurality of mother insulating sheets are laminated with these internal circuit elements interposed, and the mother insulating sheets are pierced at positions passing through the dividing lines. A hole is provided and a conductive material that is electrically connected to the internal circuit element is provided in the hole, a step of preparing a mother laminate, and dividing the conductive material in the hole into a plurality of parts So as to be electrically independent from each other, a step of forming a groove in the mother laminated body along the dividing line, and measuring the characteristics of each laminated electronic component using each divided conductive material portion as an external electrode. And a step of.
【００１５】上述した特性測定方法において与えられた
積層電子部品の形態、すなわち、溝が形成されたマザー
積層体からなる積層電子部品の集合体は、そのまま、出
荷時の形態とすることもできる。The form of the laminated electronic component given in the above-mentioned characteristic measuring method, that is, the aggregate of the laminated electronic components composed of the mother laminated body in which the groove is formed can be used as it is as the form at the time of shipment.
【００１６】[0016]
【発明の作用および効果】この発明に係る積層電子部品
によれば、外部電極となる導電材は、積層体を貫通しな
い穴内に付与されるので、外部電極は、積層体の一方主
面上に露出することがなく、そのため、積層体のこの主
面を、外部電極に干渉されることなく、複合化のための
他の部品の実装面として広く利用することができ、その
結果、部品実装の高密度化を図ることができる。また、
穴内に付与される導電材は、その付与方法を選ぶことに
より、図５に示した張出し部７を形成しないようにする
ことができるので、外部電極の配置ピッチを細かくする
ことができる。According to the laminated electronic component of the present invention, since the conductive material to be the external electrode is provided in the hole that does not penetrate the laminated body, the external electrode is provided on one main surface of the laminated body. Since it is not exposed, this main surface of the laminated body can be widely used as a mounting surface of other components for compounding without being interfered with by external electrodes, and as a result, it is possible to mount the components. Higher density can be achieved. Also,
The conductive material applied in the holes can be prevented from forming the overhanging portions 7 shown in FIG. 5 by selecting the applying method, so that the arrangement pitch of the external electrodes can be made fine.
【００１７】また、この発明に係る積層電子部品の製造
方法によれば、積層電子部品を得るための多くの工程
を、マザー積層体の状態で実施することができるので、
多数の積層電子部品を能率的に製造することができる。
また、マザー積層体を分割して複数の積層電子部品を得
ようとするとき、この分割線に沿ってマザー積層体に溝
を予め形成し、それによって、穴内の導電材に溝を形成
するようにすれば、外部電極として好ましい性質を与え
るためのめっきを、溝の側面上に露出する部分に施すこ
とができる。その結果、マザー積層体を最終的に分割し
て得られた積層電子部品の外部電極の表面は、このよう
なめっき膜により確実に覆われた状態となる。Further, according to the method of manufacturing a laminated electronic component of the present invention, many steps for obtaining a laminated electronic component can be carried out in the state of a mother laminated body.
A large number of laminated electronic components can be efficiently manufactured.
Also, when dividing the mother laminated body to obtain a plurality of laminated electronic components, a groove is formed in the mother laminated body in advance along the dividing line, thereby forming a groove in the conductive material in the hole. By doing so, the plating for giving preferable properties as the external electrode can be applied to the portion exposed on the side surface of the groove. As a result, the surface of the external electrode of the laminated electronic component obtained by finally dividing the mother laminated body is surely covered with such a plating film.
【００１８】また、この発明に係る積層電子部品の特性
測定方法によれば、溝を形成することにより、複数の積
層電子部品が、電気的に互いに独立した状態とされなが
らも、マザー積層体として機械的に一体化されたまま、
個々の積層電子部品の特性を測定することができる。し
たがって、機械的に独立した複数の積層電子部品を取扱
う必要がなく、たとえばスクリーニングすることによ
り、能率的に多数の積層電子部品の特性を測定すること
ができる。Further, according to the method for measuring characteristics of a laminated electronic component according to the present invention, by forming a groove, a plurality of laminated electronic components can be electrically isolated from each other, but as a mother laminated body. Remains mechanically integrated,
The properties of individual laminated electronic components can be measured. Therefore, it is not necessary to handle a plurality of mechanically independent laminated electronic components, and the characteristics of a large number of laminated electronic components can be efficiently measured by screening, for example.
【００１９】また、上述した特性測定を実施するための
形態である、溝が形成されたマザー積層体からなる積層
電子部品の集合体を、そのまま、出荷時の形態とすれ
ば、需要者側において、マザー積層体を溝に沿って分割
するだけで、そこから個々の積層電子部品を取出すこと
ができる。この場合、個々の積層電子部品は、その特性
測定を既に終えておくことができるので、問題なく実装
に供することができるとともに、積層電子部品の集合体
は、個々の積層電子部品がばらばらの状態にある場合に
比べて、その梱包および取扱いが容易である点に注目す
べきである。Further, if the aggregate of laminated electronic components, which is a form for carrying out the above-mentioned characteristic measurement and is composed of a mother laminate having grooves formed therein, is used as it is as a form at the time of shipment, on the consumer side. The individual laminated electronic components can be taken out from the mother laminated body only by dividing the mother laminated body along the grooves. In this case, the individual laminated electronic components can be subjected to mounting without any problem because the characteristics of the individual laminated electronic components can already be measured. It should be noted that it is easier to pack and handle than the case in.
【００２０】[0020]
【実施例】図１は、この発明の一実施例による積層電子
部品１０の外観を示す斜視図である。積層電子部品１０
は、図示したチップ状の形態で適宜の回路基板上に実装
されるが、図１では、このような回路基板側に向けられ
る主面を上方に向けた状態で、積層電子部品が１０が図
示されている。1 is a perspective view showing the external appearance of a laminated electronic component 10 according to an embodiment of the present invention. Multilayer electronic component 10
Is mounted on an appropriate circuit board in the form of the illustrated chip, but in FIG. 1, the laminated electronic component 10 is illustrated with the main surface facing the circuit board facing upward. Has been done.
【００２１】積層電子部品１０は、内部回路要素（図示
せず）を介在させた状態で複数の絶縁性シートが積層さ
れてなる積層体１１を備える。積層体１１のたとえば４
つの側面の各々には、積層体１１の外表面に露出する外
部電極１２が形成される。これら外部電極１２は、図示
しないが、内部回路要素に電気的に接続されている。The laminated electronic component 10 comprises a laminated body 11 in which a plurality of insulating sheets are laminated with an internal circuit element (not shown) interposed. For example, 4 of the laminated body 11
An external electrode 12 exposed on the outer surface of the stacked body 11 is formed on each of the two side surfaces. Although not shown, these external electrodes 12 are electrically connected to internal circuit elements.
【００２２】上述したような外部電極１２は、以下に述
べる製造方法の説明から明らかになるように、積層体１
１を貫通しないように積層体１１に設けられた穴に付与
された導電材を、穴の分割によって露出させることによ
って形成されたものである。また、積層体１１のたとえ
ば４つの側面の各々には、段差１３が形成されている
が、このような段差１３が形成される理由も、以下の製
造方法の説明から明らかになる。The external electrode 12 as described above has the laminated body 1 as will be apparent from the description of the manufacturing method described below.
1 is formed by exposing the conductive material provided in the holes provided in the laminated body 11 so as not to penetrate 1 through the division of the holes. Further, the step 13 is formed on each of the four side surfaces of the laminated body 11, for example. The reason why the step 13 is formed will be apparent from the following description of the manufacturing method.
【００２３】上述したような積層電子部品１０を得るた
め、図２に示すようなマザー積層体１４が用意される。
マザー積層体１４は、所定の分割線１５（一点鎖線）に
沿って分割することにより複数の積層電子部品１０を与
えるものであって、分割線１５によって区画される各領
域に個々の積層電子部品１０のための内部回路要素（図
示せず）を分布させるように、これら内部回路要素を介
在させた状態で複数のマザー絶縁性シート１６および１
７が積層されてなるものである。In order to obtain the laminated electronic component 10 as described above, a mother laminated body 14 as shown in FIG. 2 is prepared.
The mother laminated body 14 provides a plurality of laminated electronic components 10 by dividing the laminated electronic components 10 along a predetermined dividing line 15 (one-dot chain line). A plurality of mother insulating sheets 16 and 1 with the internal circuit elements interposed so that the internal circuit elements (not shown) for 10 are distributed.
7 is laminated.
【００２４】上述のようなマザー積層体１４を得るた
め、たとえば、以下のような工程が実施される。なお、
この実施例では、マザー絶縁性シート１６および１７
は、セラミックシートから構成される。To obtain the mother laminated body 14 as described above, for example, the following steps are carried out. In addition,
In this example, the mother insulating sheets 16 and 17 are
Is composed of a ceramic sheet.
【００２５】まず、ドクターブレード法などにより、シ
ート成形を行ない、マザー絶縁性シート１６および１７
となるべきセラミックグリーンシートを得る。これらセ
ラミックグリーンシートの特定のものには、シートを厚
み方向に貫通する電気的導通を可能とするため、ビアホ
ール等がパンチング等により形成される。次に、セラミ
ックグリーンシートの特定のものの上には、内部回路要
素となるべき導電膜および／または抵抗膜が印刷され
る。このとき、既に形成されたビアホール内に、導電材
が充填されればよい。First, sheet formation is performed by a doctor blade method or the like, and mother insulating sheets 16 and 17 are formed.
Get a ceramic green sheet that should be. A via hole or the like is formed in a particular one of these ceramic green sheets by punching or the like in order to enable electrical conduction through the sheet in the thickness direction. Next, a conductive film and / or a resistance film to be an internal circuit element is printed on a specific one of the ceramic green sheets. At this time, a conductive material may be filled in the already formed via hole.
【００２６】次に、上述したようなマザー絶縁性シート
１６および１７が積み重ねられ、プレスされる。これに
よって、マザー積層体１４が得られる。このマザー積層
体１４の一部の断面図が図３（ａ）に示されている。Next, the mother insulating sheets 16 and 17 as described above are stacked and pressed. Thereby, the mother laminated body 14 is obtained. A partial cross-sectional view of the mother laminated body 14 is shown in FIG.
【００２７】次に、図２および図３（ｂ）に示すよう
に、マザー積層体１４の、分割線１５を通る位置に、た
とえばドリル等により、所定の深さの穴１９が形成され
る。これら穴１９は、マザー積層体１４を貫通しない。
したがって、このような穴１９は、図２において比較的
上部に位置するマザー絶縁性シート１６に形成され、比
較的下部に位置するマザー絶縁性シート１７には穴１９
が届いていないと理解すればよい。Next, as shown in FIGS. 2 and 3B, a hole 19 having a predetermined depth is formed in the mother laminated body 14 at a position passing through the dividing line 15 by, for example, a drill. These holes 19 do not penetrate the mother laminate 14.
Therefore, such holes 19 are formed in the mother insulating sheet 16 located relatively above in FIG. 2, and the holes 19 are formed in the mother insulating sheet 17 located relatively below.
Just understand that it has not arrived.
【００２８】次に、図３（ｃ）に示すように、穴１９内
に導電材１８が付与される。この導電材１８は、図示し
ないが、内部回路要素と電気的に接続される。導電材１
８の付与は、たとえば、導電ペーストを、ディスペンサ
またはスクリーン印刷などにより穴１９内に充填するこ
とによって行なわれる。Next, as shown in FIG. 3C, the conductive material 18 is applied in the hole 19. Although not shown, the conductive material 18 is electrically connected to internal circuit elements. Conductive material 1
The application of 8 is performed, for example, by filling the hole 19 with a conductive paste by a dispenser or screen printing.
【００２９】上述した穴１９を形成しようとするとき、
上述したように、マザー積層体１４を得てから、このマ
ザー積層体１４の厚み方向の途中まで達するように穴１
９を設ける方法だけでなく、たとえば、図２に示したマ
ザー積層体１４の比較的上部を構成する複数のマザー絶
縁性シート１６を、比較的下部のマザー絶縁性シート１
７とは別に積層し、このように積層された複数のマザー
絶縁性シート１６に穴１９となるべき貫通孔を、たとえ
ばパンチング、ドリル、レーザ等により設けておき、そ
の後、マザー絶縁性シート１６をマザー絶縁性シート１
７上に積層する方法を採用してもよい。これらの方法で
は、穴１９が１回の工程で同時形成されるので、穴１９
の内周面を容易に平滑にできる。しかしながら、マザー
絶縁性シート１６を積層する前に、個々のマザー絶縁性
シート１６に穴１９となるべき貫通孔を予め設けてお
き、これら貫通孔が整列するように、マザー絶縁性シー
ト１６を積層するようにしてもよい。When trying to form the hole 19 described above,
As described above, after the mother laminated body 14 is obtained, the hole 1 is formed so as to reach the mother laminated body 14 partway in the thickness direction.
9, the plurality of mother insulating sheets 16 forming the relatively upper portion of the mother laminated body 14 shown in FIG.
7 are laminated separately from each other, and through holes which are to be the holes 19 are provided in the plurality of mother insulating sheets 16 thus laminated by, for example, punching, drilling, laser or the like, and then the mother insulating sheet 16 is Mother insulating sheet 1
A method of laminating on 7 may be adopted. In these methods, the holes 19 are formed at the same time in a single process, so the holes 19
The inner peripheral surface of can be easily smoothed. However, before the mother insulating sheets 16 are laminated, the through holes to be the holes 19 are provided in advance in each of the mother insulating sheets 16, and the mother insulating sheets 16 are laminated so that these through holes are aligned. You may do it.
【００３０】次に、図３（ｄ）および図４に示すよう
に、マザー積層体１４には、分割線１５に沿って溝２０
がたとえばダイシングソーによって形成される。溝２０
は、穴１９内の導電材１８を複数部分に分割して各部分
を互いに電気的に独立させるような深さに選ばれる。こ
れによって、導電材１８は、溝２０の側面において露出
する状態となる。Next, as shown in FIGS. 3D and 4, the groove 20 is formed along the dividing line 15 in the mother laminated body 14.
Are formed by, for example, a dicing saw. Groove 20
Is selected to have a depth such that the conductive material 18 in the hole 19 is divided into a plurality of parts and the parts are electrically isolated from each other. As a result, the conductive material 18 is exposed on the side surface of the groove 20.
【００３１】次に、図３（ｅ）および図４に示すよう
に、必要に応じて、溝２０の底面とそれに対向するマザ
ー積層体１４の下面に、それぞれ、スリット２１および
２２が設けられる。スリット２１および２２は、いずれ
か一方が省略されてもよい。Next, as shown in FIGS. 3 (e) and 4, slits 21 and 22 are provided on the bottom surface of the groove 20 and the lower surface of the mother laminated body 14 facing it, respectively, if necessary. One of the slits 21 and 22 may be omitted.
【００３２】なお、図４において、内部回路要素となる
べき導電膜２３および２４が図示されている。また、導
電膜２３が導電材１８に電気的に接続されている状態も
図示されている。Incidentally, in FIG. 4, conductive films 23 and 24 to be internal circuit elements are shown. Further, a state in which the conductive film 23 is electrically connected to the conductive material 18 is also illustrated.
【００３３】次に、マザー積層体１４は、マザー絶縁性
シート１６および１７を構成するセラミックを焼結させ
るため、焼成される。その後、必要に応じて、マザー積
層体１４の表面に、導電膜および／または抵抗膜が形成
され、また、オーバーコートが施され、また、ソルダー
レジストが付与される。また、必要に応じて、外部電極
１２となるべき導電材１８や他の導電膜にめっきが施さ
れる。Next, the mother laminated body 14 is fired in order to sinter the ceramics constituting the mother insulating sheets 16 and 17. Thereafter, if necessary, a conductive film and / or a resistance film is formed on the surface of the mother laminated body 14, an overcoat is applied, and a solder resist is applied. In addition, the conductive material 18 or other conductive film to be the external electrode 12 is plated if necessary.
【００３４】以上の工程を終えたとき、マザー積層体１
４に含まれる複数の積層電子部品１０は、互いに他のも
のに対して電気的に独立しているので、溝２０によって
分断された穴１９の各部分に存在する導電材１８を外部
電極として、個々の積層電子部品１０の特性を測定する
ことができる。When the above steps are completed, the mother laminated body 1
Since the plurality of laminated electronic components 10 included in 4 are electrically independent from each other, the conductive material 18 present in each part of the hole 19 divided by the groove 20 is used as an external electrode. The characteristics of each laminated electronic component 10 can be measured.
【００３５】このように、特性が測定された後、良品と
判断された積層電子部品１０上には、必要に応じて、複
合化のための他の電子部品が実装される。ここまで述べ
た工程は、マザー積層体１４の状態で能率的に行なうこ
とができる。なお、積層電子部品１０の出荷をこの段階
で行なってもよい。As described above, after the characteristics have been measured, other electronic components for compounding are mounted on the laminated electronic component 10 determined to be non-defective, if necessary. The steps described so far can be efficiently performed in the state of the mother laminated body 14. The laminated electronic component 10 may be shipped at this stage.
【００３６】次に、機械的に独立した複数の積層電子部
品１０を得るため、マザー積層体１４は、分割線１５す
なわち溝２０に沿って完全に分割される。この分割は、
チョコレートを割るように、マザー積層体１４を溝２０
に沿って割ることにより容易に達成される。前述したス
リット２１および２２は、このような分割をより容易に
する。なお、このような分割は、溝２０の幅よりも薄い
刃厚のダイシングソーで切断することによって達成して
もよい。Next, in order to obtain a plurality of mechanically independent laminated electronic components 10, the mother laminated body 14 is completely divided along the dividing line 15, that is, the groove 20. This division is
Groove the mother laminate 14 into the groove 20 so as to break the chocolate.
Easily achieved by splitting along. The slits 21 and 22 described above make such division easier. Note that such division may be achieved by cutting with a dicing saw having a blade thickness smaller than the width of the groove 20.
【００３７】このようにして、図１に示した積層電子部
品１０が得られる。以上述べた説明からわかるように、
段差１３は、前述した溝２０の形成の結果もたらされた
ものである。また、積層体１１を、段差１３の位置に対
応する境界面によって２つの部分に区分したとき、外部
電極１２は、一方の部分においてのみ形成されている。
そのため、図１に示した姿勢にある積層電子部品１０の
下方の主面（図１において隠れている側の主面）側で
は、外部電極１２が届いておらず、したがって、この主
面を、外部電極１２に干渉されることなく、他の電子部
品のための実装面として広く利用することができる。In this way, the laminated electronic component 10 shown in FIG. 1 is obtained. As can be seen from the above description,
The step 13 is a result of the formation of the groove 20 described above. When the laminated body 11 is divided into two parts by the boundary surface corresponding to the position of the step 13, the external electrode 12 is formed only in one part.
Therefore, the external electrode 12 does not reach the lower main surface (main surface hidden in FIG. 1) of the laminated electronic component 10 in the posture shown in FIG. It can be widely used as a mounting surface for other electronic components without being interfered by the external electrodes 12.
【００３８】次に、積層電子部品１０は、必要に応じ
て、ケーシングされる。このケーシングは、積層電子部
品１０の図１による下方の主面に他の部品が実装された
とき、これを覆うものである。Next, the laminated electronic component 10 is casing if necessary. This casing covers other components mounted on the lower main surface of the laminated electronic component 10 according to FIG.
【００３９】以上、この発明を図１ないし図４に図示し
た実施例に関連して説明したが、この発明の範囲内にお
いて、その他いくつかの変形例が可能である。Although the present invention has been described above with reference to the embodiments shown in FIGS. 1 to 4, several other modifications are possible within the scope of the present invention.
【００４０】たとえば、マザー積層体１４の焼成工程
は、図３（ｂ）の工程の前、同（ｃ）の工程の前、同
（ｄ）の工程の前、または同（ｅ）の工程の前に実施し
てもよい。このような焼成工程の後に図３（ｃ）の工程
が実施される場合、穴１９内に導電材１８を付与するこ
とを、乾式めっきによってもよい。For example, the step of firing the mother laminate 14 is performed before the step shown in FIG. 3B, before the step shown in FIG. 3C, before the step shown in FIG. 3D, or before the step shown in FIG. It may be performed before. When the step of FIG. 3C is performed after such a firing step, the conductive material 18 may be provided in the hole 19 by dry plating.
【００４１】また、上述した図示の実施例における焼成
工程以降の工程については、その少なくともいくつかが
省略されても、その順序が変更されてもよい。Regarding the steps after the firing step in the illustrated embodiment described above, at least some of them may be omitted or the order thereof may be changed.
【００４２】また、穴１９の断面形状は、円形とされた
が、四角形等の他の形状に変更されてもよい。Although the cross-sectional shape of the hole 19 is circular, it may be changed to another shape such as a quadrangle.
【００４３】また、この発明で用いられる絶縁性シート
は、セラミックシートに限らず、他の材料からなる絶縁
性シートに置き換えられてもよい。The insulating sheet used in the present invention is not limited to the ceramic sheet, and may be replaced with an insulating sheet made of another material.
【００４４】また、この発明は、複数の外部電極のすべ
てが穴内に付与された導電材に基づいて形成された積層
電子部品に限らず、外部電極のいくつかが他の方法によ
って形成された積層電子部品にも適用することができ
る。Further, the present invention is not limited to the laminated electronic component in which all of the plurality of external electrodes are formed on the basis of the conductive material provided in the holes, but a laminated structure in which some of the external electrodes are formed by another method. It can also be applied to electronic components.
【図１】この発明の一実施例による積層電子部品１０の
外観を示す斜視図である。FIG. 1 is a perspective view showing an appearance of a laminated electronic component 10 according to an embodiment of the present invention.
【図２】図１に示した積層電子部品１０を得るために準
備されるマザー積層体１４を示す斜視図である。2 is a perspective view showing a mother laminate 14 prepared to obtain the laminated electronic component 10 shown in FIG.
【図３】図２に示したマザー積層体１４に対して順次施
される種々工程を示す断面図である。FIG. 3 is a cross-sectional view showing various steps sequentially performed on the mother laminated body 14 shown in FIG.
【図４】図３（ｅ）に示した工程によって得られたマザ
ー積層体１４の一部を示す拡大斜視図である。4 is an enlarged perspective view showing a part of the mother laminated body 14 obtained by the step shown in FIG. 3 (e).
【図５】この発明にとって興味ある従来の積層電子部品
１の外観を示す斜視図である。FIG. 5 is a perspective view showing an appearance of a conventional laminated electronic component 1 which is of interest to the present invention.
１０ 積層電子部品 １１ 積層体 １２ 外部電極 １４ マザー積層体 １５ 分割線 １６，１７ マザー絶縁性シート １８ 導電材 １９ 穴 ２０ 溝 ２３，２４ 導電膜（内部回路要素） 10 Multi-layer electronic components 11 laminate 12 external electrodes 14 mother laminate 15 dividing line 16,17 Mother insulating sheet 18 Conductive material 19 holes 20 grooves 23, 24 conductive film (internal circuit element)
フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ Ｈ０５Ｋ 3/40 Ｈ０５Ｋ 3/40 Ｄ 3/46 3/46 Ｎ Ｗ Continuation of front page (51) Int.Cl. 7 Identification code FI H05K 3/40 H05K 3/40 D 3/46 3/46 N W
Claims (6)
絶縁性シートが積層されてなる積層体、および、前記内
部回路要素に電気的に接続されかつ前記積層体の外表面
に形成された外部電極を備え、 前記積層体は、側面に段差を有し、該段差の位置に対応
する境界面によって２つの部分に区分したとき、前記外
部電極は一方の部分に形成されており、かつ、複数の主
面のうちの少なくとも前記外部電極が形成されていない
側の積層体の主面が電子部品の実装面を構成する、積層
電子部品。1. A laminated body in which a plurality of insulating sheets are laminated with an internal circuit element interposed, and an electrically connected to the internal circuit element and formed on an outer surface of the laminated body. An external electrode, wherein the laminate has a step on a side surface, and when divided into two parts by a boundary surface corresponding to the position of the step, the external electrode is formed on one part, and A laminated electronic component in which at least the principal surface of the laminated body on the side on which the external electrode is not formed among a plurality of principal surfaces constitutes a mounting surface of the electronic component.
する境界面には届いていない、請求項１に記載の積層電
子部品。2. The laminated electronic component according to claim 1, wherein the external electrode does not reach a boundary surface corresponding to the position of the step.
って複数の積層電子部品が得られるものであって、前記
分割線によって区画される各領域に個々の前記積層電子
部品のための内部回路要素を分布させるように、これら
内部回路要素を介在させた状態で複数のマザー絶縁シー
トが積層されてなるものであり、前記分割線を通る位置
に、貫通しない穴が設けられた、マザー積層体を準備
し、 前記穴内に、前記内部回路要素に電気的に接続させる導
電材を付与し、 複数の主面のうちの少なくとも前記マザー積層体の前記
穴が設けられた側の主面に、前記穴内の前記導電材を複
数部分に分割して各部分を互いに電気的に独立させるよ
うに、前記分割線に沿って溝を形成した後、前記マザー
積層体を前記分割線に沿って分割することにより、前記
複数の積層電子部品のそれぞれの側面の周囲に段差を形
成する、 各工程を備える、積層電子部品の製造方法。3. A plurality of laminated electronic components can be obtained by dividing along a predetermined dividing line, and an internal circuit for each of the laminated electronic components is provided in each region divided by the dividing line. A mother laminate in which a plurality of mother insulating sheets are laminated with these internal circuit elements interposed so as to distribute the elements, and holes not passing through are provided at positions passing through the dividing lines. prepare, in said bore, said internal circuit elements impart electrically connected to a conductive material, at least on the hole on the side that is provided the major surface of said mother laminate of a plurality of main surfaces, said If the conductive material in the hole is
Divide into several parts and make each part electrically independent of each other.
As described above, after forming a groove along the dividing line, dividing the mother laminated body along the dividing line to form a step around each side surface of the plurality of laminated electronic components. A method of manufacturing a laminated electronic component, comprising:
後、マザー積層体を分割線に沿って分割する前記工程の
前に、前記マザー積層体を焼成する工程を備える、請求
項３記載の積層電子部品の製造方法。 4. A method for forming a groove along a parting line, comprising:
After that, in the step of dividing the mother laminated body along the division line.
Before, comprising the step of firing the mother laminate
Item 3. A method for manufacturing a laminated electronic component according to Item 3.
って複数の積層電子部品が得られるものであって、前記
分割線によって区画される各領域に個々の前記積層電子
部品のための内部回路要素を分布させるように、これら
内部回路要素を介在させた状態で複数のマザー絶縁性シ
ートが積層されてなるものであり、前記分割線を通る位
置には貫通しない穴が設けられ、前記穴内に、前記内部
回路要素に電気的に接続される導電材が付与された、マ
ザー積層体を準備し、 前記穴内の前記導電材を複数部分に分割して各部分を互
いに電気的に独立させるように、前記分割線に沿って前
記マザー積層体に溝を形成し、 分割された前記導電材の各部分を外部電極として個々の
積層電子部品の特性を測定する、 各工程を備える、積層電子部品の特性測定方法。5. A plurality of laminated electronic components are obtained by dividing along a predetermined dividing line, and an internal circuit for each of the laminated electronic components is provided in each region divided by the dividing line. In order to distribute the elements, a plurality of mother insulating sheets are laminated with these internal circuit elements interposed, and a hole that does not penetrate is provided at a position passing through the dividing line. Preparing a mother laminated body to which a conductive material electrically connected to the internal circuit element is provided, and dividing the conductive material in the hole into a plurality of parts so that the respective parts are electrically independent from each other. A groove is formed in the mother laminated body along the dividing line, and the characteristic of each laminated electronic component is measured by using each divided portion of the conductive material as an external electrode. Characteristic measurement Method.
って複数の積層電子部品が得られるものであって、前記
分割線によって区画される各領域に個々の前記積層電子
部品のための内部回路要素を分布させるように、これら
内部回路要素を介在させた状態で複数のマザー絶縁性シ
ートが積層されてなり、かつ前記分割線を通る位置には
貫通しない穴が設けられ、前記穴内に、前記内部回路要
素に電気的に接続される導電材が付与された、マザー積
層体を備え、 前記マザー積層体には、前記穴内の前記導電材を複数部
分に分割して各部分を互いに電気的に独立させるよう
に、前記分割線に沿って溝が形成された、 積層電子部品の集合体。6. A plurality of laminated electronic components are obtained by dividing along a predetermined dividing line, and an internal circuit for each of the laminated electronic components is provided in each region divided by the dividing line. In order to distribute the elements, a plurality of mother insulating sheets are laminated with these internal circuit elements interposed, and a hole that does not penetrate is provided at a position that passes through the dividing line. A conductive material that is electrically connected to the internal circuit element is provided, and a mother laminated body is provided, and the mother laminated body is divided into a plurality of portions of the conductive material in the hole to electrically connect each portion to each other. A group of laminated electronic components, wherein grooves are formed along the dividing lines so as to be independent.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33185293A JP3368645B2 (en) | 1993-12-27 | 1993-12-27 | LAMINATED ELECTRONIC COMPONENT, ITS MANUFACTURING METHOD AND ITS CHARACTERISTIC MEASUREMENT METHOD |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33185293A JP3368645B2 (en) | 1993-12-27 | 1993-12-27 | LAMINATED ELECTRONIC COMPONENT, ITS MANUFACTURING METHOD AND ITS CHARACTERISTIC MEASUREMENT METHOD |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07192961A JPH07192961A (en) | 1995-07-28 |
| JP3368645B2 true JP3368645B2 (en) | 2003-01-20 |
Family
ID=18248378
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP33185293A Expired - Lifetime JP3368645B2 (en) | 1993-12-27 | 1993-12-27 | LAMINATED ELECTRONIC COMPONENT, ITS MANUFACTURING METHOD AND ITS CHARACTERISTIC MEASUREMENT METHOD |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3368645B2 (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002141248A (en) | 2000-11-02 | 2002-05-17 | Murata Mfg Co Ltd | Ceramic electronic component and its manufacturing method |
| US6760227B2 (en) | 2000-11-02 | 2004-07-06 | Murata Manufacturing Co., Ltd. | Multilayer ceramic electronic component and manufacturing method thereof |
| JP4696443B2 (en) * | 2003-09-19 | 2011-06-08 | 株式会社村田製作所 | Manufacturing method of multilayer ceramic substrate |
| JP4502675B2 (en) * | 2004-03-22 | 2010-07-14 | 京セラ株式会社 | Multiple wiring board |
| JP4688554B2 (en) * | 2004-12-01 | 2011-05-25 | 株式会社リコー | Manufacturing method of electronic component mounting body |
| JP5743779B2 (en) * | 2010-07-27 | 2015-07-01 | 京セラ株式会社 | Multi-circuit board and electronic device |
| JP5753734B2 (en) * | 2011-05-19 | 2015-07-22 | 日本特殊陶業株式会社 | Wiring board, multi-cavity wiring board, and manufacturing method thereof |
| KR101922191B1 (en) * | 2012-03-02 | 2019-02-20 | 엘지이노텍 주식회사 | Printed circuit board and method for manufacturing the same |
| WO2014103541A1 (en) * | 2012-12-27 | 2014-07-03 | 日本碍子株式会社 | Electronic component and method for manufacturing same |
| JP5859678B1 (en) * | 2014-05-30 | 2016-02-10 | 株式会社メイコー | Method for manufacturing printed wiring board |
| WO2017134993A1 (en) * | 2016-02-02 | 2017-08-10 | 株式会社村田製作所 | Surface mount type coil component, method of manufacturing same, and dc-dc converter using same |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61269336A (en) * | 1985-05-24 | 1986-11-28 | Hitachi Vlsi Eng Corp | Semiconductor device |
| JPH03280412A (en) * | 1990-03-29 | 1991-12-11 | Mitsubishi Materials Corp | Capacitor network structure and manufacture thereof |
-
1993
- 1993-12-27 JP JP33185293A patent/JP3368645B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07192961A (en) | 1995-07-28 |
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