JP3313250B2 - Substrate for mounting high frequency devices - Google Patents
Substrate for mounting high frequency devicesInfo
- Publication number
- JP3313250B2 JP3313250B2 JP23943494A JP23943494A JP3313250B2 JP 3313250 B2 JP3313250 B2 JP 3313250B2 JP 23943494 A JP23943494 A JP 23943494A JP 23943494 A JP23943494 A JP 23943494A JP 3313250 B2 JP3313250 B2 JP 3313250B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating layer
- conductor line
- characteristic impedance
- line
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
Landscapes
- Structure Of Printed Boards (AREA)
- Wire Bonding (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、高速で作動させる高周
波デバイスを収容するパッケージの本体等を構成する高
周波デバイス実装用基板に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-frequency device mounting board which constitutes a main body of a package for accommodating a high-frequency device operated at high speed.
【０００２】[0002]
【従来の技術】高集積化された高周波用の半導体チップ
等のデバイスを収容する多ピン構造のパッケージとし
て、ＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）パッケ
ージが開発され、使用されている。2. Description of the Related Art A BGA (Ball Grid Array) package has been developed and used as a package having a multi-pin structure for accommodating a device such as a highly integrated high-frequency semiconductor chip.
【０００３】ＢＧＡパッケージは、図４に示したよう
に、その本体を構成する基板１０下面に基板１０に備え
た信号線路３０、電源線路（図示せず）又はグランド線
路５４に電気的に接続された外部接続端子２０を複数個
格子状に並べて備えている。外部接続端子２０表面に
は、はんだバンプ２２を半球状に形成している。そし
て、基板１０下面の複数の外部接続端子２０をパッケー
ジ実装用のボード表面の接続端子（図示せず）にそれぞ
れ重ね合わせて、それらの外部接続端子２０をボードの
接続端子にはんだバンプ２２を用いてそれぞれはんだ付
け接続することにより、パッケージをボードに表面実装
できるようにしている。As shown in FIG. 4, the BGA package is electrically connected to a signal line 30, a power supply line (not shown) or a ground line 54 provided on the substrate 10 on the lower surface of the substrate 10 constituting the main body. And a plurality of external connection terminals 20 arranged in a lattice. On the surface of the external connection terminal 20, a solder bump 22 is formed in a hemispherical shape. Then, the plurality of external connection terminals 20 on the lower surface of the substrate 10 are respectively superimposed on connection terminals (not shown) on the surface of the board for package mounting, and these external connection terminals 20 are used as connection terminals of the board by using solder bumps 22. The package can be surface-mounted on the board by soldering.
【０００４】このＢＧＡパッケージにおいては、その本
体を構成する基板１０を、セラミック等からなる絶縁層
１２を複数積層して形成している。基板の絶縁層１２間
には、メタライズ等からなるグランド層５０を薄層状に
連続して広く備えている。基板１０の上面には、メタラ
イズ等からなる細帯状の信号線路３０を備えている。そ
して、信号線路３０をその下方のグランド層５０により
マイクロストリップ線路構造に形成して、信号線路３０
の特性インピーダンスを所定値の５０Ω等にマッチング
させている。In this BGA package, a substrate 10 constituting a main body is formed by laminating a plurality of insulating layers 12 made of ceramic or the like. A ground layer 50 made of metallization or the like is continuously provided in a thin layer between the insulating layers 12 of the substrate. On the upper surface of the substrate 10, there is provided a strip-shaped signal line 30 made of metallization or the like. Then, the signal line 30 is formed into a microstrip line structure by the ground layer 50 thereunder, and the signal line 30 is formed.
Is matched to a predetermined value such as 50Ω.
【０００５】この基板上面の信号線路３０の特性インピ
ーダンスＺ0 の値は、次の式から得られることが知られ
ている。It is known that the value of the characteristic impedance Z 0 of the signal line 30 on the upper surface of the substrate can be obtained from the following equation.
【０００６】[0006]
【数１】 (Equation 1)
【０００７】数１の式において、信号線路３０の幅ｗと
その厚さｔ、信号線路３０とグランド層５０との間の距
離ｈ、即ち絶縁層１２の層厚ｈは、図６に示した部位を
それぞれ示している。In the equation (1), the width w and the thickness t of the signal line 30 and the distance h between the signal line 30 and the ground layer 50, that is, the thickness h of the insulating layer 12, are shown in FIG. Each part is shown.
【０００８】基板１０には、タングステンメタライズ等
のメタライズを充填したビア等からなる円柱状の導体線
路６０を、基板１０を構成する複数の絶縁層１２を上下
に連続して貫通させて備えている。導体線路６０の上下
端は、基板上面の信号線路３０と基板下面の所定の外部
接続端子２０とにそれぞれ一連に接続している。導体線
路６０と交叉するグランド層５０部分には、図５に示し
たように、円形状の透孔５２を、導体線路６０を中心に
開口している。そして、導体線路６０をグランド層５０
により擬似同軸線路構造に形成している。The substrate 10 is provided with a columnar conductor line 60 made of a via or the like filled with metallized metal such as tungsten metallized by continuously penetrating a plurality of insulating layers 12 constituting the substrate 10 vertically. . The upper and lower ends of the conductor line 60 are connected to the signal line 30 on the upper surface of the substrate and the predetermined external connection terminals 20 on the lower surface of the substrate, respectively. As shown in FIG. 5, a circular through hole 52 is opened in the ground layer 50 crossing the conductor line 60 around the conductor line 60. Then, the conductor line 60 is connected to the ground layer 50.
To form a pseudo coaxial line structure.
【０００９】このグランド層の透孔５２に遊挿した導体
線路部分６０ａの特性インピーダンスＺ0 の値は、次の
式から得られることが知られている。It is known that the value of the characteristic impedance Z 0 of the conductor line portion 60a loosely inserted into the through hole 52 of the ground layer can be obtained from the following equation.
【００１０】[0010]
【数２】 (Equation 2)
【００１１】数２の式において、グランド層の透孔５２
の内径Ｄ、円柱状をした導体線路６０の外径ｄは、図５
に示した部位をそれぞれ示している。In the equation (2), the through hole 52 in the ground layer
5 and the outer diameter d of the cylindrical conductor line 60 are shown in FIG.
Are shown, respectively.
【００１２】グランド層５０は、基板の最上層の絶縁層
１２より下方の複数の絶縁層１２に上下に連続して貫通
させて備えたグランド線路５４を介して、基板下面の所
定の外部接続端子２０に一連に接続していて、グランド
層５０を接地できるようにしている。The ground layer 50 is provided with a predetermined external connection terminal on the lower surface of the substrate via a ground line 54 which is vertically penetrated through a plurality of insulating layers 12 below the uppermost insulating layer 12 of the substrate. 20 are connected in series so that the ground layer 50 can be grounded.
【００１３】グランド層５０に開口した透孔５２は、そ
の内径を数２の式のＤから得られる大きさに形成してい
る。この数２の式によれば、基板の絶縁層１２が比誘電
率εr が９．５のアルミナセラミックで形成されてい
て、導体線路６０の外径が０．１ｍｍのときに、導体線
路６０の特性インピーダンスＺ0 を５０Ωにマッチング
させようとする場合には、グランド層５０に開口する透
孔５２の内径Ｄを約１．３０８ｍｍとすれば良いことが
判る。この数２の式を用いてグランド層の透孔５２の内
径Ｄを設定した場合には、グランド層の透孔５２に遊挿
した導体線路部分６０ａの特性インピーダンスを数２の
式から得られる所定値のＺ0 に正確にマッチングさせる
ことができる。The through-hole 52 opened in the ground layer 50 has an inner diameter formed to be a size obtained from D in Equation (2). According to the equation (2), when the insulating layer 12 of the substrate is formed of alumina ceramic having a relative dielectric constant ε r of 9.5 and the outer diameter of the conductor line 60 is 0.1 mm, In order to match the characteristic impedance Z 0 to 50Ω, it can be understood that the inner diameter D of the through hole 52 opened in the ground layer 50 should be about 1.308 mm. When the inner diameter D of the through hole 52 in the ground layer is set using the equation (2), the characteristic impedance of the conductor line portion 60a loosely inserted into the through hole 52 in the ground layer is determined by a predetermined value obtained from the equation (2). It can be matched exactly to the value Z 0 .
【００１４】そのため、上記ＢＧＡパッケージにおいて
は、図７に示したように、基板の最上層の絶縁層１２よ
り下方の基板１０部分を多数の薄い絶縁層１２を積層し
て形成している。そして、それらの多数の絶縁層１２間
にグランド層５０をそれぞれ備えて、それらのグランド
層５０に開口した透孔５２に導体線路６０を連続して遊
挿している。そして、それらの多数のグランド層５０を
用いて高周波信号を伝える導体線路６０を同軸線路に近
い擬似同軸線路構造に形成している。そして、導体線路
６０の特性インピーダンスを導体線路６０のほぼ全長に
亙って数２の式から得られる特性インピーダンスのＺ0
に近づけている。そして、その導体線路６０を高周波信
号を伝送損失少なく伝えることができるようにしてい
る。Therefore, in the BGA package, as shown in FIG. 7, a portion of the substrate 10 below the uppermost insulating layer 12 of the substrate is formed by laminating a large number of thin insulating layers 12. The ground layers 50 are provided between the plurality of insulating layers 12, respectively, and the conductor lines 60 are continuously inserted into the through holes 52 opened in the ground layers 50. The conductor line 60 for transmitting a high-frequency signal is formed in a pseudo coaxial line structure close to a coaxial line by using the ground layers 50. Then, the characteristic impedance of the conductor line 60 is set to Z 0 of the characteristic impedance obtained from the equation (2) over substantially the entire length of the conductor line 60.
Approaching. The conductor line 60 can transmit a high-frequency signal with little transmission loss.
【００１５】最上層の絶縁層１２は、基板上面のマイク
ロストリップ線路構造をした信号線路３０の特性インピ
ーダンスを所定値の５０Ω等にマッチングさせるため
に、数１の式のＺ0 を５０Ω等とした場合に、数１の式
から得られる層厚ｈにその厚さを形成している。In order to match the characteristic impedance of the signal line 30 having the microstrip line structure on the upper surface of the substrate to the predetermined value of 50Ω or the like, the uppermost insulating layer 12 is set to Z 0 of the formula 1 as 50Ω or the like. In this case, the thickness is formed on the layer thickness h obtained from the equation (1).
【００１６】[0016]
【発明が解決しようとする課題】しかしながら、上記の
ようにして、ＢＧＡパッケージの基板１０を形成した場
合には、導体線路６０の特性インピーダンスを５０Ω等
にマッチングさせようとすると、グランド層５０に開口
する透孔５２の内径Ｄが、前述のように約１．３０８ｍ
ｍ等と大きくなってしまった。そして、基板１０の下面
に外部接続端子２０を一般に汎用されている１．２７ｍ
ｍ等の小ピッチＨで複数個格子状に並べて備えるため
に、基板１０に導体線路６０を１．２７ｍｍ等の小ピッ
チＨで並べて備えようとした場合に、図８に示したよう
に、導体線路６０を遊挿するためのグランド層５０に開
口した透孔５２がそれに隣合う同じグランド層５０に開
口した透孔５２の一部に重なり合ってしまった。そし
て、グランド層の透孔５２に遊挿した導体線路部分６０
ａの特性インピーダンスを数２の式から得られる特性イ
ンピーダンスの５０Ω等にマッチングさせることが不可
能となってしまった。However, when the substrate 10 of the BGA package is formed as described above, if the characteristic impedance of the conductor line 60 is to be matched to 50Ω or the like, an opening is formed in the ground layer 50. The inner diameter D of the through hole 52 is about 1.308 m as described above.
m and so on. The external connection terminal 20 is provided on the lower surface of the substrate 10 at 1.27 m which is generally used.
When a plurality of conductor lines 60 are arranged on the substrate 10 at a small pitch H such as 1.27 mm in order to arrange them in a lattice at a small pitch H such as m, as shown in FIG. The through hole 52 opened in the ground layer 50 for inserting the line 60 loosely overlaps a part of the through hole 52 opened in the same ground layer 50 adjacent thereto. The conductor line portion 60 loosely inserted into the through hole 52 of the ground layer
It has become impossible to match the characteristic impedance of a with the characteristic impedance of 50Ω obtained from the equation (2).
【００１７】そこで、本発明者らは、鋭意研究の末、グ
ランド層５０に開口する透孔５２の内径を数２の式から
得られる透孔の内径Ｄより狭めて、その透孔５２に遊挿
した導体線路部分６０ａの特性インピーダンスを低く抑
えても、基板１０を構成する絶縁層１２の層厚を厚く形
成すれば、基板１０に上下に貫通させて備えた導体線路
６０の特性インピーダンスを、グランド層の透孔５２に
遊挿した導体線路部分６０ａの特性インピーダンスに比
べて、高められることを発見した。Therefore, the present inventors have made intensive studies and made the inner diameter of the through hole 52 opened in the ground layer 50 smaller than the inner diameter D of the through hole obtained from the equation (2). Even if the characteristic impedance of the inserted conductor line portion 60a is kept low, if the thickness of the insulating layer 12 forming the substrate 10 is made large, the characteristic impedance of the conductor line 60 provided vertically through the substrate 10 can be reduced. It has been found that the characteristic impedance can be increased as compared with the characteristic impedance of the conductor line portion 60a loosely inserted into the through hole 52 of the ground layer.
【００１８】それと共に、基板１０を構成する絶縁層１
２の数を減少させて、絶縁層１２の層厚を厚く形成すれ
ば、基板１０に上下に貫通させて備えた導体線路６０の
共振周波数点を高周波領域側にシフトさせることができ
ることを発見した。At the same time, the insulating layer 1 forming the substrate 10
It has been found that, by reducing the number of 2 and increasing the thickness of the insulating layer 12, the resonance frequency point of the conductor line 60 provided vertically through the substrate 10 can be shifted to the high frequency region side. .
【００１９】そして、これらの発見に基づき、導体線路
６０の特性インピーダンスを所定値の５０Ω等にマッチ
ングさせると共に、導体線路６０下端に一連に接続され
た外部接続端子２０を基板１０の下面に１．２７ｍｍ等
の小ピッチで並べて備えた高周波デバイス実装用基板で
あって、導体線路６０の共振周波数点を高周波領域側に
シフトさせた高周波デバイス実装用基板を開発した。Based on these findings, the characteristic impedance of the conductor line 60 is matched to a predetermined value of 50Ω or the like, and the external connection terminals 20 connected in series to the lower end of the conductor line 60 are placed on the lower surface of the substrate 10. A high-frequency device mounting substrate which is arranged at a small pitch of 27 mm or the like and has a resonance frequency point of the conductor line 60 shifted to a high-frequency region side has been developed.
【００２０】即ち、本発明は、基板に備えた擬似同軸線
路構造をした導体線路の特性インピーダンスを所定値に
マッチングさせることができると共に、基板に備えた導
体線路下端に一連に接続された外部接続端子を基板の下
面に小ピッチで並べて備えることが可能な高周波デバイ
ス実装用基板であって、基板に備えた導体線路の共振周
波数点を高周波領域側にシフトさせることのできる高周
波デバイス実装用基板を提供することを目的としてい
る。That is, according to the present invention, it is possible to match the characteristic impedance of a conductor line having a quasi-coaxial line structure provided on a substrate to a predetermined value, and to connect an external connection serially connected to the lower end of the conductor line provided on the substrate. A high-frequency device mounting substrate capable of providing terminals arranged on the lower surface of the substrate at a small pitch, wherein the high-frequency device mounting substrate is capable of shifting a resonance frequency point of a conductor line provided on the substrate toward a high-frequency region. It is intended to provide.
【００２１】[0021]
【課題を解決するための手段】上記目的を達成するため
に、本発明の高周波デバイス実装用基板は、下部絶縁層
上に上部絶縁層をグランド層を介して積層して形成した
基板の上部絶縁層の上面に信号線路を備えて、該信号線
路をその下方の前記グランド層によりマイクロストリッ
プ線路構造に形成すると共に、前記基板に導体線路を前
記上部絶縁層と下部絶縁層とを連続して貫通させて備え
て、その導体線路の上下端を前記信号線路と前記下部絶
縁層の下面に備えた外部接続端子にそれぞれ一連に接続
し、さらに、前記導体線路と交叉する前記グランド層部
分に円形状の透孔を導体線路を中心に開口して、前記導
体線路を前記グランド層により擬似同軸線路構造に形成
してなる高周波デバイス実装用基板であって、前記グラ
ンド層の透孔の内径を、その透孔に遊挿した前記導体線
路部分の特性インピーダンスが所定値より低くなるよう
に小径に形成して、前記透孔に遊挿した導体線路部分の
特性インピーダンスを所定値より低下させると共に、前
記下部絶縁層の層厚を、その下部絶縁層に貫通させて備
えた前記導体線路部分の線路長が延長されてその導体線
路部分の特性インピーダンスが所定値より高くなるよう
に厚く形成して、該下部絶縁層に貫通させて備えた導体
線路部分の特性インピーダンスを所定値より上昇させ、
前記透孔に遊挿した導体線路部分の特性インピーダンス
の低下を前記下部絶縁層に貫通させて備えた導体線路部
分の特性インピーダンスの上昇分により相殺して、前記
導体線路の特性インピーダンスを所定値にマッチングさ
せたことを特徴としている。In order to achieve the above object, a substrate for mounting a high-frequency device according to the present invention comprises an upper insulating layer formed by laminating an upper insulating layer on a lower insulating layer via a ground layer. A signal line is provided on the upper surface of the layer, the signal line is formed in a microstrip line structure by the ground layer therebelow, and the conductor line is continuously penetrated through the upper insulating layer and the lower insulating layer on the substrate. The upper and lower ends of the conductor line are connected in series to external connection terminals provided on the lower surface of the signal line and the lower insulating layer, respectively, and further, a circular shape is formed on the ground layer portion crossing the conductor line. A high-frequency device mounting substrate, wherein the through-hole is opened around the conductor line, and the conductor line is formed in a pseudo-coaxial line structure by the ground layer. Is formed with a small diameter so that the characteristic impedance of the conductor line portion loosely inserted into the through hole is lower than a predetermined value, and the characteristic impedance of the conductor line portion loosely inserted into the through hole is reduced below a predetermined value. The thickness of the lower insulating layer is formed so as to be thicker so that the line length of the conductor line portion provided through the lower insulating layer is extended so that the characteristic impedance of the conductor line portion becomes higher than a predetermined value. Raising the characteristic impedance of the conductor line portion provided to penetrate the lower insulating layer from a predetermined value,
A decrease in the characteristic impedance of the conductor line portion loosely inserted into the through-hole is offset by an increase in the characteristic impedance of the conductor line portion provided through the lower insulating layer, so that the characteristic impedance of the conductor line becomes a predetermined value. It is characterized by matching.
【００２２】本発明の高周波デバイス実装用基板におい
ては、外部接続端子表面にはんだバンプを形成すること
を好適としている。In the high-frequency device mounting board of the present invention, it is preferable that a solder bump is formed on the surface of the external connection terminal.
【００２３】また、本発明の高周波デバイス実装用基板
においては、下部絶縁層の層厚を０．１２ｍｍ以上に厚
く形成することを好適としている。In the high-frequency device mounting board of the present invention, it is preferable that the lower insulating layer is formed to have a thickness of 0.12 mm or more.
【００２４】また、本発明の高周波デバイス実装用基板
においては、上部絶縁層と下部絶縁層とがセラミックか
らなり、グランド層がメタライズからなり、導体線路が
メタライズが充填されたビアからなることを好適として
いる。In the high frequency device mounting board of the present invention, it is preferable that the upper insulating layer and the lower insulating layer are made of ceramic, the ground layer is made of metallized, and the conductor line is made of a via filled with metallized. And
【００２５】[0025]
【作用】本発明の高周波デバイス実装用基板において
は、グランド層の透孔の内径を、設定しようとする導体
線路の特性インピーダンスＺ0 を求める数２の式から得
られる透孔の内径Ｄより小径に形成している。そして、
そのグランド層の透孔に遊挿した導体線路部分の特性イ
ンピーダンスＺ1 を、設定しようとする導体線路の特性
インピーダンスの所定値のＺ0 に比べて、低下させてい
る。In the high-frequency device mounting board of the present invention, the inner diameter of the through hole in the ground layer is smaller than the inner diameter D of the through hole obtained from the equation (2) for obtaining the characteristic impedance Z 0 of the conductor line to be set. Is formed. And
The characteristic impedance Z 1 of the conductor line portion is loosely inserted into the through hole of the ground layer, as compared with the Z 0 of the predetermined value of the characteristic impedance of the conductor line to be set, are reduced.
【００２６】それと共に、下部絶縁層の層厚を厚く形成
して、その下部絶縁層に貫通させて備えた導体線路部分
の線路長を延長している。そして、下部絶縁層に貫通さ
せて備えた導体線路部分の特性インピーダンスＺ2 を、
設定しようとする導体線路の特性インピーダンスの所定
値のＺ0 に比べて、上昇させている。At the same time, the thickness of the lower insulating layer is made thicker, and the line length of the conductor line portion penetrating the lower insulating layer is extended. Then, the characteristic impedance Z 2 of the conductor line portion provided so as to penetrate the lower insulating layer,
The characteristic impedance of the conductor line to be set is increased as compared with a predetermined value Z 0 of the characteristic impedance.
【００２７】そのため、グランド層の透孔に遊挿した導
体線路部分の特性インピーダンスＺ1 の低下を下部絶縁
層に貫通させて備えた導体線路部分の特性インピーダン
スＺ2 の上昇分により相殺して、基板の上部絶縁層と下
部絶縁層とに連続して貫通させて備えた導体線路の特性
インピーダンスを設定しようとする導体線路の特性イン
ピーダンスの所定値のＺ0 にマッチングさせることがで
きる。Therefore, the decrease in the characteristic impedance Z 1 of the conductor line portion loosely inserted into the through hole of the ground layer is offset by the increase in the characteristic impedance Z 2 of the conductor line portion provided through the lower insulating layer. can be matched to the Z 0 of the predetermined value of the characteristic impedance of the conductor line which is continuous with the upper insulating layer of the substrate and the lower insulating layer by through-attempts to set the characteristic impedance of the conductor line with it.
【００２８】それと共に、グランド層の透孔の内径を小
径に形成したため、基板の上部絶縁層と下部絶縁層とに
連続して貫通させて備えた導体線路のピッチを狭めて
も、グランド層に開口した透孔がそれに隣合う同じグラ
ンド層に開口した透孔の一部に重なり合うのを防ぐこと
ができる。At the same time, since the inner diameter of the through hole of the ground layer is formed to be small, even if the pitch of the conductor lines provided continuously through the upper insulating layer and the lower insulating layer of the substrate is narrowed, the pitch of the conductive line is reduced. It is possible to prevent the opened through hole from overlapping with a part of the through hole opened in the same ground layer adjacent thereto.
【００２９】その結果、基板の上部絶縁層と下部絶縁層
とに連続して貫通させて備えた複数本の導体線路のピッ
チを狭めて、それらの導体線路下端にそれぞれ一連に接
続された外部接続端子を基板の下面に小ピッチで並べて
備えることができる。As a result, the pitch of the plurality of conductor lines provided continuously penetrating through the upper insulating layer and the lower insulating layer of the substrate is reduced, and the external connection lines respectively connected to the lower ends of the conductor lines are serially connected. The terminals can be arranged on the lower surface of the substrate at a small pitch.
【００３０】さらに、上部絶縁層の層厚を調整して、上
部絶縁層上面の信号線路とその下方のグランド層との間
の距離を調整したり、信号線路の幅やその厚さを調整し
たりして、上部絶縁層上面のマイクロストリップ線路構
造をした信号線路の特性インピーダンスを設定しようと
する信号線路の特性インピーダンスの所定値のＺ0 にマ
ッチングさせることができる。Further, the thickness of the upper insulating layer is adjusted to adjust the distance between the signal line on the upper insulating layer and the ground layer thereunder, and the width and thickness of the signal line are adjusted. and or can be matched to the Z 0 of the predetermined value of the characteristic impedance of the signal line to be set to the characteristic impedance of the signal line in which the microstrip line structure of the upper insulating layer upper surface.
【００３１】また、本発明の高周波デバイス実装用基板
においては、基板を下部絶縁層と上部絶縁層との少数層
で形成して、下部絶縁層の層厚を厚く形成したため、基
板の上部絶縁層と下部絶縁層とに連続して貫通させて備
えた導体線路の共振周波数点を、高周波領域側にシフト
させることができる。In the high-frequency device mounting substrate of the present invention, the substrate is formed of a small number of lower insulating layers and an upper insulating layer, and the lower insulating layer is formed to have a large thickness. The resonance frequency point of the conductor line provided continuously penetrating through the lower insulating layer can be shifted to the high frequency region side.
【００３２】また、外部接続端子表面にはんだバンプを
形成した本発明の高周波デバイス実装用基板にあって
は、その外部接続端子をボード表面の接続端子に重ね合
わせて、外部接続端子をボードの接続端子に外部接続端
子に形成されたはんだバンプを用いて距離短くはんだ付
け接続できる。そして、外部接続端子とボード表面の接
続端子との間を高周波信号を伝送損失少なく伝えること
ができる。Further, in the high frequency device mounting substrate of the present invention in which solder bumps are formed on the surface of the external connection terminal, the external connection terminal is superimposed on the connection terminal on the board surface, and the external connection terminal is connected to the board. The terminals can be connected by soldering with a short distance by using solder bumps formed on the external connection terminals. Then, a high-frequency signal can be transmitted between the external connection terminal and the connection terminal on the board surface with little transmission loss.
【００３３】[0033]
【実施例】次に、本発明の実施例を図面に従い説明す
る。図１と図２は本発明の高周波デバイス実装用基板の
好適な実施例を示し、図１はその一部拡大正面断面図、
図２は図１のＡ―Ａ断面図である。以下に、この基板を
説明する。Next, an embodiment of the present invention will be described with reference to the drawings. 1 and 2 show a preferred embodiment of a high-frequency device mounting substrate according to the present invention, and FIG. 1 is a partially enlarged front sectional view thereof.
FIG. 2 is a sectional view taken along line AA of FIG. Hereinafter, this substrate will be described.
【００３４】図の高周波デバイス実装用基板では、基板
１０を下部絶縁層１２ａ上に上部絶縁層１２ｂを積層し
て形成している。下部絶縁層１２ａと上部絶縁層１２ｂ
とは、セラミックで形成している。In the high-frequency device mounting substrate shown in the figure, the substrate 10 is formed by laminating an upper insulating layer 12b on a lower insulating layer 12a. Lower insulating layer 12a and upper insulating layer 12b
Is formed of ceramic.
【００３５】基板１０には、円柱状の導体線路６０を上
部絶縁層１２ｂと下部絶縁層１２ａとを上下に連続して
貫通させて備えている。導体線路６０は、タングステン
メタライズ等のメタライズが充填されたビアで形成して
いる。The substrate 10 is provided with a columnar conductor line 60 in which the upper insulating layer 12b and the lower insulating layer 12a are vertically penetrated continuously. The conductor line 60 is formed by a via filled with metallization such as tungsten metallization.
【００３６】導体線路６０の上下端は、上部絶縁層１２
ｂの上面に備えた信号線路３０と下部絶縁層１２ａの下
面に備えたパッド状の外部接続端子２０とにそれぞれ一
連に接続している。信号線路３０と外部接続端子２０と
は、タングステンメタライズ等のメタライズでそれぞれ
形成している。The upper and lower ends of the conductor line 60 are connected to the upper insulating layer 12.
The signal lines 30 provided on the upper surface of the lower insulating layer 12a and the pad-shaped external connection terminals 20 provided on the lower surface of the lower insulating layer 12a are connected in series. The signal line 30 and the external connection terminal 20 are formed by metallization such as tungsten metallization.
【００３７】外部接続端子２０表面には、はんだバンプ
２２を半球状に形成している。そして、そのはんだバン
プ２２を用いて外部接続端子２０をボード表面の接続端
子（図示せず）にはんだ付け接続できるようにしてい
る。On the surface of the external connection terminal 20, a solder bump 22 is formed in a hemispherical shape. The solder bumps 22 are used to connect the external connection terminals 20 to connection terminals (not shown) on the board surface by soldering.
【００３８】上部絶縁層１２ｂと下部絶縁層１２ａとの
間には、タングステンメタライズ等のメタライズからな
るグランド層５０を薄層状に連続して広く備えている。Between the upper insulating layer 12b and the lower insulating layer 12a, a ground layer 50 made of metallized metal such as tungsten metallized is continuously provided in a thin layer.
【００３９】導体線路６０と交叉するグランド層５０部
分には、図２に示したように、円形状の透孔５２を導体
線路６０を中心に開口している。そして、そのグランド
層の透孔５２に導体線路６０を遊挿して、導体線路６０
をグランド層５０により擬似同軸線路構造に形成してい
る。As shown in FIG. 2, a circular through hole 52 is opened in the ground layer 50 crossing the conductor line 60 with the conductor line 60 as the center. Then, the conductor line 60 is loosely inserted into the through hole 52 of the ground layer, and the conductor line 60 is inserted.
Are formed in a pseudo coaxial line structure by the ground layer 50.
【００４０】信号線路３０は、その下方の上記グランド
層５０により、マイクロストリップ線路構造に形成して
いる。そして、信号線路３０の幅ｗとその厚さｔ、信号
線路３０とグランド層５０との間の距離ｈ、即ち上部絶
縁層１２ｂの厚さｈ１をそれぞれ大小に調整して、数１
の式から得られる信号線路３０の特性インピーダンスＺ
0 を設定しようとする信号線路３０の特性インピーダン
スの所定値の５０Ω等にマッチングさせている。The signal line 30 is formed in a microstrip line structure by the ground layer 50 below the signal line 30. Then, the width w and the thickness t of the signal line 30 and the distance h between the signal line 30 and the ground layer 50, that is, the thickness h1 of the upper insulating layer 12b are adjusted to be large and small, respectively.
The characteristic impedance Z of the signal line 30 obtained from the equation
The characteristic impedance of the signal line 30 to be set to 0 is matched with a predetermined value such as 50Ω.
【００４１】導体線路６０を遊挿したグランド層の透孔
５２の内径は、数２の式のＺ0 を所定値の５０Ω等とし
た場合に数２の式から得られるグランド層の透孔の内径
Ｄに比べて、小径に形成している。そして、グランド層
の透孔５２に遊挿した導体線路部分６０ａの特性インピ
ーダンスＺ1 を設定しようとする導体線路６０の特性イ
ンピーダンスの所定値の５０Ω等より低下させている。The inner diameter of the through-hole 52 in the ground layer into which the conductor line 60 is loosely inserted is defined by the through-hole in the ground layer obtained from the equation (2) when Z 0 in the equation (2) is set to a predetermined value of 50Ω or the like. The diameter is smaller than the inner diameter D. Then, the reduced than 50Ω such predetermined value of the characteristic impedance of the conductor line 60 to be set to the characteristic impedance Z 1 of the conductor line portion 60a which is loosely inserted into the through hole 52 of the ground layer.
【００４２】下部絶縁層１２ａは、その層厚を厚く形成
して、その下部絶縁層１２ａに上下に貫通させて備えた
導体線路部分６０ｂの線路長を延長している。そして、
その導体線路部分６０ｂの特性インピーダンスＺ2 を設
定しようとする導体線路６０の特性インピーダンスの所
定値の５０Ω等より上昇させている。The lower insulating layer 12a is formed to have a large thickness, and extends the line length of the conductor line portion 60b provided vertically through the lower insulating layer 12a. And
And the conductive line portions 60b is raised from 50Ω such predetermined value of the characteristic impedance of the conductor line 60 to be set to the characteristic impedance Z 2 of the.
【００４３】そして、グランド層の透孔５２に遊挿した
導体線路部分６０ａの特性インピーダンスＺ1 の低下を
下部絶縁層１２ａに上下に貫通させて備えた導体線路部
分６０ｂの特性インピーダンスＺ2 の上昇分により相殺
して、基板の上部絶縁層１２ｂと下部絶縁層１２ａとに
上下に連続して貫通させて備えた導体線路６０の特性イ
ンピーダンスＺ0 を設定しようとする導体線路６０の特
性インピーダンスの所定値の５０Ω等にマッチングさせ
ている。そして、信号線路３０とそれに連なる導体線路
６０とに高周波信号を伝送損失少なく伝えることができ
るようにしている。[0043] Then, the increase in characteristic impedance Z 2 of the conductor line portion 60b having been the reduction of the characteristic impedance Z 1 of the conductor line portion 60a which is loosely inserted into the through hole 52 of the ground layer is vertically penetrating the lower insulating layer 12a The predetermined characteristic impedance of the conductor line 60 for setting the characteristic impedance Z 0 of the conductor line 60 which is vertically penetrated continuously through the upper insulating layer 12b and the lower insulating layer 12a of the substrate to offset each other. The value is matched to 50Ω or the like. Then, a high-frequency signal can be transmitted to the signal line 30 and the conductor line 60 connected thereto with a small transmission loss.
【００４４】それと共に、基板１０を下部絶縁層１２ａ
と上部絶縁層１２ｂとの少数層で形成して、下部絶縁層
１２ａの層厚を厚く形成することにより、上部絶縁層１
２ｂと下部絶縁層１２ａとに上下に連続して貫通させて
備えた導体線路６０の共振周波数点を高周波領域側にシ
フトさせている。そして、導体線路６０に高周波信号を
伝えた場合に、導体線路６０が共振を起こして、導体線
路６０に高周波信号を伝えることが不可能となるのを防
ぐことができるようにしている。At the same time, the substrate 10 is placed on the lower insulating layer 12a.
And the upper insulating layer 12b are formed by a small number of layers, and the lower insulating layer 12a is formed to have a large layer thickness.
The resonance frequency point of the conductor line 60 provided by continuously penetrating vertically through the lower insulating layer 12b and the lower insulating layer 12a is shifted to the high frequency region side. Then, when a high-frequency signal is transmitted to the conductor line 60, it is possible to prevent the conductor line 60 from resonating and becoming unable to transmit the high-frequency signal to the conductor line 60.
【００４５】図１と図２に示した高周波デバイス実装用
基板は、以上のように構成している。The high frequency device mounting substrate shown in FIGS. 1 and 2 is configured as described above.
【００４６】次に、上述高周波デバイス実装用基板の具
体的な実験例を示す。この実験例では、上部絶縁層１２
ｂと下部絶縁層１２ａとを比誘電率εr が９．５のアル
ミナセラミックでそれぞれ形成して、上部絶縁層上面の
信号線路３０の幅ｗを０．３ｍｍとし、その信号線路３
０の厚さｔを０．０２０〜０．０２５ｍｍとした。そし
て、数１の式から得られる信号線路３０の特性インピー
ダンスＺ0 の値が５０Ωとなるように、数１の式を用い
て信号線路３０とその下方のグランド層５０との間の距
離ｈ、即ち上部絶縁層１２ｂの厚さｈ１を０．３２ｍｍ
とした。Next, specific experimental examples of the above-mentioned substrate for mounting a high-frequency device will be described. In this experimental example, the upper insulating layer 12
b and the lower insulating layer 12a are each formed of alumina ceramic having a relative dielectric constant ε r of 9.5, and the width w of the signal line 30 on the upper surface of the upper insulating layer is set to 0.3 mm.
The thickness t of 0 was set to 0.020 to 0.025 mm. Then, the distance h between the signal line 30 and the ground layer 50 below the signal line 30 is calculated using the expression 1 so that the value of the characteristic impedance Z 0 of the signal line 30 obtained from the expression 1 is 50Ω. That is, the thickness h1 of the upper insulating layer 12b is set to 0.32 mm.
And
【００４７】それと共に、メタライズが充填されたビア
からなる導体線路６０の外径ｄを０．１ｍｍとして、メ
タライズからなるグランド層の透孔５２の内径Ｄを０．
４７ｍｍとすると共に、下部絶縁層１２ａの厚さｈ２を
０．３２ｍｍとしたり、グランド層の透孔５２の内径Ｄ
を０．５２ｍｍとすると共に、下部絶縁層１２ａの厚さ
ｈ２を０．１９ｍｍとしたり、グランド層の透孔５２の
内径Ｄを０．６７ｍｍとすると共に、下部絶縁層１２ａ
の厚さｈ２を０．１２ｍｍとしたりした。At the same time, the outer diameter d of the conductor line 60 made of a via filled with metallization is set to 0.1 mm, and the inner diameter D of the through hole 52 of the ground layer made of metallized is set to 0.1 mm.
47 mm, the thickness h2 of the lower insulating layer 12a is set to 0.32 mm, and the inner diameter D of the through hole 52 of the ground layer is set to
Is set to 0.52 mm, the thickness h2 of the lower insulating layer 12a is set to 0.19 mm, the inner diameter D of the through hole 52 of the ground layer is set to 0.67 mm, and the lower insulating layer 12a
Was set to 0.12 mm.
【００４８】そして、ＴＤＲ法を用いて導体線路６０の
特性インピーダンスＺ0 を測定したところ、いずれも５
０Ωとなることが確認された。The characteristic impedance Z 0 of the conductor line 60 was measured using the TDR method.
It was confirmed to be 0Ω.
【００４９】また、ネットワークアナライザを用いて導
体線路６０のＳパラメータ値を測定したところ、上記の
ように、下部絶縁層１２ａの層厚を厚く形成した場合に
は、導体線路６０の共振周波数点が高周波領域側にシフ
トすることが確認された。具体的には、上部絶縁層１２
ｂの層厚ｈ１を０．３２ｍｍに形成すると共に、下部絶
縁層１２ａの層厚ｈ２を０．１２ｍｍに厚く形成した場
合には、導体線路６０の共振周波数点が１０ＧＨｚ付近
の高周波領域まで生じないことが確認された。また、上
部絶縁層１２ｂの層厚ｈ１を０．３２ｍｍに形成すると
共に、下部絶縁層１２ａの層厚ｈ２を０．３２ｍｍに厚
く形成した場合には、導体線路６０の共振周波数点が１
９ＧＨｚ付近の高周波領域まで生じないことが確認され
た。When the S-parameter value of the conductor line 60 was measured using a network analyzer, the resonance frequency point of the conductor line 60 was reduced when the lower insulating layer 12a was formed thick as described above. The shift to the high frequency region side was confirmed. Specifically, the upper insulating layer 12
In the case where the layer thickness h1 of b is formed to be 0.32 mm and the layer thickness h2 of the lower insulating layer 12a is formed to be thicker to 0.12 mm, the resonance frequency point of the conductor line 60 does not occur up to a high frequency region around 10 GHz. It was confirmed that. When the layer thickness h1 of the upper insulating layer 12b is formed to be 0.32 mm and the layer thickness h2 of the lower insulating layer 12a is formed to be 0.32 mm, the resonance frequency point of the conductor line 60 becomes 1
It was confirmed that no high frequency region around 9 GHz was generated.
【００５０】また、上記のようにして、グランド層の透
孔５２の内径Ｄを０．４７ｍｍに狭めて、下部絶縁層１
２ａの層厚ｈ２を０．３２ｍｍに厚く形成した場合に
は、基板１０に上下に貫通させて備えた複数本の導体線
路６０のピッチＨ、即ち導体線路６０下端に一連に接続
された下部絶縁層下面の外部接続端子２０のピッチＨ
を、一般に汎用されている１．２７ｍｍは勿論、０．６
５ｍｍまで狭めても、グランド層の透孔５２がそれに隣
合う同じグランド層の透孔５２の一部に重なり合うのを
防いで、導体線路６０の特性インピーダンスを５０Ωに
的確にマッチングさせることができることが確認され
た。Further, as described above, the inner diameter D of the through hole 52 of the ground layer is reduced to 0.47 mm, and the lower insulating layer 1 is formed.
In the case where the layer thickness h2 of 2a is formed to be as thick as 0.32 mm, the pitch H of the plurality of conductor lines 60 provided vertically penetrating through the substrate 10, that is, the lower insulation connected in series to the lower end of the conductor lines 60 Pitch H of external connection terminals 20 on the lower surface of the layer
Of course, the commonly used 1.27 mm, of course, 0.6
Even if it is narrowed to 5 mm, it is possible to prevent the through hole 52 of the ground layer from overlapping with a part of the through hole 52 of the same ground layer adjacent thereto, and to accurately match the characteristic impedance of the conductor line 60 to 50Ω. confirmed.
【００５１】図３は本発明の高周波デバイス実装用基板
の他の好適な実施例を示し、詳しくはその一部拡大正面
断面図である。以下に、この基板を説明する。FIG. 3 shows another preferred embodiment of the substrate for mounting a high-frequency device according to the present invention. Hereinafter, this substrate will be described.
【００５２】図の高周波デバイス実装用基板では、上部
絶縁層１２ｂと下部絶縁層１２ａとを合成樹脂で形成し
ている。In the high-frequency device mounting substrate shown in the figure, the upper insulating layer 12b and the lower insulating layer 12a are formed of a synthetic resin.
【００５３】グランド層５０は、上部絶縁層１２ｂ下面
又は下部絶縁層１２ａ上面に銅等の金属箔を被着させて
備えている。導体線路６０と交叉するグランド層５０部
分には、円形状の透孔５２を導体線路５０を中心に開口
している。The ground layer 50 includes a metal foil such as copper adhered to the lower surface of the upper insulating layer 12b or the upper surface of the lower insulating layer 12a. In the portion of the ground layer 50 that intersects with the conductor line 60, a circular through hole 52 is opened around the conductor line 50.
【００５４】信号線路３０は、上部絶縁層１２ｂの上面
に被着された銅等の金属箔を細帯状にエッチング加工等
することにより上部絶縁層１２ｂの上面に備えている。The signal line 30 is provided on the upper surface of the upper insulating layer 12b by etching a metal foil made of copper or the like on the upper surface of the upper insulating layer 12b into a narrow band.
【００５５】外部接続端子２０は、下部絶縁層１２ａの
下面に被着された銅等の金属箔をエッチング加工等する
ことにより下部絶縁層１２ａの下面に備えている。外部
接続端子２０表面には、はんだバンプ２２を半球状に形
成している。The external connection terminal 20 is provided on the lower surface of the lower insulating layer 12a by etching a metal foil such as copper adhered to the lower surface of the lower insulating layer 12a. On the surface of the external connection terminal 20, a solder bump 22 is formed in a hemispherical shape.
【００５６】導体線路６０は、円筒状をしていて、上部
絶縁層１２ｂと下部絶縁層１２ａとにスルーホール６２
を上下に連続して貫通させて開口して、そのスルーホー
ル６２内周面に導体めっき層６４を無電解めっき法等に
より信号線路３０と所定の外部接続端子２０とにそれぞ
れ連続させて備えることにより形成している。The conductor line 60 has a cylindrical shape and has through holes 62 formed in the upper insulating layer 12b and the lower insulating layer 12a.
And a conductor plating layer 64 is provided on the inner peripheral surface of the through hole 62 so as to be continuous with the signal line 30 and the predetermined external connection terminal 20 by an electroless plating method or the like. It is formed by.
【００５７】グランド線路５４は、円筒状をしていて、
下部絶縁層１２ａにスルーホール５６を上下に貫通させ
て開口して、そのスルーホール５６内周面に導体めっき
層５８を無電解めっき法等によりグランド層５０と所定
の外部接続端子２０とにそれぞれ連続させて備えること
により形成している。The ground line 54 has a cylindrical shape.
A through-hole 56 is vertically opened through the lower insulating layer 12a, and an opening is formed. A conductor plating layer 58 is formed on the inner peripheral surface of the through-hole 56 with the ground layer 50 and the predetermined external connection terminal 20 by an electroless plating method or the like. It is formed by being provided continuously.
【００５８】その他は、前述図１と図２に示した高周波
デバイス実装用基板と同様に構成していて、その作用
も、前述図１と図２に示した高周波デバイス実装用基板
と同様である。In other respects, the configuration is the same as that of the high-frequency device mounting substrate shown in FIGS. 1 and 2, and the operation is the same as that of the high-frequency device mounting substrate shown in FIGS. 1 and 2. .
【００５９】[0059]
【発明の効果】以上説明したように、本発明の高周波デ
バイス実装用基板によれば、基板の上部絶縁層と下部絶
縁層とに連続して貫通させて備えた擬似同軸線路構造を
した導体線路の特性インピーダンスを設定しようとする
導体線路の特性インピーダンスの所定値のＺ0 にマッチ
ングさせることができる。As described above, according to the high frequency device mounting substrate of the present invention, the conductor line having the pseudo coaxial line structure provided continuously through the upper insulating layer and the lower insulating layer of the substrate. Can be matched to a predetermined value Z 0 of the characteristic impedance of the conductor line whose characteristic impedance is to be set.
【００６０】それと共に、グランド層の透孔の内径を小
径に形成したため、基板の上部絶縁層と下部絶縁層とに
連続して貫通させて備えた複数本の導体線路のピッチを
狭めた場合に、グランド層の透孔がそれに隣合う同じグ
ランド層の透孔の一部に重なり合うのを防ぐことができ
る。そして、基板の上部絶縁層と下部絶縁層とに連続し
て貫通させて備えた複数本の導体線路のピッチを狭め
て、それらの導体線路下端にそれぞれ一連に接続された
外部接続端子を下部絶縁層の下面に小ピッチで並べて備
えることができる。At the same time, since the inner diameter of the through hole in the ground layer is formed to be small, when the pitch of a plurality of conductor lines provided continuously through the upper insulating layer and the lower insulating layer of the substrate is reduced. In addition, it is possible to prevent the through hole of the ground layer from overlapping with a part of the through hole of the same ground layer adjacent thereto. Then, the pitch of the plurality of conductor lines provided continuously penetrating through the upper insulating layer and the lower insulating layer of the substrate is narrowed, and the external connection terminals connected in series to the lower ends of the conductor lines, respectively, are connected to the lower insulating layer. It can be provided side by side at a small pitch on the lower surface of the layer.
【００６１】さらに、基板の上部絶縁層と下部絶縁層と
に連続して貫通させて備えた導体線路の共振周波数点を
高周波領域側にシフトさせることができる。そして、基
板の上部絶縁層と下部絶縁層とに連続して貫通させて備
えた導体線路に高周波信号を伝えた場合に、導体線路が
共振を起こして、導体線路に高周波信号を伝えることが
不可能となるのを防ぐことができる。Further, it is possible to shift the resonance frequency point of the conductor line provided continuously through the upper insulating layer and the lower insulating layer of the substrate to the high frequency region side. When a high-frequency signal is transmitted to a conductor line provided continuously penetrating the upper insulating layer and the lower insulating layer of the substrate, the conductor line resonates, and it is impossible to transmit the high-frequency signal to the conductor line. It can be prevented from becoming possible.
【図１】本発明の高周波デバイス実装用基板の一部拡大
正面断面図である。FIG. 1 is a partially enlarged front sectional view of a high-frequency device mounting substrate according to the present invention.
【図２】図１のＡ―Ａ断面図である。FIG. 2 is a sectional view taken along line AA of FIG.
【図３】本発明の高周波デバイス実装用基板の一部拡大
正面断面図である。FIG. 3 is a partially enlarged front sectional view of the high-frequency device mounting substrate of the present invention.
【図４】ＢＧＡパッケージの本体を構成する高周波デバ
イス実装用基板の一部拡大正面断面図である。FIG. 4 is a partially enlarged front cross-sectional view of a high-frequency device mounting substrate constituting a main body of a BGA package;
【図５】図４のＢ―Ｂ断面図である。FIG. 5 is a sectional view taken along line BB of FIG. 4;
【図６】数１の式の参考図である。FIG. 6 is a reference diagram of the equation (1).
【図７】ＢＧＡパッケージの本体を構成する高周波デバ
イス実装用基板の一部拡大正面断面図である。FIG. 7 is a partially enlarged front cross-sectional view of a high-frequency device mounting substrate constituting a main body of a BGA package;
【図８】高周波デバイス実装用基板の一部拡大断面図で
ある。FIG. 8 is a partially enlarged sectional view of a high-frequency device mounting substrate.
１０ 基板 １２ 絶縁層 １２ａ 下部絶縁層 １２ｂ 上部絶縁層 ２０ 外部接続端子 ２２ はんだバンプ ３０ 信号線路 ５０ グランド層 ５２ 透孔 ５４ グランド線路 ５６ スルーホール ５８ 導体めっき層 ６０ 導体線路 ６２ スルーホール ６４ 導体めっき層 DESCRIPTION OF SYMBOLS 10 Substrate 12 Insulating layer 12a Lower insulating layer 12b Upper insulating layer 20 External connection terminal 22 Solder bump 30 Signal line 50 Ground layer 52 Through hole 54 Ground line 56 Through hole 58 Conductor plating layer 60 Conductor line 62 Through hole 64 Conductor plating layer
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H05K 1/02 H05K 3/46 H01L 23/12 301 H01P 5/08 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H05K 1/02 H05K 3/46 H01L 23/12 301 H01P 5/08
Claims (4)
を介して積層して形成した基板の上部絶縁層の上面に信
号線路を備えて、該信号線路をその下方の前記グランド
層によりマイクロストリップ線路構造に形成すると共
に、前記基板に導体線路を前記上部絶縁層と下部絶縁層
とを連続して貫通させて備えて、その導体線路の上下端
を前記信号線路と前記下部絶縁層の下面に備えた外部接
続端子にそれぞれ接続し、さらに、前記導体線路と交叉
する前記グランド層部分にグランド層の非形成部分を導
体線路を中心に円形状に設けて、前記導体線路を前記グ
ランド層により擬似同軸線路構造に形成してなる高周波
デバイス実装用基板であって、前記グランド層の円形状
の非形成部分の内径を、その非形成部分を貫通する前記
導体線路部分の特性インピーダンスが所定値よりも低く
なるように小径に形成して、該導体線路部分の特性イン
ピーダンスを所定値よりも低下させると共に、前記下部
絶縁層の層厚を、その下部絶縁層に貫通させて備えた前
記導体線路部分の特性インピーダンスが所定値よりも高
くなるように厚く形成して、該導体線路部分の特性イン
ピーダンスを所定値よりも上昇させ、前記非形成部分を
貫通する導体線路部分の特性インピーダンスの低下分を
前記下部絶縁層に貫通させて備えた導体線路部分の特性
インピーダンスの上昇分により相殺して、前記導体線路
の特性インピーダンスを所定値にマッチングさせたこと
を特徴とする高周波デバイス実装用基板。1. A signal line is provided on an upper surface of an upper insulating layer of a substrate formed by laminating an upper insulating layer on a lower insulating layer via a ground layer, and the signal line is formed by the ground layer below the signal line. The substrate is formed in a stripline structure, and the substrate is provided with a conductor line continuously penetrating the upper insulating layer and the lower insulating layer, and upper and lower ends of the conductor line are formed on the lower surface of the signal line and the lower insulating layer. their respective connect to an external connection terminal provided in further, provided in a circular shape to the non-formation portion of the ground layer around the conductor <br/> body line on the ground layer portion intersecting with the conductor line, A high-frequency device mounting substrate formed by forming the conductor line into a pseudo-coaxial line structure using the ground layer, wherein the ground layer has a circular shape.
The inner diameter of the non-formation portion of the characteristic impedance of the conductor line portion of the non-formation portion through is formed in the small diameter so as to be lower than the predetermined value, than a predetermined value the characteristic impedance of the conductor line sections Before lowering, the thickness of the lower insulating layer is provided so as to penetrate the lower insulating layer.
Characteristic impedance of Kishirube body line portion is formed thicker in the high <br/> Kunar so than a predetermined value, the characteristic impedance of the conductor line portion is higher than a predetermined value, the non-forming portion
And offset by increase in the characteristic impedance of the conductor line portion of the reduced amount having been passed through the lower insulating layer of the characteristic impedance of the conductor line portion for penetrating, that is matched to the characteristic impedance of the conductor line to a predetermined value A substrate for mounting a high-frequency device, characterized in that:
成した請求項１記載の高周波デバイス実装用基板。2. A high frequency device mounting substrate according to claim 1, wherein the formation of the solder bumps on the surface of the external connection terminal.
形成した請求項１又は２記載の高周波デバイス実装用基
板。3. The thickness of the lower insulating layer is set to 0.12 mm or more .
High frequency device mounting substrate according to claim 1 or 2, wherein the form shape.
からなり、グランド層がメタライズからなり、導体線路
がメタライズが充填されたビアからなる請求項１、２又
は３記載の高周波デバイス実装用基板。4. The high-frequency device mounting substrate according to claim 1, wherein the upper insulating layer and the lower insulating layer are made of ceramic, the ground layer is made of metallized metal, and the conductor line is made of a via filled with metallized metal. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23943494A JP3313250B2 (en) | 1994-09-06 | 1994-09-06 | Substrate for mounting high frequency devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23943494A JP3313250B2 (en) | 1994-09-06 | 1994-09-06 | Substrate for mounting high frequency devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0878797A JPH0878797A (en) | 1996-03-22 |
| JP3313250B2 true JP3313250B2 (en) | 2002-08-12 |
Family
ID=17044723
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23943494A Expired - Fee Related JP3313250B2 (en) | 1994-09-06 | 1994-09-06 | Substrate for mounting high frequency devices |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3313250B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4623850B2 (en) * | 2001-03-27 | 2011-02-02 | 京セラ株式会社 | High frequency semiconductor element storage package and its mounting structure |
| JP5318360B2 (en) * | 2007-03-30 | 2013-10-16 | 京セラ株式会社 | Wiring board and electronic device |
| JP5155582B2 (en) * | 2007-03-30 | 2013-03-06 | 京セラ株式会社 | Wiring board and electronic device |
| JP5971000B2 (en) | 2012-07-20 | 2016-08-17 | 富士通株式会社 | WIRING BOARD, WIRING BOARD MANUFACTURING METHOD, ELECTRONIC DEVICE AND ELECTRONIC DEVICE MANUFACTURING METHOD |
| JP6866789B2 (en) | 2017-07-11 | 2021-04-28 | 富士通株式会社 | Electronic devices and methods for manufacturing electronic devices |
-
1994
- 1994-09-06 JP JP23943494A patent/JP3313250B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0878797A (en) | 1996-03-22 |
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