JP3263956B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP3263956B2 JP3263956B2 JP22583391A JP22583391A JP3263956B2 JP 3263956 B2 JP3263956 B2 JP 3263956B2 JP 22583391 A JP22583391 A JP 22583391A JP 22583391 A JP22583391 A JP 22583391A JP 3263956 B2 JP3263956 B2 JP 3263956B2
- Authority
- JP
- Japan
- Prior art keywords
- temperature
- manufacturing
- semiconductor device
- heat treatment
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Formation Of Insulating Films (AREA)
- Junction Field-Effect Transistors (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、イオン注入した半導体
基板を熱処理（アニールと称す）する半導体装置の製造
方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device in which an ion-implanted semiconductor substrate is heat-treated (called annealing).
【０００２】[0002]
【従来の技術】従来の半導体装置の製造方法におけるア
ニール温度は１ステップのみで行なわれている。2. Description of the Related Art In a conventional method of manufacturing a semiconductor device, an annealing temperature is performed in only one step.
【０００３】[0003]
【発明が解決しようとする課題】従来の方法では、表面
に残留ダメージが存在し、これがアニール中で特異な振
舞いをするため、表面に変成層を形成しやすく、また不
純物の活性化が安定しないため、デバイスの特性が劣化
し、歩留りも安定しないという課題がある。In THE INVENTION Problems to be Solved by the conventional method, there is residual damage to the surface, which is to the peculiar behavior in annealing, easily formed metamorphic layer on the surface, also not
Since the activation of the pure substance is not stable, there is a problem that the characteristics of the device are deteriorated and the yield is not stable.
【０００４】本発明は上記課題を解決するもので、残留
ダメージを消失させ、変成層の形成を防ぎ、歩留り向
上、ばらつきを激減させた半導体装置の製造方法を提供
することを目的とする。An object of the present invention is to solve the above-mentioned problems, and an object of the present invention is to provide a method of manufacturing a semiconductor device in which residual damage is eliminated, formation of a metamorphic layer is prevented, yield is improved, and variation is drastically reduced.
【０００５】[0005]
【課題を解決するための手段】上記目的を達成するため
に本発明は、化合物半導体基板の一表面にイオン注入し
た後、前記表面を表面保護膜でキャップして、次いで前
記基板を熱処理して一導電型拡散層を形成する工程とを
備えた半導体装置の製造方法において、前記熱処理が２
または３ステップで行われており、第１番目のステップ
温度が第２番目のステップ温度より低い条件で処理した
ものであって、第１番目のステップ温度で熱処理するこ
とにより、第２番目のステップ温度での熱処理中に形成
される極低濃度の他導電型キャリアからなる変成層を回
避することを特徴とする。Means for Solving the Problems To accomplish the above object, after ion implantation into a surface of a compound semiconductor substrate, the surface is capped with a surface protective film, then the substrate is thermally treated Forming a one-conductivity-type diffusion layer by heat treatment.
Or, the process is performed in three steps, and the first step temperature is lower than the second step temperature .
Heat treatment at the first step temperature.
Formed during heat treatment at the second step temperature
The metamorphic layer consisting of the very low-concentration carriers of other conductivity type
It is characterized by avoiding .
【０００６】[0006]
【作用】この構成によって、第２番目のステップ温度の
アニール中に形成される変成層を回避し、安定に注入イ
オンのみを活性化でき、デバイスの特性や、歩留りを向
上させる。With this configuration, a metamorphic layer formed during the annealing at the second step temperature can be avoided, only the implanted ions can be activated stably, and the characteristics of the device and the yield can be improved.
【０００７】[0007]
【実施例】本発明の一実施例としてＧａＡｓ基板にＳｉ
注入した後、この基板をプラズマシリコン窒化膜でキャ
ップアニールする場合について説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As one embodiment of the present invention, a GaAs substrate is made of Si.
A case in which the substrate is cap-annealed with a plasma silicon nitride film after the implantation will be described.
【０００８】図１は、本発明の一実施例に用いたアニー
ルにおける温度プロファイルであり、第１ステップの温
度は５５０℃で、第２ステップの温度は８２０℃で、第
３ステップの温度は３００℃である。アニール工程とし
て３ステップを採用し、第１ステップの温度でプラズマ
シリコン窒化膜を形成する際に生じたプラズマダメージ
を回復し、第２ステップの温度で注入イオンを活性化さ
せ、第３ステップの温度で結晶を安定化させることを目
的としている。[0008] Figure 1 is a temperature profile in the annealing used in an embodiment of the present invention, the first step temperature
The temperature is 550 ° C and the temperature of the second step is 820 ° C.
The temperature for the three steps is 300 ° C. It employs three steps as annealing process, at temperature of the first steps to recover the plasma damage caused in forming the plasma silicon nitride film, to activate the implanted ions at a temperature of the second step, a third step It is intended to stabilize the crystals temperature of up.
【０００９】図２は第２ステップの温度を８２０℃、そ
の時間を１５分とし、第１ステップの時間を１０分とし
て、第１ステップの温度を変えた場合の活性化率の変化
の様子を示す。図３は、図１における第１ステップの温
度を５５０℃とし、第１ステップの処理時間を変えた場
合の活性率の変化を示す図である。図２，図３から５５
０〜６５０℃で１０〜１５分の間で最も活性化が高くな
っておりばらつきも小さいことがわかる。従来の１ステ
ップアニールによる活性化率は２０〜６０％で、しかも
ばらつきもあり、この第１ステップの温度で処理するこ
とにより活性化率の向上と安定化を図ることができる。[0009] Figure 2 is 820 ° C. The temperature of the second step, the time to minutes 15, the time of the first step as 10 minutes, the change of the activation rate when changing the temperature of the first steps Show the situation. 3, the temperature <br/> of the first steps in FIG. 1 and 550 ° C., a diagram illustrating a change in the activity rate when changing the processing time of the first step. 2 to 3 to 55
It can be seen that the activation is highest at 0 to 650 ° C. for 10 to 15 minutes and the variation is small. The activation rate by the conventional one-step annealing at 20% to 60%, yet there is also variation, it is possible to improve and stabilize the activation rate by treatment with temperature of the first step.
【００１０】図４は本発明の半導体装置の製造方法にお
けるキャリアプロファイルを従来例と比較して示した図
である。この図より、本発明の方法により従来問題とな
っていたＧａＡｓ表面のキャリア濃度の減少と深さ２０
００Å付近に存在するプラズマダメージによる極低濃度
のＰ型キャリアからなる変成層が回避でき、キャリアプ
ロファイルの急峻性も向上していることがわかる。FIG. 4 is a diagram showing a carrier profile in a method of manufacturing a semiconductor device according to the present invention in comparison with a conventional example. From this figure, it can be seen that the carrier concentration on the GaAs surface and the depth 20
It can be seen that a metamorphic layer composed of extremely low-concentration P-type carriers due to plasma damage existing near 00 ° can be avoided, and the steepness of the carrier profile is also improved.
【００１１】図５に本発明により製作した電界効果トラ
ンジスタ（ＦＥＴと略す）の特性分布を示す。ＦＥＴの
相互コンダクタンスｇｍが３０％以上向上し、ばらつき
も半分以下となっている。FIG. 5 shows a characteristic distribution of a field effect transistor (abbreviated as FET) manufactured according to the present invention. The mutual conductance gm of the FET is improved by 30% or more, and the variation is reduced to half or less.
【００１２】本発明の半導体の製造方法における熱処理
方法は、半導体基板にイオン注入を行った場合のダメー
ジ回復、また半導体基板にプラズマ処理した場合のダメ
ージ回復にも用いることができる。The heat treatment method in the method of manufacturing a semiconductor according to the present invention can be used for recovery from damage when ion implantation is performed on a semiconductor substrate, and recovery from damage when plasma processing is performed on a semiconductor substrate.
【００１３】また半導体基板に異種イオンを多重注入し
た場合の熱処理にも用いることができ、この場合は拡散
係数の大きいイオンの活性温度で熱処理し、続いてその
次に拡散係数の大きいイオンの活性化温度で、順次熱処
理するという構成をとればよい、例えばＧａＡｓにＺｎ
注入とＳｉ注入を行ないアニールする場合は第２ステッ
プにＺｎアニール温度を、第２ステップにＳｉアニール
温度を設定すればよい。The present invention can also be used for heat treatment in the case where multiple ions of different types of ions are implanted into a semiconductor substrate. In this case, heat treatment is performed at the activation temperature of ions having the next largest diffusion coefficient, The heat treatment may be performed sequentially at the crystallization temperature. For example, Zn may be added to GaAs.
When annealing is performed by performing implantation and Si implantation, the Zn annealing temperature may be set in the second step, and the Si annealing temperature may be set in the second step.
【００１４】[0014]
【発明の効果】以上の実施例から明らかなように本発明
は、連続して２または３ステップの温度で熱処理する工
程とを備えた半導体装置の製造方法において、第１番目
のステップ温度が第２番目のステップ温度より低い条件
で処理したものであって、第１番目のステップ温度で熱
処理することにより、第２番目のステップ温度での熱処
理中に形成される極低濃度の他導電型キャリアからなる
変成層を回避する構成によるので、安定なキャリアプロ
ファイルが実現でき、ＦＥＴの特性も３０％以上向上
し、ばらつきも従来の半分以下に減少できる半導体装置
の製造方法を提供できる。As is apparent from the above embodiments, the present invention relates to a method for manufacturing a semiconductor device comprising a step of continuously performing heat treatment at two or three steps of temperature. Condition lower than the second step temperature
And heat at the first step temperature
The heat treatment at the second step temperature
Consists of extremely low-concentration carriers of other conductivity type formed during processing
Because of the configuration that avoids the metamorphic layer, a method of manufacturing a semiconductor device can be provided in which a stable carrier profile can be realized, the characteristics of the FET can be improved by 30% or more, and the variation can be reduced to half or less of the conventional case.
【図１】本発明の一実施例の半導体装置の製造方法にお
ける熱処理工程の温度プロファイルを示す図FIG. 1 is a diagram showing a temperature profile of a heat treatment step in a method of manufacturing a semiconductor device according to one embodiment of the present invention.
【図２】図１における第１ステップの温度に対する活性
化率の変化を示す図FIG. 2 is a diagram showing a change in an activation rate with respect to a temperature in a first step in FIG. 1;
【図３】図１における第１ステップの処理時間に対する
活性化率の変化を示す図FIG. 3 is a diagram showing a change in an activation rate with respect to a processing time of a first step in FIG. 1;
【図４】図１の本発明の半導体装置の製造方法により得
られた半導体基板における表面からの深さとキャリア濃
度の関係を従来例と比較して示した図FIG. 4 is a diagram showing the relationship between the depth from the surface and the carrier concentration in a semiconductor substrate obtained by the method for manufacturing a semiconductor device of the present invention in FIG. 1 in comparison with a conventional example.
【図５】図１の本発明の半導体装置の製造方法により得
られたＦＥＴの相互コンダクタンスに対するそのＦＥＴ
の数の分布を示す図FIG. 5 shows the relationship between the transconductance of the FET obtained by the method for manufacturing a semiconductor device of FIG.
Diagram showing the distribution of the number of
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭64−37010（ＪＰ，Ａ) 特開 昭49−12776（ＪＰ，Ａ) 特開 昭59−191329（ＪＰ，Ａ) 特開 平３−68134（ＪＰ，Ａ) 特開 昭60−119718（ＪＰ，Ａ) 特開 昭48−32478（ＪＰ，Ａ) 特開 平２−237023（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/26 - 21/268 H01L 21/322 - 21/326 H01L 21/312 - 21/32 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-64-37010 (JP, A) JP-A-49-12776 (JP, A) JP-A-59-191329 (JP, A) 68134 (JP, A) JP-A-60-119718 (JP, A) JP-A-48-32478 (JP, A) JP-A-2-237023 (JP, A) (58) Fields investigated (Int. 7 , DB name) H01L 21/26-21/268 H01L 21/322-21/326 H01L 21/312-21/32
Claims (4)
した後、前記表面を表面保護膜でキャップして、次いで
前記基板を熱処理して一導電型拡散層を形成する工程と
を備えた半導体装置の製造方法において、前記熱処理が２ステップで行われており、 第１番目のス
テップ温度が第２番目のステップ温度より低い条件で処
理したものであって、第１番目のステップ温度で熱処理
することにより、第２番目のステップ温度での熱処理中
に形成される極低濃度の他導電型キャリアからなる変成
層を回避することを特徴とする半導体装置の製造方法。[Claim 1] After ion implantation into a surface of a compound semiconductor substrate, and a cap the surface with a surface protective film, followed by a step of forming a first conductivity type diffusion layer of the substrate was thermally treated semiconductor In the device manufacturing method, the heat treatment is performed in two steps, and the heat treatment is performed under the condition that the first step temperature is lower than the second step temperature.
Heat treatment at the first step temperature
During the heat treatment at the second step temperature
Composed of ultra-low concentration of other conductive type carriers
A method for manufacturing a semiconductor device, comprising: avoiding a layer .
おいて、前記第２番目の熱処理ステップの後に第３番目
の熱処理ステップが追加されており、該第３番目のステ
ップ温度が前記第１番目のステップ温度より低い条件で
処理したものであることを特徴とする半導体装置の製造
方法。2. The method of manufacturing a semiconductor device according to claim 1, wherein a third heat treatment step is performed after said second heat treatment step.
The third heat treatment step has been added.
Under the condition that the tap temperature is lower than the first step temperature.
A method for manufacturing a semiconductor device, wherein the semiconductor device is processed.
体装置の製造方法において、第１番目のステップ温度が
５５０℃から６５０℃の範囲にあることを特徴とする半
導体装置の製造方法。3. A semiconductor according to claim 1, wherein
In the body device manufacturing method, the first step temperature is
A method for manufacturing a semiconductor device, wherein the temperature is in a range of 550 ° C. to 650 ° C.
記載の半導体装置の製造方法において、表面保護膜がプ
ラズマシリコン窒化膜であることを特徴とする半導体装
置の製造方法4. The method according to claim 1, 2 or 3,
In the method for manufacturing a semiconductor device according to
A method of manufacturing a semiconductor device characterized by being a plasma silicon nitride film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22583391A JP3263956B2 (en) | 1991-09-05 | 1991-09-05 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22583391A JP3263956B2 (en) | 1991-09-05 | 1991-09-05 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0567581A JPH0567581A (en) | 1993-03-19 |
| JP3263956B2 true JP3263956B2 (en) | 2002-03-11 |
Family
ID=16835529
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22583391A Expired - Fee Related JP3263956B2 (en) | 1991-09-05 | 1991-09-05 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3263956B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4577462B2 (en) * | 1999-11-05 | 2010-11-10 | 住友電気工業株式会社 | Semiconductor heat treatment method |
-
1991
- 1991-09-05 JP JP22583391A patent/JP3263956B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0567581A (en) | 1993-03-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH036027A (en) | Method of forming structure shaped of polysilicon and selectively removing structure | |
| US5851888A (en) | Controlled oxide growth and highly selective etchback technique for forming ultra-thin oxide | |
| JP3263956B2 (en) | Method for manufacturing semiconductor device | |
| JPH04215424A (en) | Metal semiconductor ohmic contact point type formation processing method | |
| JPH10199829A (en) | Manufacture of semiconductor device | |
| JPH03209834A (en) | Manufacture of mis semiconductor device | |
| JPS6390175A (en) | Manufacture of compound semiconductor field effect transistor | |
| JPS63236310A (en) | Semiconductor device and manufacture thereof | |
| JP3261444B2 (en) | Manufacturing method of semiconductor thin film | |
| JP3035941B2 (en) | Method for manufacturing group III-V compound semiconductor device | |
| KR100256246B1 (en) | Method of forming gate electrode in semiconductor device | |
| JP2528660B2 (en) | Method for forming compound semiconductor conductive layer | |
| JPS61248476A (en) | Manufacture of semiconductor device | |
| JPH0380542A (en) | Semiconductor integrated circuit device | |
| JPH0730114A (en) | Manufacture of mos transistor | |
| JPH01220439A (en) | Manufacture of semiconductor device | |
| JPH06326316A (en) | Manufacture of semiconductor device | |
| JPH0697424A (en) | Manufacture of semiconductor element | |
| JPH0458524A (en) | Manufacture of semiconductor device | |
| JPS58100445A (en) | Manufacture of semiconductor device | |
| JPH06224380A (en) | Manufacture of semiconductor device | |
| JPH02304934A (en) | Manufacture of mis type transistor | |
| JPH08124939A (en) | Fabrication of semiconductor device | |
| JPS63173320A (en) | Manufacture of compound semiconductor device | |
| JPH023297B2 (en) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20071228 Year of fee payment: 6 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081228 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091228 Year of fee payment: 8 |
|
| LAPS | Cancellation because of no payment of annual fees |