JPH03209834A - Manufacture of mis semiconductor device - Google Patents
Manufacture of mis semiconductor deviceInfo
- Publication number
- JPH03209834A JPH03209834A JP479590A JP479590A JPH03209834A JP H03209834 A JPH03209834 A JP H03209834A JP 479590 A JP479590 A JP 479590A JP 479590 A JP479590 A JP 479590A JP H03209834 A JPH03209834 A JP H03209834A
- Authority
- JP
- Japan
- Prior art keywords
- film
- polycrystalline silicon
- titanium
- titanium silicide
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 44
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 43
- 229910021341 titanium silicide Inorganic materials 0.000 claims abstract description 33
- 239000010936 titanium Substances 0.000 claims abstract description 24
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 24
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims abstract description 22
- 239000012535 impurity Substances 0.000 claims abstract description 21
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 17
- 239000011574 phosphorus Substances 0.000 claims abstract description 17
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 15
- 150000002500 ions Chemical class 0.000 claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims abstract description 7
- -1 argon ions Chemical class 0.000 claims description 11
- 229910052796 boron Inorganic materials 0.000 claims description 7
- XKRFYHLGVUSROY-UHFFFAOYSA-N argon Substances [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 5
- 229910052786 argon Inorganic materials 0.000 claims description 5
- 150000003609 titanium compounds Chemical class 0.000 claims description 4
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- 238000000206 photolithography Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 16
- 229910052710 silicon Inorganic materials 0.000 abstract description 16
- 239000010703 silicon Substances 0.000 abstract description 16
- 238000010438 heat treatment Methods 0.000 abstract description 3
- 150000001875 compounds Chemical class 0.000 abstract 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000000779 smoke Substances 0.000 description 3
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- XHXFXVLFKHQFAL-UHFFFAOYSA-N phosphoryl trichloride Chemical compound ClP(Cl)(Cl)=O XHXFXVLFKHQFAL-UHFFFAOYSA-N 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- QGZKDVFQNNGYKY-UHFFFAOYSA-N ammonia Natural products N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 150000003608 titanium Chemical class 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、シリコン表面にチタンシリサイドを選択的に
形成した半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device in which titanium silicide is selectively formed on a silicon surface.
［従来の技術］
従来のシリコンの表面にチタンシリサイドを選択的に形
成した構造を有する半導体装置の製造方法において、特
にゲート電極として多結晶シリコンを用い該ゲート電極
の多結晶シリコンの表面にチタンシリサイドを形成する
半導体装置の製造方法においては、多結晶シリコンに導
電性をもたす力めに多結晶シリコン中に不純物として燐
を拡散していたがこの’ｔ１４？Ｍ度が高くなって多結
晶シリコン中に過飽和になってくるとチタンとシリコン
の反応が抑制されシソサイドになり難くなるため、従来
技術の半導体装置の製造方法では多結晶シリコン中に拡
散する燐の濃度を低くしていた。[Prior Art] In a conventional method for manufacturing a semiconductor device having a structure in which titanium silicide is selectively formed on the surface of silicon, in particular, polycrystalline silicon is used as a gate electrode and titanium silicide is formed on the surface of the polycrystalline silicon of the gate electrode. In the manufacturing method of semiconductor devices that form semiconductor devices, phosphorus is diffused as an impurity into polycrystalline silicon in order to make it conductive, but this 't14? When the M degree increases and becomes supersaturated in polycrystalline silicon, the reaction between titanium and silicon is suppressed and formation of sisoside becomes difficult. The concentration was kept low.
［発明が解決しようとする課題及び目的］しかしながら
前述の従来技術の製造方法を用いて相補型のＭＩＳ型ト
ランジスタを形成すると、ゲート電極としての多結晶シ
リコン中の燐？Ｍ度が低いため、Ｐチャンネル側にソー
ス・ドレインにする不純物拡散層を形成するときに注入
されるＰ型の不純物であるホウ素がゲート電極中にも注
入されるためＮ型の不純物の烟が発生するキャリアとし
ての電子数が減少しゲート電極の抵抗が高くなったり、
トランジスタのスイッチング特性であるしきい値電圧が
変化する問題を有していた。またゲート電極中のキャリ
アの濃度が低くいため多結晶シリコン表面に形成したチ
タンシリサイドと多結晶シリコンの接触抵抗も高くなり
半導体装置の動作不良の原因になることや半導体装置の
高速動作をできなくする問題点を有していた。[Problems and Objects to be Solved by the Invention] However, when a complementary MIS transistor is formed using the manufacturing method of the prior art described above, phosphorus in polycrystalline silicon as a gate electrode is removed. Due to the low M degree, boron, which is a P-type impurity that is injected when forming an impurity diffusion layer for the source and drain on the P-channel side, is also injected into the gate electrode, which causes smoke from N-type impurities. The number of electrons generated as carriers decreases, and the resistance of the gate electrode increases,
There was a problem in that the threshold voltage, which is the switching characteristic of the transistor, changed. Furthermore, since the concentration of carriers in the gate electrode is low, the contact resistance between the titanium silicide formed on the polycrystalline silicon surface and the polycrystalline silicon also increases, causing malfunction of the semiconductor device and making it impossible for the semiconductor device to operate at high speed. It had some problems.
そこで、本発明はこのような課題を解決しようとするも
ので゛、その目的とするところは、ゲート電極としての
多結晶シリコン表面にチタンシリサイドを自己整合的に
形成し同時にゲート電極の配線抵抗の増加やトランジス
タのしきい値電圧の変化、チタンシリサイドと多結晶シ
リコンの接触抵抗の増加を抑えた半導体装置の製造方法
を提供するところにある。Therefore, the present invention aims to solve these problems.The purpose of the present invention is to form titanium silicide in a self-aligned manner on the surface of polycrystalline silicon as a gate electrode, and at the same time to reduce the wiring resistance of the gate electrode. It is an object of the present invention to provide a method for manufacturing a semiconductor device in which increase in the threshold voltage of a transistor and increase in contact resistance between titanium silicide and polycrystalline silicon are suppressed.
［課題を解決するための手段］
本発明の半導体装置の製造方法は、露出した多結晶シリ
コン表面にチタンシリサイドを自己整合的に形成する半
導体装置の製造方法において、半導体基板上にゲート絶
縁膜を介して多結晶シリコン膜を形成する工程と、該多
結晶シリコン中に燐を拡散する工程と、烟を拡散した多
結晶シリコン膜に不純物イオンをイオン注入することに
より該多結晶シリコン膜の表面近傍をアモルファス化す
る工程と、該多結晶シリコン膜をフォトリソ技術とエツ
チング技術によりゲート電極および配線に加工する工程
と、該ゲート電極および配線を形成した半導体基板上に
絶縁膜を堆積し、前記半導体基板全面を異方性エツチン
グする事により前記ゲート電極側面に絶縁膜のサイドウ
オールを形成する工程と、該サイドウオールを形成した
半導体基板全面にチタン金属膜を形成する工程と、該チ
タン金属膜を形成した半導体基板を加熱処理することに
より露出したシリコン表面および前記ゲート電極上のチ
タンをチタンシリサイドに変化させる工程と、該チタン
シリサイド以外のチタン化合物及びチタン金属を選択的
に除去する工程からなることを特徴とする。[Means for Solving the Problems] A method for manufacturing a semiconductor device of the present invention includes forming a gate insulating film on a semiconductor substrate in a method for manufacturing a semiconductor device in which titanium silicide is formed on an exposed polycrystalline silicon surface in a self-aligned manner. a process of forming a polycrystalline silicon film through the polycrystalline silicon film, a process of diffusing phosphorus into the polycrystalline silicon, and a process of ion-implanting impurity ions into the polycrystalline silicon film into which smoke has been diffused, amorphous, processing the polycrystalline silicon film into gate electrodes and interconnections by photolithography and etching techniques, depositing an insulating film on the semiconductor substrate on which the gate electrodes and interconnections are formed, and forming the semiconductor substrate. forming a side wall of an insulating film on the side surface of the gate electrode by anisotropic etching the entire surface; forming a titanium metal film on the entire surface of the semiconductor substrate on which the side wall has been formed; and forming the titanium metal film. The method includes a step of heat-treating the semiconductor substrate exposed to the exposed silicon surface and the titanium on the gate electrode to change it into titanium silicide, and a step of selectively removing titanium compounds and titanium metal other than the titanium silicide. Features.
また前記不純物イオンとしてアルゴンイオン、または燐
イオン、または砒素イオン、またはホウ素イオンを用い
ることを特徴とする。Further, the method is characterized in that argon ions, phosphorus ions, arsenic ions, or boron ions are used as the impurity ions.
［実施例コ
第１図（ａ）〜（ｇ）は本発明の実施例であり、本発明
の半導体装置の製造方法を工程を追って示した半導体装
置の断面図である。以下この図にしたがって本発明の半
導体装置の製造方法をを実施例として説明する。Embodiment FIGS. 1(a) to 1(g) show an embodiment of the present invention, and are cross-sectional views of a semiconductor device showing step by step the method for manufacturing a semiconductor device of the present invention. A method for manufacturing a semiconductor device according to the present invention will be described below as an example with reference to this figure.
第１図（ａ）に示すように半導体装置のシリコン基板１
上にゲート絶縁膜２を介して多結晶シリコン膜３を形成
する。本実施例ではこの第１の多結晶シリコン膜の膜厚
は４０００人とする。多結晶シリコン膜は不純物を含ま
ない状態ではほとんど導電性はない。そこで本実施例と
しては第１図（ｂ）で示すように半導体基板をオキシ塩
化燐雰囲気中において９００°Ｃで加熱処理することに
より多結晶シリコン膜中に不純物として燐を熱拡散する
ことによりＮ型の半導体として導電性をもたせた。熱拡
散により注入される燐の濃度はＰチャンネルのソース・
ドレインの不純物拡散層形成のために注入されるホウ素
の濃度より１桁以上高く拡散しておく。このように高い
濃度に燐を含んでいる多結晶シリコンに対してチタンは
シリサイドを作りにくい。次に第１図（Ｃ）”で示すよ
うに燐を拡散した多結晶シリコン膜１中に不純物イオン
をイオン注入する。本実施例では一例としてアルゴンイ
オンをイオン注入することにする。注入されたアルゴン
イオンは多結晶シリコンの結晶性を破壊し非晶質化する
ため結果として多結晶シリコンの表面近傍はアモルファ
ス化したシリコン層４となる。アモルファス化したシリ
コンはチタンと反応してチタンシリサイドになり易い。As shown in FIG. 1(a), a silicon substrate 1 of a semiconductor device
A polycrystalline silicon film 3 is formed thereon with a gate insulating film 2 interposed therebetween. In this embodiment, the thickness of this first polycrystalline silicon film is 4000. A polycrystalline silicon film has almost no conductivity when it does not contain impurities. Therefore, in this embodiment, as shown in FIG. 1(b), the semiconductor substrate is heat-treated at 900°C in a phosphorus oxychloride atmosphere to thermally diffuse phosphorus as an impurity into the polycrystalline silicon film. It has conductivity as a type of semiconductor. The concentration of phosphorus injected by thermal diffusion is
The concentration of boron is diffused at least one order of magnitude higher than the concentration of boron implanted to form the impurity diffusion layer of the drain. In contrast to polycrystalline silicon, which contains such a high concentration of phosphorus, titanium is difficult to form silicide. Next, impurity ions are implanted into the polycrystalline silicon film 1 in which phosphorus is diffused, as shown in FIG. Argon ions destroy the crystallinity of polycrystalline silicon and make it amorphous, resulting in an amorphous silicon layer 4 near the surface of the polycrystalline silicon.The amorphous silicon reacts with titanium and becomes titanium silicide. easy.
この多結晶シリコン膜とアモルファスシリコン層をフォ
トリソ技術及びエツチング技術によりゲート電極および
配線以外の部分を除去することにより第１図（ｄ）の様
に半導体基板上にゲート電極および配線を形成する。次
にこの半導体基板上の全面に絶縁膜を形成する。一実施
例としてこの絶縁膜は４ｏｏ’ｃ程度の温度での化学的
気層成長法による５ｉ０２を主成分とする絶縁膜で膜厚
は５０００人で形成した。この絶縁膜を全面に渡ってフ
ロン系ガスのプラズマ中での異方性エツチングによりケ
ート電極および配線の側面のみ残しそのほかの部分は除
去することにより、第１図（ｅ）に示すようにゲート電
極および配線の側面に絶縁膜からなるサイドウオール５
を形成する。この後第１図（ｆ）に示すように半導体基
板全面にチタン金属膜６を形成する。本実施例としてこ
のチタン金属膜の膜厚は５００人である。この半導体基
板に加熱処理を行なうことによりシリコンとチタンを反
応させシリコンと接触している部分のチタンを選択的に
チタンシリサイドに変化させる。本発明の実施例として
は、窒素ガス中でのハロゲンランプによる光照射による
短時間アニールにより３０秒間７５０°Ｃに半導体基板
表面を加熱する。この加熱によりアモルファス化した多
結晶シリコン表面のシリコン層および半導体基板のシリ
コンでシリコン表面がチタンと接触している部分が反応
してチタンシリサイドとなる。またサイドウオールの絶
縁膜上および素子分離の絶縁膜上のチタンのほとんどは
窒素と反応して窒化チタンとなる。また多少はチタンの
まま残っているがチタンシリサイド以外のチタン化合物
はアンモニア水と過酸化水素水の混合液で溶かすことが
できる。本実施例ではこの方法を用いてチタンシリサイ
ドのみを残しサイドウオール上や素子分離絶縁膜上のチ
タン金属およびチタン化合物を除去することにより第１
図（ｇ）に示すように露出したシリコン基板上、および
ゲート電極と配線である多結晶シリコン上に選択的にチ
タンシリサイド７を形成することがで９−
きた。The polycrystalline silicon film and the amorphous silicon layer are removed by photolithography and etching to form gate electrodes and wiring on the semiconductor substrate, as shown in FIG. 1(d), by removing portions other than the gate electrode and wiring. Next, an insulating film is formed over the entire surface of this semiconductor substrate. As an example, this insulating film was formed by chemical vapor deposition at a temperature of about 400° C. to a thickness of 5000 by using 5,000 people. By anisotropically etching the entire surface of this insulating film in a fluorocarbon-based gas plasma, leaving only the side surfaces of the gate electrode and wiring and removing the other parts, the gate electrode is etched as shown in Figure 1(e). and a side wall 5 made of an insulating film on the side of the wiring.
form. Thereafter, as shown in FIG. 1(f), a titanium metal film 6 is formed over the entire surface of the semiconductor substrate. In this example, the thickness of this titanium metal film is 500 mm. By subjecting this semiconductor substrate to heat treatment, silicon and titanium are reacted, and the titanium in the portion that is in contact with silicon is selectively converted into titanium silicide. As an example of the present invention, the surface of the semiconductor substrate is heated to 750° C. for 30 seconds by short-time annealing by light irradiation with a halogen lamp in nitrogen gas. As a result of this heating, the silicon layer on the polycrystalline silicon surface which has become amorphous and the silicon of the semiconductor substrate where the silicon surface is in contact with titanium react to form titanium silicide. Further, most of the titanium on the sidewall insulating film and the element isolation insulating film reacts with nitrogen to become titanium nitride. Although some titanium remains as it is, titanium compounds other than titanium silicide can be dissolved with a mixture of aqueous ammonia and hydrogen peroxide. In this example, this method is used to remove titanium metal and titanium compounds on the sidewalls and element isolation insulating film, leaving only titanium silicide.
As shown in Figure (g), titanium silicide 7 could be selectively formed on the exposed silicon substrate and on the polycrystalline silicon that is the gate electrode and wiring.
以上実施例として述べてきた本発明の半導体装置の製造
方法によれば、不純物イオンのイオン注入によりアモル
ファス化したシリコン層４はチタンと反応しやすくチタ
ンシリサイドになりやすいのに対し多結晶シリコン膜３
は不純物として烟を多量に含んでいるためチタンとの反
応が抑制される。すなわちアモルファス化したシリコン
層４をすべてチタンシリサイド７にでき、かつ多結晶シ
リコン膜３はそのまま残るためゲート電極上および配線
上にチタンシリサイドを制御性よく形成することができ
る。さらにゲート電極および配線上に形成されたチタン
シリサイドは高濃度に燐を含んだ多結晶シリコンと接触
しているため従来技術の課題であったチタンシリサイド
と多結晶シリコンの接触抵抗は低減している。According to the method of manufacturing a semiconductor device of the present invention described above as an embodiment, the silicon layer 4 made amorphous by implantation of impurity ions easily reacts with titanium and easily becomes titanium silicide, whereas the polycrystalline silicon film 3
contains a large amount of smoke as an impurity, which inhibits the reaction with titanium. That is, since the amorphous silicon layer 4 can be entirely made into titanium silicide 7 and the polycrystalline silicon film 3 remains as it is, titanium silicide can be formed on the gate electrode and wiring with good controllability. Furthermore, since the titanium silicide formed on the gate electrode and wiring is in contact with polycrystalline silicon containing a high concentration of phosphorus, the contact resistance between titanium silicide and polycrystalline silicon, which was a problem with conventional technology, has been reduced. .
さらに以上の実施例で述べてきたように多結晶シリコン
は高濃度に燐を含んでいるためＰチャンネルのソース・
ドレインを形成するための不純物であるホウ素の注入拡
散によっても燐の濃度はは１０−
とんと変化しないためＰチャンネル側のゲート電極の抵
抗が高くなったり、トランジスタのしきい値電圧が変化
することはなくなった。Furthermore, as described in the above embodiments, polycrystalline silicon contains a high concentration of phosphorus, so it can be used as a source of P channel.
Even with the implantation and diffusion of boron, which is an impurity for forming the drain, the concentration of phosphorus does not change significantly, so the resistance of the gate electrode on the P-channel side does not increase or the threshold voltage of the transistor changes. lost.
また以上の実施例においては多結晶シリコンの表面近傍
の結晶性を破壊してアモルファス化する不純物イオンと
してアルゴンイオンを例に説明してきたがアルゴンイオ
ンの他に燐や砒素、ホウ素などのイオンを用いても特に
以上の実施例で述べてきた作用と異なるものではなく、
本発明の半導体装置の製造方法と異なるものではない。Furthermore, in the above embodiments, argon ions were used as an example of impurity ions that destroy the crystallinity near the surface of polycrystalline silicon and make it amorphous, but in addition to argon ions, ions of phosphorus, arsenic, boron, etc. However, the effect is not particularly different from that described in the above embodiments,
This method is not different from the method for manufacturing a semiconductor device of the present invention.
［発明の効果］
以上述べたように、本発明によれば以下に列挙するよう
な効果を有する。[Effects of the Invention] As described above, the present invention has the following effects.
（１）ゲート電極として高濃度に燐を含んだ多結晶シリ
コン上にチタンシリサイドを制御性よく形成することが
できた。(1) Titanium silicide could be formed with good controllability on polycrystalline silicon containing a high concentration of phosphorus as a gate electrode.
（２）またゲート電極および配線である多結晶シリコン
とチタンシリサイドとの接触抵抗を低減さ１１−
せるごとができた。このことは半導体装置の高速動作に
おいて非常に有利である。(2) It was also possible to reduce the contact resistance between the polycrystalline silicon and titanium silicide, which are the gate electrode and wiring. This is very advantageous in high-speed operation of semiconductor devices.
（３）従来技術におけるシリコン表面に自己整合的にチ
タンシリサイドを形成する技術で問題であったＰチャン
ネル側のゲート電極の抵抗が高くなる問題やＰチャンネ
ルトランジスタのしきい値電圧が変化する問題を解決で
きた。(3) Solved the problems of the conventional technology of forming titanium silicide on the silicon surface in a self-aligned manner, such as the increase in resistance of the gate electrode on the P-channel side and the change in the threshold voltage of the P-channel transistor. I was able to solve it.
第１図（ａ）〜（ｇ）は、本発明の半導体装置の製造方
法を工程を追って示した半導体装置の断面図。
シリコン半導体基板
ゲート絶縁膜
多結晶シリコン膜
アモルファス化したシリコン層
サイドウオール
チタン金属
チタンシリサイド
１２−FIGS. 1(a) to 1(g) are cross-sectional views of a semiconductor device showing the method for manufacturing a semiconductor device of the present invention step by step. Silicon semiconductor substrate Gate insulating film Polycrystalline silicon film Amorphous silicon layer Sidewall Titanium metal Titanium silicide 12-
Claims (5)
を自己整合的に形成する半導体装置の製造方法において
、半導体基板上にゲート絶縁膜を介して多結晶シリコン
膜を形成する工程と、該多結晶シリコン中に燐を拡散す
る工程と、燐を拡散した多結晶シリコン膜に不純物イオ
ンをイオン注入することにより該多結晶シリコン膜の表
面近傍をアモルファス化する工程と、該多結晶シリコン
膜をフオトリソ技術とエッチング技術によりゲート電極
および配線に加工する工程と、該ゲート電極および配線
を形成した半導体基板上に絶縁膜を堆積し、前記半導体
基板全面を異方性エッチングする事により前記ゲート電
極側面に絶縁膜のサイドウォールを形成する工程と、該
サイドウォールを形成した半導体基板全面にチタン金属
膜を形成する工程と、該チタン金属膜を形成した半導体
基板を加熱処理することにより露出したシリコン表面お
よび前記ゲート電極上のチタンをチタンシリサイドに変
化させる工程と、該チタンシリサイド以外のチタン化合
物及びチタン金属を選択的に除去する工程からなること
を特徴とするＭＩＳ型半導体装置の製造方法。(1) A method for manufacturing a semiconductor device in which titanium silicide is formed on an exposed polycrystalline silicon surface in a self-aligned manner, including the steps of forming a polycrystalline silicon film on a semiconductor substrate via a gate insulating film, and a step of diffusing phosphorus into the polycrystalline silicon film; a step of implanting impurity ions into the phosphorus-diffused polycrystalline silicon film to make the surface of the polycrystalline silicon film amorphous; and converting the polycrystalline silicon film using photolithography technology. A step of processing into gate electrodes and wiring using etching technology, depositing an insulating film on the semiconductor substrate on which the gate electrode and wiring are formed, and anisotropically etching the entire surface of the semiconductor substrate to form an insulating film on the side surface of the gate electrode. a step of forming a titanium metal film on the entire surface of the semiconductor substrate on which the sidewall has been formed; and a step of forming a titanium metal film on the entire surface of the semiconductor substrate on which the sidewall has been formed; A method for manufacturing an MIS type semiconductor device, comprising a step of converting titanium on an electrode into titanium silicide, and a step of selectively removing titanium compounds and titanium metal other than the titanium silicide.
ことを特徴とする請求項１記載のＭＩＳ型半導体装置の
製造方法。(2) The method for manufacturing an MIS type semiconductor device according to claim 1, characterized in that argon ions are used as the impurity ions.
特徴とする請求項１記載のＭＩＳ型半導体装置の製造方
法。(3) The method for manufacturing an MIS type semiconductor device according to claim 1, characterized in that phosphorus ions are used as the impurity ions.
を特徴とする請求項１記載のＭＩＳ型半導体装置の製造
方法。(4) The method for manufacturing an MIS type semiconductor device according to claim 1, characterized in that arsenic ions are used as the impurity ions.
とを特徴とする請求項１記載のＭＩＳ型半導体装置の製
造方法。(5) The method for manufacturing an MIS type semiconductor device according to claim 1, characterized in that boron ions are used as the impurity ions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP479590A JP2917348B2 (en) | 1990-01-12 | 1990-01-12 | Method of manufacturing MIS type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP479590A JP2917348B2 (en) | 1990-01-12 | 1990-01-12 | Method of manufacturing MIS type semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03209834A true JPH03209834A (en) | 1991-09-12 |
| JP2917348B2 JP2917348B2 (en) | 1999-07-12 |
Family
ID=11593711
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP479590A Expired - Lifetime JP2917348B2 (en) | 1990-01-12 | 1990-01-12 | Method of manufacturing MIS type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2917348B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5554566A (en) * | 1994-09-06 | 1996-09-10 | United Microelectronics Corporation | Method to eliminate polycide peeling |
| US6033978A (en) * | 1994-07-05 | 2000-03-07 | Nec Corporation | Process of selectively producing refractory metal silicide uniform in thickness regardless of conductivity type of silicon thereunder |
| US6100170A (en) * | 1997-07-07 | 2000-08-08 | Matsushita Electronics Corporation | Method of manufacturing semiconductor device |
| KR100295383B1 (en) * | 1997-12-10 | 2001-08-07 | 다니구찌 이찌로오, 기타오카 다카시 | Semiconductor device and method for manufacturing the same |
| US6869867B2 (en) | 1997-10-01 | 2005-03-22 | Kabushiki Kaisha Toshiba | Semiconductor device comprising metal silicide films formed to cover gate electrode and source-drain diffusion layers and method of manufacturing the same wherein the silicide on gate is thicker than on source-drain |
-
1990
- 1990-01-12 JP JP479590A patent/JP2917348B2/en not_active Expired - Lifetime
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6033978A (en) * | 1994-07-05 | 2000-03-07 | Nec Corporation | Process of selectively producing refractory metal silicide uniform in thickness regardless of conductivity type of silicon thereunder |
| US5554566A (en) * | 1994-09-06 | 1996-09-10 | United Microelectronics Corporation | Method to eliminate polycide peeling |
| US6100170A (en) * | 1997-07-07 | 2000-08-08 | Matsushita Electronics Corporation | Method of manufacturing semiconductor device |
| US6869867B2 (en) | 1997-10-01 | 2005-03-22 | Kabushiki Kaisha Toshiba | Semiconductor device comprising metal silicide films formed to cover gate electrode and source-drain diffusion layers and method of manufacturing the same wherein the silicide on gate is thicker than on source-drain |
| US7220672B2 (en) | 1997-10-01 | 2007-05-22 | Kabushiki Kaisha Toshiba | Semiconductor device comprising metal silicide films formed to cover gate electrode and source-drain diffusion layers and method of manufacturing the same |
| US7638432B2 (en) | 1997-10-01 | 2009-12-29 | Kabushiki Kaisha Toshiba | Semiconductor device comprising metal silicide films formed to cover gate electrode and source-drain diffusion layers and method of manufacturing the same |
| KR100295383B1 (en) * | 1997-12-10 | 2001-08-07 | 다니구찌 이찌로오, 기타오카 다카시 | Semiconductor device and method for manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2917348B2 (en) | 1999-07-12 |
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