JP3263554B2 - Chip component and method of manufacturing the same - Google Patents
Chip component and method of manufacturing the sameInfo
- Publication number
- JP3263554B2 JP3263554B2 JP01191595A JP1191595A JP3263554B2 JP 3263554 B2 JP3263554 B2 JP 3263554B2 JP 01191595 A JP01191595 A JP 01191595A JP 1191595 A JP1191595 A JP 1191595A JP 3263554 B2 JP3263554 B2 JP 3263554B2
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- substrate
- wafer
- chip
- hybrid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、チップ部品およびその
製造方法に関し、特に安価で特性の優れたチップ部品に
関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip component and a method of manufacturing the same, and more particularly to a chip component which is inexpensive and has excellent characteristics.
【０００２】[0002]
【従来の技術】一般にチップ部品といえば、セラミツク
基板にスクリーン印刷等の技術により受動素子である、
抵抗体、コンデンサおよびコイル等が形成され、ハイブ
リッド基板に実装されている。例えば工業調査会発行の
ＩＣ化実装技術（１９８１年２版）等に詳しく述べられ
ている。2. Description of the Related Art Generally, a chip component is a passive element formed by a technique such as screen printing on a ceramic substrate.
A resistor, a capacitor, a coil and the like are formed and mounted on the hybrid board. For example, it is described in detail in an IC mounting technology (2nd edition, 1981) issued by the Industrial Research Council.
【０００３】本願は、半導体素子や受動素子に適用され
るものであるが、一例としてチップ抵抗で説明する。一
般に抵抗は、ここに流れる電流により両端に電圧が生
じ、この電圧をピックアップして制御回路等を介してコ
ントロールされる回路にフィードバックし、回路を保護
したり、制御したりしている。The present application is applied to a semiconductor element and a passive element, and will be described by using a chip resistor as an example. In general, a voltage is generated at both ends of a resistor due to a current flowing therethrough, and this voltage is picked up and fed back to a circuit controlled via a control circuit or the like to protect or control the circuit.
【０００４】例えば、特開昭６３−１２８６７５号公報
は、抵抗体を出力トランジスタのエミッタ側に付け、こ
の抵抗体に流れる電流を検出して、この出力トランジス
タの保護をしている。前述のようにチップ抵抗と称する
ものは、一般にセラミツク基板等の絶縁性基板に実装し
てあり、抵抗体自身の温度特性、絶縁性基板の熱伝導率
等を考慮すると好ましいものでなく、本公報では、金属
基板に貼着されたＣｕ配線自身を活用し、熱伝導率は金
属基板により、温度特性は、正の温度特性をコンペンセ
イトする素子を実装して補償したりしていた。For example, Japanese Patent Application Laid-Open No. 63-128675 discloses that a resistor is attached to the emitter side of an output transistor, and a current flowing through the resistor is detected to protect the output transistor. As described above, what is called a chip resistor is generally mounted on an insulating substrate such as a ceramic substrate, and is not preferable in consideration of the temperature characteristics of the resistor itself, the thermal conductivity of the insulating substrate, and the like. Has utilized the Cu wiring itself adhered to the metal substrate, and compensated for the thermal conductivity by mounting the element compensating for the positive temperature characteristic with the metal substrate.
【０００５】従って損失を少なくするために極めて小さ
い抵抗値にする必要があり、ここでは前述したようにＣ
ｕであるために比較的狭い配置面積で抵抗値を小さくで
き、また金属基板であるが故に放熱性が良くその分余計
に電流を流すことができる。Therefore, it is necessary to make the resistance value extremely small in order to reduce the loss.
Since u is used, the resistance value can be reduced with a relatively small arrangement area, and since the metal substrate is used, the heat dissipation is good, so that more current can flow.
【０００６】[0006]
【発明が解決しようとする課題】前述のＣｕ配線の一部
を抵抗体とする場合、Ｃｕ配線は、箔形状とするための
圧延工程で厚みのバラツキが有り、これを基板全面に貼
り付けてからエッチングして配線とするために、エッチ
ングのバラツキやサイドエッチングにより、精度の高い
ものが得られない問題があった。またＣｕの温度係数
は、約４０００ｐｐｍ程度と高く温度変化に対する抵抗
値の変動を例えばダイオード等で補正する必要があっ
た。When a part of the above-described Cu wiring is used as a resistor, the Cu wiring has a thickness variation in a rolling process for forming a foil shape, and this is attached to the entire surface of the substrate. Since a wiring is formed by etching from the beginning, there is a problem that a high-precision one cannot be obtained due to variations in etching and side etching. Further, the temperature coefficient of Cu is as high as about 4000 ppm, and it is necessary to correct the fluctuation of the resistance value due to the temperature change by using, for example, a diode.
【０００７】またセラミツク基板等の絶縁材料の基板上
に抵抗体を形成するチップ抵抗は、自動ダイボンド装置
等で簡単に実装する事が可能ではあるが、基板自身の熱
伝導率が小さく大電流を流した際に生ずる熱を外部に放
出しずらい問題があった。以上、前述した問題点、且つ
コスト的課題も含めて両者を解決できるものがなかっ
た。Although a chip resistor for forming a resistor on a substrate made of an insulating material such as a ceramic substrate can be easily mounted by an automatic die bonding apparatus or the like, the heat conductivity of the substrate itself is small and a large current is required. There is a problem that it is difficult to release the heat generated when flowing to the outside. As described above, there is no one that can solve both of them including the problems described above and the cost problem.
【０００８】[0008]
【課題を解決するための手段】本発明は前述の問題に鑑
みて成され、第１に、半導体基板に、不良品を使用する
ことで解決するものである。第２に、素子が実装されな
い半導体基板面には、半田となじむ電極を設け、ハイブ
リッド基板上に設けられた導電路と半田を介して固着す
ることで解決するものである。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and is firstly solved by using a defective semiconductor substrate. Second, the problem is solved by providing an electrode compatible with solder on the surface of the semiconductor substrate on which the element is not mounted, and fixing the electrode to a conductive path provided on the hybrid substrate via solder.
【０００９】第３に、ウェハへの加工工程またはウェハ
での半導体プロセス工程にに於いて不良となったウェハ
を用意し、ウェハの表面又は裏面に素子を実装する事で
解決するものである。Third, the problem is solved by preparing a wafer which has become defective in a wafer processing step or a wafer semiconductor processing step, and mounting elements on the front surface or the back surface of the wafer.
【００１０】[0010]
【作用】第１に比較的熱伝導率の良いシリコンを受動素
子を実装する基板として着目し、且つコスト的にはウェ
ハの不良品に着目した。つまり個々にスクライブした不
良ウェハ基板をハイブリッドＩＣの上に実装するヒート
シンクとして活用し、しかも通常の半導体技術を使って
不良ウェハの上にチップを形成することで、熱伝導率が
優れ、安価で精度の高いチップが実現できる。ここで熱
伝導率を、厚さ１ｍの板の両面に１Ｋの温度差が有ると
き、その板の面積１ｍ２の面を通して流れる熱量で表し
たとき、アルミナは２１、ガラスは約０．５から１、Ｃ
ｕは約４００およびシリコンは１６８である（昭和６３
年１１月３０日発行の理科年表より参照）。First, attention has been paid to silicon having relatively good thermal conductivity as a substrate on which passive elements are mounted, and to defective wafers in terms of cost. In other words, the individually scribed defective wafer substrate is used as a heat sink to be mounted on the hybrid IC, and chips are formed on the defective wafer using ordinary semiconductor technology, resulting in excellent thermal conductivity, low cost, and high accuracy. Chips with high performance can be realized. Here, when the thermal conductivity is represented by the amount of heat flowing through a 1 m2 area of a plate having a temperature difference of 1 K on both sides of a 1 m thick plate, alumina is 21 and glass is about 0.5 to 1 , C
u is about 400 and silicon is 168 (Showa 63
(Refer to the science chronology issued on November 30, 2011).
【００１１】第２に、シリコンウェハの裏面には、電極
が形成できるので、例えばＣｒ−Ｎｉ−Ａｕ等の半田付
けが可能な電極を形成することにより、不良ウェハの上
に実装された受動素子をスクライブして個々に分割した
チップを通常のハイブリッド基板にオートダイボンダー
で簡単に実装できる。第３に、例えば、シリコン基板に
拡散領域等が形成されトランジスタ等が作り込まれてい
ても、素子の実装面に絶縁層を形成してから受動素子を
形成しているので、シリコン基板内に何が作り込まれて
いてもなんら問題なくチップ素子として形成可能であ
る。Second, since an electrode can be formed on the back surface of the silicon wafer, a passive element mounted on a defective wafer is formed by forming a solderable electrode such as Cr-Ni-Au. Can be easily mounted on an ordinary hybrid board with an auto die bonder. Third, for example, even if a transistor or the like is formed by forming a diffusion region or the like on a silicon substrate, since a passive element is formed after forming an insulating layer on a mounting surface of the element, Whatever is built, it can be formed as a chip element without any problem.
【００１２】[0012]
【実施例】本発明の実施例を図１〜図３を使って説明す
る前に、本願の最大のポイントについて説明する。本願
のポイントは、通常のＩＣの製造工程において排出され
る不良ウェハを使用することであり、受動素子を形成す
る基板として廃棄されるシリコンウェハを使用するので
コストを大幅に削減する事であり、また通常の半導体技
術でウェハの上に受動素子を形成し、セラミック等の絶
縁基板よりも熱伝導率の優れた基板（ヒートシンク）と
して活用し、半導体チップと同様にオートマウンターで
実装するものである。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing an embodiment of the present invention with reference to FIGS. The point of the present application is to use a defective wafer discharged in a normal IC manufacturing process, and to use a discarded silicon wafer as a substrate for forming a passive element, thereby greatly reducing costs. In addition, passive elements are formed on a wafer by ordinary semiconductor technology, and utilized as a substrate (heat sink) having a higher thermal conductivity than an insulating substrate such as a ceramic, and mounted by an automounter like a semiconductor chip. .
【００１３】例えば、バイポーラＩＣの製造工程は、大
まかに説明すると以下のようになる。まず（１）Ｐ型基
板の用意、（２）表面の酸化、（３）この酸化膜の一部
に導入口を形成し、（４）Ｎ＋埋め込み層の形成、
（５）酸化膜除去、（６）Ｎ型エピ層の形成、（７）エ
ピ層表面の酸化、（８）アイソレーションの導入口の酸
化膜形成、（９）アイソーレーションの拡散、（１０）
ベースの導入口およびベースの拡散、（１１）エミッタ
の導入口の形成および拡散、（１２）酸化膜除去、（１
３）酸化膜の形成、（１４）コンタクト口形成、（１
４）メタルの形成の１４工程が有る。For example, the manufacturing process of a bipolar IC is roughly described as follows. First, (1) preparing a P-type substrate, (2) oxidizing the surface, (3) forming an inlet in a part of this oxide film, (4) forming an N + buried layer,
(5) removal of oxide film, (6) formation of N-type epilayer, (7) oxidation of epilayer surface, (8) formation of oxide film at isolation inlet, (9) diffusion of isolation, (10) )
(11) Formation and diffusion of an inlet for an emitter, (12) Removal of an oxide film, (1)
3) formation of an oxide film, (14) formation of a contact port, (1)
4) There are 14 steps of metal formation.
【００１４】一般に受動素子を形成する場合、表面がフ
ラットで有る方が好ましいため、（１）〜（２）、
（５）〜（７）および（１２）等の工程で不良となった
ものが好ましい。つまりシリコン表面に絶縁膜および／
またはエピ層が形成されているが、導入口やコンタクト
等のための凸凹が無いため、ウェハ表面がフラットであ
る理由に依るためである。In general, when a passive element is formed, it is preferable that the surface be flat, so that (1) to (2),
(5)-(7) and (12) are preferably defective. That is, the insulating film and / or
Alternatively, an epitaxial layer is formed, but there is no unevenness for an introduction port, a contact, and the like, and this is because the wafer surface is flat.
【００１５】またＭＯＳＩＣの製造工程では、（１）Ｐ
型基板の用意、（２）全面酸化、（３）シリコン窒化膜
の全面形成、（４）ロコス酸化のための前記窒化膜除
去、（５）窒化膜を耐酸化マスクとしてロコス酸化、
（６）窒化膜、酸化膜除去、（７）ゲート酸化膜の形
成、（８）ゲートを形成し、ゲートにセルフアラインし
てソース・ドレインを形成、（９）全面にＣＶＤによる
絶縁膜形成、（１０）コンタクト形成、（１１）メタル
形成の１１工程がある。In the manufacturing process of the MOSIC, (1) P
Preparation of a mold substrate, (2) overall oxidation, (3) formation of a silicon nitride film, (4) removal of the nitride film for locos oxidation, (5) locos oxidation using the nitride film as an oxidation resistant mask,
(6) removal of a nitride film and an oxide film; (7) formation of a gate oxide film; (8) formation of a gate; self-alignment of the gate to form a source / drain; (9) formation of an insulating film by CVD over the entire surface; There are 11 steps of (10) contact formation and (11) metal formation.
【００１６】前述したように、基板表面がフラットであ
ることが好ましいことから、（１）〜（３）で不良とな
ったウェハが好ましい。また前述した好ましい工程以外
でも、最初に凸凹ウェハにガラス等を形成してフラット
にするか、または凸凹表面をエッチングしてフラットに
しても良い。図１は、不良ウェハ１採用していることを
示すために、バイポーラＩＣプロセスで、埋め込み領域
２と分離領域３が形成された状態で不良となったとして
説明しており、分離領域形成の際の不純物導入口４がシ
リコン酸化膜５に示されている。６は、絶縁層であり、
導入口４を埋め実質的にきばん表面をフラットにすれば
良く、ガラスや樹脂で成る。また７は、裏電極で、ハイ
ブリッド基板の導電路に実装する際、簡単に半田付けで
きるように、例えばＣｒ−Ｎｉ−Ａｕの順で積層されて
いる。抵抗体８は、実質的にフラットにされた基板表
面、つまり絶縁層６の表面に例えばＣｒ−Ｎｉ−Ｍｎの
順で積層されて形成されている。また抵抗体８の両端に
は、Ａｌ電極９が形成されている。As described above, since the surface of the substrate is preferably flat, a wafer which is defective in (1) to (3) is preferable. In addition to the above-described preferred steps, glass or the like may be first formed on the uneven wafer to make it flat, or the uneven surface may be etched to make it flat. FIG. 1 illustrates that a defective wafer 1 is employed in the bipolar IC process in a state where the buried region 2 and the isolation region 3 are formed in order to show that the defective wafer 1 is employed. Is shown in the silicon oxide film 5. 6 is an insulating layer,
What is necessary is just to fill the inlet 4 and make the surface of the bag substantially flat, and it is made of glass or resin. Reference numeral 7 denotes a back electrode, which is laminated, for example, in the order of Cr-Ni-Au so that it can be easily soldered when mounted on the conductive path of the hybrid substrate. The resistor 8 is formed on the substantially flat substrate surface, that is, the surface of the insulating layer 6 by, for example, laminating Cr-Ni-Mn in this order. Al electrodes 9 are formed at both ends of the resistor 8.
【００１７】図２の抵抗体も同様であるが、温度係数Ｔ
ＣＲは、実質±５０ＰＰＭ程度で、抵抗体として数ｍｍ
Ωから実現可能である。１９８９年第６２冊の理科年表
４７７ページに依れば、アルミナは、常温で２１κ、ポ
リエチレンが０．２５程度、珪素は０度で１６８κ、ア
ルミニウムは、０度で２３６κ、Ｃｕは、０度で４０３
κである。ここでκの単位は、Ｗ／（ｍ・Ｋ）である。
説明するまでもないが、シリコン基板１の上に配置され
ているので、絶縁性基板の上に形成された抵抗体よりも
放熱性が優れている。The same applies to the resistor shown in FIG.
CR is substantially ± 50 PPM and several mm as a resistor.
Can be realized from Ω. According to page 477 of the Science Chronology Table of the 62nd volume of 1989, alumina is 21 K at ordinary temperature, polyethylene is about 0.25, silicon is 168 K at 0 degree, aluminum is 236 k at 0 degree, and Cu is 0 degree. At 403
κ. Here, the unit of κ is W / (m · K).
Needless to say, since it is arranged on the silicon substrate 1, it has better heat dissipation than a resistor formed on an insulating substrate.
【００１８】一方、図２は、図１の抵抗体にパシベーシ
ョン膜１０が形成されているものである。ウェハ１は、
好ましい工程で形成されたもので、表面１１が絶縁層で
有れば、別途絶縁層を付けても付けなくても良い。しか
しエピタキシャル層やシリコン層であれば、別途前記絶
縁層１１を全表面に設ける必要がある。またエッチング
によりシリコン層が露出している場合も、別途絶縁層を
設ける必要がある。FIG. 2 shows a structure in which a passivation film 10 is formed on the resistor shown in FIG. Wafer 1
It is formed by a preferable process, and if the surface 11 is an insulating layer, an insulating layer may or may not be separately provided. However, in the case of an epitaxial layer or a silicon layer, it is necessary to separately provide the insulating layer 11 on the entire surface. Also, when the silicon layer is exposed by etching, it is necessary to provide an insulating layer separately.
【００１９】図３は、図１の平面図であり、抵抗体８と
相似形で縮小された抵抗体２０が電極９とコンタクトし
て配置されており、抵抗体２０の左端には電極２１が設
けられている。電極２１は、プロービングの際に使用す
る電極で、抵抗体２０をみて抵抗体８の抵抗値を予測す
るものである。図４は、ハイブリッドＩＣ基板３０に前
述した抵抗チップ１を実装した図であり、例えば金属基
板、ＡｌやＣｕの基板３０に絶縁層３１を介して貼着さ
れた導電路３２や導電ランド３３があり、導電ランド３
３には図面では省略したが半田を介して抵抗チップの裏
電極が接続されている。また表面にある電極９，９は、
金属細線を介して導電路３２と電気的に接続されてい
る。FIG. 3 is a plan view of FIG. 1, in which a reduced resistor 20 similar to the resistor 8 is arranged in contact with the electrode 9, and an electrode 21 is provided on the left end of the resistor 20. Is provided. The electrode 21 is an electrode used for probing, and predicts the resistance value of the resistor 8 by looking at the resistor 20. FIG. 4 is a diagram in which the above-described resistor chip 1 is mounted on a hybrid IC substrate 30. For example, a conductive path 32 and a conductive land 33 attached to a metal substrate, an Al or Cu substrate 30 via an insulating layer 31 are provided. Yes, conductive land 3
Although not shown in the drawing, the back electrode 3 of the resistor chip is connected to 3 via solder. The electrodes 9 on the surface are
It is electrically connected to the conductive path 32 via a thin metal wire.
【００２０】以上説明したように、前述した工程で不良
となったウェハを用意し、必要により耐絶縁および目的
の抵抗値の達成のために絶縁層を形成し、裏面または表
面の一方に、前述した抵抗体や電極を形成し、ウェハ内
にマトリックス状に形成された抵抗体（受動素子）をス
クライバーで個々に分割し、この分割された抵抗体チッ
プを図４のように、ハイブリッドＩＣに実装し、ワイヤ
ーボンドする。この一連のプロセスにより、安価なチッ
プ抵抗が通常の半導体プロセスにて形成でき、しかも基
板自身熱抵抗が小さいので、金属基板に実装すればヒー
トシンクとして働くと共に、基板に熱を良好に伝えるこ
とができ、抵抗体の熱による抵抗値変化も防止できる。
或いは、Ｃｕ等のヒートシンクブロックの上に実装して
も良い。この場合、ランドとブロックが半田や銀ペース
ト等で固着される。しかも材料により温度係数の小さい
抵抗対が実現できるので、高精度で低抵抗の抵抗体が実
現できる。従って、出力トランジスタの出入口に検出用
の抵抗体として活用すれば、抵抗値が小さいためロスが
すくなく、精度の高い検出が可能となる。従って抵抗体
の電圧を制御回路にフィードバックして出力トランジス
タを制御すれば、出力トランジスタの保護が高精度で実
現できる。As described above, a wafer which has become defective in the above-described process is prepared, and if necessary, an insulating layer is formed to achieve insulation resistance and a desired resistance value. Resistors and electrodes formed in a matrix, and the resistors (passive elements) formed in a matrix in the wafer are individually divided by a scriber, and the divided resistor chips are mounted on a hybrid IC as shown in FIG. And wire bond. Through this series of processes, inexpensive chip resistors can be formed by ordinary semiconductor processes, and since the substrate itself has low thermal resistance, it can act as a heat sink if mounted on a metal substrate and conduct heat well to the substrate. Also, it is possible to prevent a change in resistance value due to heat of the resistor.
Alternatively, it may be mounted on a heat sink block of Cu or the like. In this case, the land and the block are fixed with solder, silver paste, or the like. In addition, since a resistor pair having a small temperature coefficient can be realized by a material, a resistor with high precision and low resistance can be realized. Therefore, if a resistor for detection is used at the entrance and exit of the output transistor, the loss is small due to the small resistance value, and highly accurate detection is possible. Therefore, if the output transistor is controlled by feeding back the voltage of the resistor to the control circuit, the protection of the output transistor can be realized with high accuracy.
【００２１】[0021]
【発明の効果】以上の説明から明らかなように、不良と
なったウェハを基板として活用すれば、基板のコストが
比較にならないほど安価とすることができる。しかもシ
リコンは熱抵抗が絶縁体よりもはるかに小さいため、基
板の上に載せる受動素子が熱を発生しても良好に外部に
放出できる。As is clear from the above description, if a defective wafer is used as a substrate, the cost of the substrate can be reduced so as to be incomparable. Moreover, since silicon has a much lower thermal resistance than an insulator, even when a passive element mounted on a substrate generates heat, it can be satisfactorily released to the outside.
【００２２】第二に、ウェハの裏面（抵抗体実装面と異
なる面）に半田付け可能な電極を形成すれば、ハイブリ
ッド基板に半田を介して実装でき、通常の半導体チップ
の実装と同様にハイブリッド基板に実装できる。第３に
ウェハ内にマトリックス状に数多く抵抗体が形成でき、
安価な基板に数多く抵抗体が形成できるため、非常に安
価なものが実現できる。またリサイクルの面でも有効で
ある。Secondly, if solderable electrodes are formed on the back surface of the wafer (a surface different from the resistor mounting surface), the electrodes can be mounted on the hybrid substrate via solder, and the hybrid can be mounted in the same manner as a normal semiconductor chip. Can be mounted on a board. Third, a large number of resistors can be formed in a matrix in the wafer,
Since many resistors can be formed on an inexpensive substrate, a very inexpensive substrate can be realized. It is also effective in terms of recycling.
【図１】本発明のチップ部品を説明する図である。FIG. 1 is a diagram illustrating a chip component of the present invention.
【図２】本発明のチップ部品を説明する図である。FIG. 2 is a diagram illustrating a chip component of the present invention.
【図３】図１の平面図である。FIG. 3 is a plan view of FIG. 1;
【図４】チップ部品をハイブリッド基板に実装した断面
図である。FIG. 4 is a cross-sectional view in which chip components are mounted on a hybrid substrate.
１ 基板 ６ 絶縁層 ７ 裏電極 ８ 抵抗体 ９ 電極 １０ パシベーション膜 ３０ ハイブリッド基板 Reference Signs List 1 substrate 6 insulating layer 7 back electrode 8 resistor 9 electrode 10 passivation film 30 hybrid substrate
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 23/12 H01L 21/60 H01L 21/88 H01L 21/82 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 23/12 H01L 21/60 H01L 21/88 H01L 21/82
Claims (2)
絶縁層上に能動素子または受動素子を形成したチップ部
品であり、 前記半導体基板はウェハへの加工工程またはウェハでの
半導体プロセス工程において排出される不良ウェハであ
り、 前記素子が実装されない半導体基板面には、半田となじ
む電極が設けられ、ハイブリット基板上に設けられた導
電路とロウ材を介して固着されることを特徴とするチッ
プ部品。1. A chip component having an active element or a passive element formed on an insulating layer formed on a front surface or a back surface of a semiconductor substrate, wherein the semiconductor substrate is discharged in a wafer processing step or a semiconductor processing step on the wafer. Chip component, wherein an electrode compatible with solder is provided on the surface of the semiconductor substrate on which the elements are not mounted, and is fixed to a conductive path provided on the hybrid substrate via a brazing material. .
導体プロセス工程に於いて排出される不良ウェハを用意
し、 前記ウェハ上に受動素子を実装し、 前記ウェハに形成された受動素子を個別分離し、前記排
出される不良ウェハをヒートシンクとして再利用するこ
とを特徴とするチップ部品の製造方法。 2. A process for processing a wafer or a half process on a wafer.
Prepare defective wafers discharged in conductor processing process
Then , passive elements are mounted on the wafer, the passive elements formed on the wafer are individually separated, and the
Re-use the defective wafers as heat sinks
And a method of manufacturing a chip component.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP01191595A JP3263554B2 (en) | 1995-01-27 | 1995-01-27 | Chip component and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP01191595A JP3263554B2 (en) | 1995-01-27 | 1995-01-27 | Chip component and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08204063A JPH08204063A (en) | 1996-08-09 |
| JP3263554B2 true JP3263554B2 (en) | 2002-03-04 |
Family
ID=11791008
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP01191595A Expired - Fee Related JP3263554B2 (en) | 1995-01-27 | 1995-01-27 | Chip component and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3263554B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005159120A (en) | 2003-11-27 | 2005-06-16 | Disco Abrasive Syst Ltd | Method for manufacturing chip resistor |
-
1995
- 1995-01-27 JP JP01191595A patent/JP3263554B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH08204063A (en) | 1996-08-09 |
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