JP3240292B2 - 半導体パッケージ - Google Patents
半導体パッケージInfo
- Publication number
- JP3240292B2 JP3240292B2 JP27342499A JP27342499A JP3240292B2 JP 3240292 B2 JP3240292 B2 JP 3240292B2 JP 27342499 A JP27342499 A JP 27342499A JP 27342499 A JP27342499 A JP 27342499A JP 3240292 B2 JP3240292 B2 JP 3240292B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor package
- terminal
- power semiconductor
- copper plate
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
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Description
と下側プレート部材の間に半導体ダイが配置された半導
体パッケージに関し、さらに詳細には、MOSFET半
導体ダイのソースが上側プレート部材を介してリードフ
レームに電気的に結合され、MOSFETのゲートがワ
イヤボンディングを介してリードフレームに電気的に結
合された、SO8半導体パッケージに関する。
体パッケージ10が示してある。この半導体パッケージ
10は、底部プレート部分13および端子12a、12
bを含む。半導体ダイ16は、底部プレート13の上に
配置され、通常はエポキシ材料を使用してこれに固定さ
れる。半導体ダイ16は、半導体ダイ16の上部表面の
接続エリアを画定する金属化(metalized)領
域18(通常はアルミニウム)を含む。端子12a、1
2bの一部分、底部プレート部分13、および半導体ダ
イ16は、通常は成形性(moldable)材料で形
成されるハウジング22中に封入される。金属化領域1
8と端子12bの間の電気接続を得るために、1本また
は複数本のワイヤ20を、一端21aで金属化領域18
に、末端21bで端子12bに超音波ボンディングす
る。
100を示す図である。金属化領域18と端子12bと
を電気的に接続するために、1本または複数本のワイヤ
24を位置23でスティッチボンディングし、それによ
り半導体ダイ16から端子12bに電流が流れる追加経
路を提供する。これにより、半導体ダイ16から端子1
2bまでの電流経路の抵抗がわずかに低下する。
の性能を確保するために、パワー半導体パッケージを通
る電流経路の抵抗およびインダクタンスを大幅に低下さ
せることが望ましい。残念ながら、従来技術の半導体パ
ッケージではこの目的は完全には達成されないが、これ
は特に、金属化領域18の1つのエリアとワイヤ20の
末端21aとの間の距離Dが金属化領域18から端子1
2bへの電流経路の抵抗を増大させるからである。この
問題は、金属化領域18の厚さが比較的薄い(通常はこ
の厚さは約4から8ミクロンである)ときに悪化する。
比較的薄い金属化領域18と、距離Dおよびワイヤボン
ディング20の断面プロフィルとが相まって、それを通
る電流経路の抵抗およびインダクタンスを比較的高くす
ることになる。
ケージ)では、距離Dは約80から100ミルであり、
その結果、金属化領域18の抵抗は約0.79から1.
58ミリオームとなる。ワイヤ20、24の直径は約2
ミルであり、約1.05ミリオームの抵抗を生じる(ワ
イヤ14本使用時)。端子およびエポキシの抵抗を合計
すると約0.307ミリオームとなるので、このような
パッケージは、約2.14から2.93ミリオームの全
抵抗を示す。その結果生じるパッケージの熱抵抗RJA
は、62.5EC/Wに達する可能性がある。
T半導体ダイ16を含むときには、距離Dおよびワイヤ
20、24の比較的小さな直径によって引き起こされる
抵抗がMOSFETの全抵抗に加算される。実際には、
ダイ16がMOSFETダイであるときには、端子12
aは通常はMOSFETのドレインに結合され、端子1
2bは1本または複数本のワイヤボンディング20を介
してMOSFETのソースに結合される。MOSFET
ダイのオン抵抗が小さくなるほど、距離Dおよびワイヤ
ボンディング20、24によって引き起こされる抵抗
が、端子12aからもう一方の端子12bまでの全抵抗
に占める割合は大きくなる。もちろん、MOSFETな
どの半導体デバイスの高周波性能は、デバイスを通る端
子から端子までの抵抗およびインダクタンスの影響をか
なり受ける。
化領域18と端子12bの間の電気的接続を得るため
に、大きな金属ストラップを組み込んでいる。残念なが
ら、この技法は、バイポーラ接合トランジスタやダイオ
ード、サイリスタなど、比較的単純な表面構造を有する
大規模な半導体パッケージでなければ可能でない。さら
に、金属ストラップは、外形の小さなパッケージ(SO
8や表面実装型デュアルインラインパッケージなど)で
は実用的ではない。
で大きな金属ストラップを使用することは、このような
デバイスが比較的複雑な表面構造を有するので、これま
でのところ達成されていない。特にMOSゲートデバイ
スは、通常は、ゲート電位がダイ表面全体に分配される
ように表面を横切る、半導体ダイの表面上に配置された
ゲートランナ(gate runner)(またはバ
ス)を含む。その結果として、ゲートランナがダイ表面
へのアクセスを制限し、また金属ストラップに短絡する
可能性もあるので、大きな金属ストラップをダイ表面の
上に配置することには問題がある。したがって、MOS
ゲート半導体デバイスで金属ストラップを使用すること
はできない。
OSゲートデバイスを通る電流経路の抵抗を低下させ、
この電流経路のインダクタンスを低下させることによっ
て従来技術の半導体パッケージの欠点を克服する、新し
い半導体パッケージが必要とされている。
るために、本発明の1つの態様による半導体パッケージ
は、底部プレート部分およびこの底部プレート部分から
延びる少なくとも1つの第1の端子を有する底部リード
フレーム、この第1の端子と同一平面上にある少なくと
も1つの第2の端子、第1の端子がドレインに電気的に
接続されるようにリードフレームの底部プレートに結合
された、ドレイン接続を画定する底部表面と、ソースを
画定する第1の金属化領域、およびゲートを画定する第
2の金属化領域がその上に配置された上部表面とを有す
る半導体パワーMOSFETダイ、ソース接続を画定す
る第1の金属化領域の大部分に結合され、その大部分に
及ぶ銅板、ならびに第2の端子がソースに電気的に結合
されるようにこの銅板部分を少なくとも1つの第2の端
子に結合するようにサイズを取られ成形された、少なく
とも1つのビーム部分を含む。
くつかの形態を図面に示すが、本発明は図示の配列およ
び手段に厳密に限定されるわけではないことを理解され
たい。
番号で示す図面を参照すると、本発明の一態様による半
導体パッケージ110の側面図が図3に示してある。半
導体パッケージ110は、底部表面が底部プレート13
に結合された半導体ダイ16を含む。好ましくは、半導
体ダイ16はMOSFETダイであり、端子12aはM
OSFETダイ16のドレインに電気的に結合される。
もちろん、半導体ダイ16は、ダイオードや絶縁ゲート
バイポーラトランジスタなど、その他の形態をとること
もできる。
続を画定する金属化領域18を有する上部表面を含む。
例えば、半導体ダイ16がMOSFETであるときに
は、金属化領域18はソース接続を画定することができ
る。
8を端子12bに電気的に結合するために利用されるス
トラップ部材28も含む。各ストラップ部材28は、十
分に厚いプレート部分30、および成形ビーム部分34
を含むことが好ましい。プレート部分30は銅で形成さ
れることが好ましく、金属化領域18の大部分に及ぶ。
ビーム部分34は、プレート部分30を端子12bに結
合するように成形され、サイズを取られている。
0の側縁部に結合され、それぞれの端子12bに結合さ
れた末端36を含むことが好ましい。
されるように、硬化性(curable)導電材料46
(銀充填導電性エポキシなど)を、プレート部分30の
下側表面と金属化領域18の間に配置することが好まし
い。軟質はんだを使用することもできる。
ラスチックなど)から形成されたハウジング22を含
み、パッケージの構成がSO8標準に準拠することが好
ましい。
化領域18に結合する比較的大きな接触領域を提供し、
それにより電流に対する抵抗を低下させ、インダクタン
スを低下させる。これにより、高周波での性能の改善が
もたらされる。さらに、この構造には、ストラップ部材
28を介して半導体ダイ16から熱が逃げる熱経路がも
たらされるという利点もある。
4および図6で最もよく分かるように、ビーム部分34
は、プレート部分30の1つの側縁部から延びて端子1
2bで終端する1つの流れ部材(flowing me
mber)として一体化されて形成されることが好まし
い。図5は、図4のパッケージの斜視図である。
のゲートを画定する。金属化領域19はワイヤボンディ
ング20を介して1つの端子12cに電気的に結合され
る。このように、本発明では、MOSFETダイ16の
上部表面への混合接続、すなわちソースに接続するため
の低抵抗プレート部分30、およびゲート19に接続す
るためのワイヤボンディング20を利用する。
ナ(またはバス)19aは、ゲート金属化領域19をダ
イ16の表面のソース領域に結合する。プレート部分3
0は、ゲートランナ19aの最も外側の部分を超えて横
方向に延びることが好ましい。また、プレート部分30
は、ゲートランナ19aを超えて延び、可能な限り大き
くこれを覆うことが好ましい。これにより、性能改善の
達成が保証される。
面図である。ゲートランナ19aの一部分は、金属化領
域18の間に配置して示してある。はんだ濡れ性金属
(TiNiAgなど)を金属化領域18の上に配置する
ことが好ましい。ゲートランナ19aをプレート部分3
0から絶縁するために、窒化物層27をゲートランナ1
9aの上に配置する。硬化性導電材料46(好ましくは
銀充填エポキシ)をはんだ濡れ性金属25の上に配置
し、プレート部分30を金属化領域18に電気的かつ機
械的に結合する。プレート部分30は、ゲートランナ1
9aを妨害することなく電気的かつ熱的に金属化領域1
8と結合される。
れ性金属25にはんだ付けすることもできることに留意
されたい。しかし、銀充填エポキシ46を利用して、プ
レート部分30を金属化領域18に結合することが好ま
しい。導電性エポキシ46を利用するときには、はんだ
濡れ性金属25を除去し、エポキシを直接金属化領域1
8と接触させることができる。
参照する。特に、ビーム部分34の末端は、端子12b
の付近にボイド42を形成するヒール37と、トウ(t
oe)38とを含む。ビーム部分34の末端は、ボイド
42を通って端子12bに向かって延びる下向きの突起
40を含むことが好ましい。硬化性導電材料44をボイ
ド42中に導入し、ビーム部分34の末端の端子12b
への電気的および機械的な結合を容易にすることが好ま
しい。本発明で使用するのに適した硬化性導電媒質44
は、既知の導電性エポキシおよびその類似のもの(銀充
填エポキシであることが好ましい)のいずれかから選択
することができる。
ケージ116の切欠斜視図である図9を参照する。図9
の半導体パッケージ116は、複数のビーム部分34が
クロスバー部分50で終端する点を除けば、前述の実施
形態のパッケージとほぼ同じである。クロスバー部分5
0は少なくとも2つの端子12bに結合される。
に位置するボイドを画定する長手方向ヒール52および
長手方向トウ54を含むことが好ましい。ボイド56
は、クロスバー部分50のほぼ全長にわたって延びるチ
ャネルの形をしている。クロスバー部分50は、チャネ
ルを通って端子12bに向かって延びる下向きの突起5
8(壁面の形状)を含むことが好ましい。硬化性導電材
料(導電性エポキシなど)の層をチャネル内に配置し、
クロスバー部分50を端子12bに結合することが好ま
しい。
パッケージ118の切欠斜視図を示す図10を参照す
る。半導体パッケージ118は、プレート部分30、ビ
ーム部分34、および端子12bが全て一体に結合さ
れ、好ましくは共通の材料シートから形成される点を除
けば、本発明の前述の実施形態と同様である。したがっ
て、端子12bは、ハウジング22の外側からハウジン
グ内部に、半導体ダイ16の上部をかなり覆って延び、
半導体ダイ16を上部プレート部分30と底部プレート
部分13の間に挟む。
金、銀など)から形成することができること、および複
数の流動性導電バンプ(好ましくははんだバンプ、図示
せず)を金属化領域18の表面上に配置することができ
ることに留意されたい。さらに、プレート部分30は、
電気的かつ/または機械的に流動性導電バンプおよび金
属化領域18と係合することができるように、流動性導
電バンプと反対に配向された下側表面を含むことができ
る。
部分30から流動性導電バンプおよび金属化領域18に
向かって延びる、1つまたは複数の下向きの突起を含む
こともできる。
04ミルであるときには、パッケージに導入される抵抗
はわずか約0.115ミリオームであることが分かって
いる。全体で約0.08ミリオームとなる金属化領域1
8を使用すると、本発明によるパッケージの全抵抗はわ
ずか約0.506ミリオームとなる(従来技術のパッケ
ージより50%から75%の改善)。さらに、本発明の
パッケージの熱抵抗RJAは、最大でわずか約46EC
/Wとなる(従来技術のパッケージより25%の低
下)。
の説明は、例示および説明を目的として与えたものであ
る。これは本発明を網羅する、または本発明を開示の形
態に厳密に限定するものではない。上記の教示に照らし
て多くの修正および変形が可能である。本発明の範囲
は、この詳細な説明ではなく、添付の特許請求の範囲に
よって限定されるものとする。
る。
る。
る。
上面図である。
図である。
ジの断面図である。
欠斜視図である。
形態の切欠斜視図である。
施形態の切欠斜視図である。
Claims (28)
- 【請求項1】 底部プレート部分および該底部プレート
部分から延びる少なくとも1つの第1の端子を有する底
部リードフレーム、 前記第1の端子と同一平面上にある少なくとも1つの第
2の端子、 前記第1の端子がドレインに電気的に接続されるように
前記リードフレームの底部プレートに結合された、ドレ
イン接続を画定する底部表面と、ソースを画定する第1
の金属化領域、およびゲートを画定する第2の金属化領
域がその上に配置された上部表面とを有する半導体パワ
ーMOSFETダイ、 ソース接続を画定する前記第1の金属化領域の大部分に
結合され、その大部分に及ぶ、前記リードフレームから
セパレートされたディスクリート銅板、および前記第2
の端子が前記ソースに電気的に結合されるように前記銅
板部分を少なくとも1つの前記第2の端子に結合するよ
うにサイズを取られ成形された、少なくとも1つのビー
ム部分を含むパワー半導体パッケージ。 - 【請求項2】 前記ゲートを第3の端子に結合するワイ
ヤボンディングをさらに含む、請求項1に記載のパワー
半導体パッケージ。 - 【請求項3】 前記銅板部分が前記ソースに堅く結合さ
れるように前記銅板と前記第1の金属化領域との間に配
置された硬化性導電材料の層をさらに含む、請求項1に
記載のパワー半導体パッケージ。 - 【請求項4】 前記銅板が上部表面および底部表面を含
み、前記底部表面が前記ソースに向かって延びる下向き
の突起を有する、請求項1に記載のパワー半導体パッケ
ージ。 - 【請求項5】 前記MOSFETダイが、前記ソースの
一部分を覆って延びるゲートバスを含み、前記銅板がゲ
ートバスのほぼ全体を覆う、請求項1に記載のパワー半
導体パッケージ。 - 【請求項6】 前記MOSFETダイが、前記ソースの
一部分を覆って延びるゲートバスを含み、さらに前記ゲ
ートバスの少なくとも一部分を実質上覆う窒化物層を含
み、前記銅板が窒化物層によって前記ゲートバスから電
気的に絶縁された、請求項1に記載のパワー半導体パッ
ケージ。 - 【請求項7】 前記銅板と前記ソースの間に配置された
硬化性導電材料の層をさらに含む、請求項6に記載のパ
ワー半導体パッケージ。 - 【請求項8】 前記窒化物層が、前記ゲートバスを前記
硬化性導電材料から電気的に絶縁する、請求項7に記載
のパワー半導体パッケージ。 - 【請求項9】 前記硬化性導電材料が銀充填エポキシで
ある、請求項8に記載のパワー半導体パッケージ。 - 【請求項10】 少なくとも1つの前記ビーム部分が前
記銅板の側縁部から延び、その末端で少なくとも1つの
前記第2の端子に結合された、請求項1に記載のパワー
半導体パッケージ。 - 【請求項11】 前記ビーム部分と少なくとも1つの前
記第2の端子との間に配置された硬化性導電材料の層を
さらに含む、請求項10に記載のパワー半導体パッケー
ジ。 - 【請求項12】 少なくとも1つの前記第2の端子が少
なくとも1つの前記ビーム部分と一体化された、請求項
10に記載のパワー半導体パッケージ。 - 【請求項13】 前記ビーム部分が、前記銅板の側縁部
から少なくとも1つの前記第2の端子まで延びる単一部
材である、請求項10に記載のパワー半導体パッケー
ジ。 - 【請求項14】 前記銅板の側縁部から延びて少なくと
も1つの前記第2の端子で終端する少なくとも2つのビ
ーム部分を含む、請求項10に記載のパワー半導体パッ
ケージ。 - 【請求項15】 前記少なくとも2つのビーム部分が前
記銅板の側縁部からクロスバー部分まで延び、前記クロ
スバー部分が少なくとも2つの前記第2の端子に結合さ
れた、請求項14に記載のパワー半導体パッケージ。 - 【請求項16】 前記クロスバー部分を前記第2の端子
に結合するために配置された硬化性導電材料の層をさら
に含む、請求項15に記載のパワー半導体パッケージ。 - 【請求項17】 前記硬化性導電材料が銀充填エポキシ
である、請求項16に記載のパワー半導体パッケージ。 - 【請求項18】 前記クロスバー部分が、前記第2の端
子の付近に位置し、前記第2の端子との係合を容易にす
るようにサイズを取られ成形されたボイドを含む、請求
項15に記載のパワー半導体パッケージ。 - 【請求項19】 前記ボイドが、前記クロスバー部分の
ほぼ全長にわたって延びるチャネルの形をしている、請
求項18に記載のパワー半導体パッケージ。 - 【請求項20】 前記チャネル内に配置され前記クロス
バー部分を前記第2の端子に結合する硬化性導電材料を
さらに含む、請求項19に記載のパワー半導体パッケー
ジ。 - 【請求項21】 前記チャネルを通って前記第2の端子
に向かって延びる下向きの突起をさらに含む、請求項2
0に記載のパワー半導体パッケージ。 - 【請求項22】 前記突起が、前記クロスバー部分のほ
ぼ全長にわたって延びる壁面の形をしている、請求項2
1に記載のパワー半導体パッケージ。 - 【請求項23】 前記ボイド内に配置され前記クロスバ
ー部分を前記第2の端子に結合する硬化性導電材料をさ
らに含む、請求項22に記載のパワー半導体パッケー
ジ。 - 【請求項24】 前記硬化性導電材料が銀充填エポキシ
である、請求項23に記載のパワー半導体パッケージ。 - 【請求項25】 前記底部リードフレーム、前記半導体
ダイ、および前記銅板をほぼ封入するプラスチックハウ
ジングを含む、請求項1に記載のパワー半導体パッケー
ジ。 - 【請求項26】 底部プレート部分および前記底部プレ
ート部分から延びる少なくとも1つの第1の端子を有す
る底部リードフレームと、 前記第1の端子と同一平面上にある少なくとも1つの第
2の端子と、 ソースを画定する第1の金属化領域、およびゲートを画
定する第2の金属化領域がその上に配置された、前記ソ
ースの一部分を覆って延びるゲートバスをさらに含む上
部表面を有する半導体パワーMOSFETダイであっ
て、前記第1の端子がドレインに電気的に接続されるよ
うに前記リードフレームの底部プレートに結合された、
前記ドレイン接続を画定する底部表面をさらに含むMO
SFETダイと、 前記ゲートバスの少なくとも一部分を実質上覆う窒化物
層と、 前記窒化物層および前記ソースの上に配置された硬化性
導電材料の層と、 前記ソースの大部分に結合されてその大部分に及び、ゲ
ートバスのほぼ全体を覆う、前記リードフレームからセ
パレートされたディスクリート銅板と、 前記第2の端子が前記ソースに電気的に結合されるよう
に、前記銅板部分を少なくとも1つの前記第2の端子に
結合するようにサイズを取られ成形された少なくとも1
つのビーム部分と、 前記ゲートを第3の端子に結合するワイヤボンディング
とを含み、前記硬化性導電材料は、前記銅板を前記ソー
スに電気的に結合し、前記窒化物層によって前記ゲート
バスからは電気的に絶縁されるパワー半導体パッケー
ジ。 - 【請求項27】 前記硬化性導電材料が銀充填エポキシ
である、請求項26に記載のパワー半導体パッケージ。 - 【請求項28】 前記少なくとも1つのビーム部分が前
記銅板の側縁部から延び、その末端で少なくとも1つの
前記第2の端子に結合された、請求項26に記載のパワ
ー半導体パッケージ。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10181098P | 1998-09-25 | 1998-09-25 | |
US09/225,153 | 1999-01-04 | ||
US09/225,153 US6040626A (en) | 1998-09-25 | 1999-01-04 | Semiconductor package |
US60/101,810 | 1999-01-04 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2000114445A JP2000114445A (ja) | 2000-04-21 |
JP3240292B2 true JP3240292B2 (ja) | 2001-12-17 |
Family
ID=26798655
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP27342499A Expired - Fee Related JP3240292B2 (ja) | 1998-09-25 | 1999-09-27 | 半導体パッケージ |
Country Status (3)
Country | Link |
---|---|
US (1) | US6040626A (ja) |
JP (1) | JP3240292B2 (ja) |
TW (1) | TW425682B (ja) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
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US7138673B2 (en) | 2002-08-19 | 2006-11-21 | Nec Electronics Corporation | Semiconductor package having encapsulated chip attached to a mounting plate |
JP2009071033A (ja) * | 2007-09-13 | 2009-04-02 | Toshiba Corp | 半導体装置及びその製造方法 |
US7656034B2 (en) | 2007-09-14 | 2010-02-02 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
DE102014223863B4 (de) | 2014-04-22 | 2022-10-13 | Mitsubishi Electric Corporation | Leistungshalbleitereinrichtungen |
Families Citing this family (150)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6249041B1 (en) | 1998-06-02 | 2001-06-19 | Siliconix Incorporated | IC chip package with directly connected leads |
US6143981A (en) | 1998-06-24 | 2000-11-07 | Amkor Technology, Inc. | Plastic integrated circuit package and method and leadframe for making the package |
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US6246587B1 (en) * | 1998-12-03 | 2001-06-12 | Intermedics Inc. | Surface mounted device with grooves on a termination lead and methods of assembly |
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US6307755B1 (en) | 1999-05-27 | 2001-10-23 | Richard K. Williams | Surface mount semiconductor package, die-leadframe combination and leadframe therefor and method of mounting leadframes to surfaces of semiconductor die |
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US6521982B1 (en) | 2000-06-02 | 2003-02-18 | Amkor Technology, Inc. | Packaging high power integrated circuit devices |
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US6762067B1 (en) * | 2000-01-18 | 2004-07-13 | Fairchild Semiconductor Corporation | Method of packaging a plurality of devices utilizing a plurality of lead frames coupled together by rails |
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US6870254B1 (en) * | 2000-04-13 | 2005-03-22 | Fairchild Semiconductor Corporation | Flip clip attach and copper clip attach on MOSFET device |
US7042068B2 (en) | 2000-04-27 | 2006-05-09 | Amkor Technology, Inc. | Leadframe and semiconductor package made using the leadframe |
TW451392B (en) * | 2000-05-18 | 2001-08-21 | Siliconix Taiwan Ltd | Leadframe connecting method of power transistor |
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JP4102012B2 (ja) * | 2000-09-21 | 2008-06-18 | 株式会社東芝 | 半導体装置の製造方法および半導体装置 |
US6525372B2 (en) | 2000-11-16 | 2003-02-25 | Silicon Wireless Corporation | Vertical power devices having insulated source electrodes in discontinuous deep trenches |
US6566164B1 (en) | 2000-12-07 | 2003-05-20 | Amkor Technology, Inc. | Exposed copper strap in a semiconductor package |
JP3512078B2 (ja) | 2000-12-26 | 2004-03-29 | 関西日本電気株式会社 | 半導体装置の製造方法 |
JP3563387B2 (ja) | 2001-01-23 | 2004-09-08 | Necエレクトロニクス株式会社 | 半導体装置用導電性硬化樹脂及び半導体装置 |
US6777786B2 (en) * | 2001-03-12 | 2004-08-17 | Fairchild Semiconductor Corporation | Semiconductor device including stacked dies mounted on a leadframe |
US6545345B1 (en) | 2001-03-20 | 2003-04-08 | Amkor Technology, Inc. | Mounting for a package containing a chip |
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US6469398B1 (en) | 2001-03-29 | 2002-10-22 | Kabushiki Kaisha Toshiba | Semiconductor package and manufacturing method thereof |
US6597059B1 (en) | 2001-04-04 | 2003-07-22 | Amkor Technology, Inc. | Thermally enhanced chip scale lead on chip semiconductor package |
US6756658B1 (en) | 2001-04-06 | 2004-06-29 | Amkor Technology, Inc. | Making two lead surface mounting high power microleadframe semiconductor packages |
JP4112816B2 (ja) * | 2001-04-18 | 2008-07-02 | 株式会社東芝 | 半導体装置および半導体装置の製造方法 |
US7057273B2 (en) * | 2001-05-15 | 2006-06-06 | Gem Services, Inc. | Surface mount package |
EP1271648A1 (en) * | 2001-06-22 | 2003-01-02 | Siliconx (Taiwan) Ltd | Power semiconductor package and method for making the same |
US6528880B1 (en) * | 2001-06-25 | 2003-03-04 | Lovoltech Inc. | Semiconductor package for power JFET having copper plate for source and ribbon contact for gate |
ITMI20012284A1 (it) * | 2001-10-30 | 2003-04-30 | St Microelectronics Srl | Metodo per il perfezionamento della connessione elettrica tra un dispositivo elettronico di potenza ed il suo package |
US6630726B1 (en) | 2001-11-07 | 2003-10-07 | Amkor Technology, Inc. | Power semiconductor package with strap |
US6737750B1 (en) | 2001-12-07 | 2004-05-18 | Amkor Technology, Inc. | Structures for improving heat dissipation in stacked semiconductor packages |
US6765292B2 (en) * | 2001-12-10 | 2004-07-20 | International Rectifier Corporation | Contact structure for semiconductor device |
US6608366B1 (en) | 2002-04-15 | 2003-08-19 | Harry J. Fogelson | Lead frame with plated end leads |
DE10221085B4 (de) * | 2002-05-11 | 2012-07-26 | Robert Bosch Gmbh | Baugruppe mit einer Verbindungseinrichtung zum Kontaktieren eines Halbleiter-Bauelements und Herstellungsverfahren |
JP3637330B2 (ja) * | 2002-05-16 | 2005-04-13 | 株式会社東芝 | 半導体装置 |
JP3942500B2 (ja) | 2002-07-02 | 2007-07-11 | Necエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP2004111885A (ja) | 2002-07-23 | 2004-04-08 | Toshiba Corp | 半導体装置 |
US6747342B1 (en) * | 2002-08-09 | 2004-06-08 | Lovoltech, Inc. | Flip-chip packaging |
US20040080028A1 (en) * | 2002-09-05 | 2004-04-29 | Kabushiki Kaisha Toshiba | Semiconductor device with semiconductor chip mounted in package |
US6818973B1 (en) | 2002-09-09 | 2004-11-16 | Amkor Technology, Inc. | Exposed lead QFP package fabricated through the use of a partial saw process |
JP2004111745A (ja) * | 2002-09-19 | 2004-04-08 | Toshiba Corp | 半導体装置 |
US7723210B2 (en) | 2002-11-08 | 2010-05-25 | Amkor Technology, Inc. | Direct-write wafer level chip scale package |
US6905914B1 (en) | 2002-11-08 | 2005-06-14 | Amkor Technology, Inc. | Wafer level package and fabrication method |
US6798047B1 (en) | 2002-12-26 | 2004-09-28 | Amkor Technology, Inc. | Pre-molded leadframe |
DE10301091B4 (de) * | 2003-01-14 | 2015-01-22 | Infineon Technologies Ag | Leistungs-Halbleiterbauelement und Verfahren zur Verbindung von einem gemeinsamen Substratträger zugeordneten Halbleitereinrichtungen |
DE10303463B4 (de) * | 2003-01-29 | 2006-06-14 | Infineon Technologies Ag | Halbleiterbauelement mit wenigstens zwei in einem Gehäuse integrierten und durch einen gemeinsamen Kontaktbügel kontaktierten Chips |
US6750545B1 (en) | 2003-02-28 | 2004-06-15 | Amkor Technology, Inc. | Semiconductor package capable of die stacking |
US6794740B1 (en) | 2003-03-13 | 2004-09-21 | Amkor Technology, Inc. | Leadframe package for semiconductor devices |
US20040217488A1 (en) * | 2003-05-02 | 2004-11-04 | Luechinger Christoph B. | Ribbon bonding |
JP4248953B2 (ja) | 2003-06-30 | 2009-04-02 | 株式会社ルネサステクノロジ | 半導体装置およびその製造方法 |
JP4239723B2 (ja) * | 2003-07-24 | 2009-03-18 | トヨタ自動車株式会社 | 発電電動装置を備える駆動システムおよび発電電動装置の制御をコンピュータに実行させるためのプログラムを記録したコンピュータ読取り可能な記録媒体 |
DE10349477A1 (de) * | 2003-10-21 | 2005-02-24 | Infineon Technologies Ag | Halbleiterbauteile mit einem Gehäuse und mit einem Halbleiterchip, sowie Verfahren zur Herstellung desselben |
JP3809168B2 (ja) * | 2004-02-03 | 2006-08-16 | 株式会社東芝 | 半導体モジュール |
JP4489485B2 (ja) | 2004-03-31 | 2010-06-23 | 株式会社ルネサステクノロジ | 半導体装置 |
DE102004041088B4 (de) * | 2004-08-24 | 2009-07-02 | Infineon Technologies Ag | Halbleiterbauteil in Flachleitertechnik mit einem Halbleiterchip und Verfahren zu seiner Herstellung |
US7135761B2 (en) * | 2004-09-16 | 2006-11-14 | Semiconductor Components Industries, L.Lc | Robust power semiconductor package |
US20060145319A1 (en) * | 2004-12-31 | 2006-07-06 | Ming Sun | Flip chip contact (FCC) power package |
DE102005009163B4 (de) * | 2005-02-25 | 2013-08-14 | Infineon Technologies Ag | Halbleiterbauteil mit einem Halbleiterchip, der Signalkontaktflächen und Versorgungskontaktflächen aufweist, sowie Verfahren zur Herstellung des Halbleiterbauteils |
DE102005011159B4 (de) * | 2005-03-09 | 2013-05-16 | Infineon Technologies Ag | Halbleiterbauteil mit oberflächenmontierbaren Außenkontaktflächen und Verfahren zur Herstellung desselben |
DE102005027356B4 (de) * | 2005-06-13 | 2007-11-22 | Infineon Technologies Ag | Halbleiterleistungsbauteilstapel in Flachleitertechnik mit oberflächenmontierbaren Außenkontakten und ein Verfahren zur Herstellung desselben |
US7504733B2 (en) * | 2005-08-17 | 2009-03-17 | Ciclon Semiconductor Device Corp. | Semiconductor die package |
US7683464B2 (en) * | 2005-09-13 | 2010-03-23 | Alpha And Omega Semiconductor Incorporated | Semiconductor package having dimpled plate interconnections |
US7622796B2 (en) * | 2005-09-13 | 2009-11-24 | Alpha And Omega Semiconductor Limited | Semiconductor package having a bridged plate interconnection |
US20070057368A1 (en) * | 2005-09-13 | 2007-03-15 | Yueh-Se Ho | Semiconductor package having plate interconnections |
JP4764692B2 (ja) * | 2005-09-29 | 2011-09-07 | 日立オートモティブシステムズ株式会社 | 半導体モジュール |
US20070075406A1 (en) * | 2005-09-30 | 2007-04-05 | Yueh-Se Ho | Wafer-level method for metallizing source, gate and drain contact areas of semiconductor die |
DE102005049687B4 (de) * | 2005-10-14 | 2008-09-25 | Infineon Technologies Ag | Leistungshalbleiterbauteil in Flachleitertechnik mit vertikalem Strompfad und Verfahren zur Herstellung |
US7560808B2 (en) * | 2005-10-19 | 2009-07-14 | Texas Instruments Incorporated | Chip scale power LDMOS device |
US7285849B2 (en) * | 2005-11-18 | 2007-10-23 | Fairchild Semiconductor Corporation | Semiconductor die package using leadframe and clip and method of manufacturing |
US7572681B1 (en) | 2005-12-08 | 2009-08-11 | Amkor Technology, Inc. | Embedded electronic component package |
US7582958B2 (en) * | 2005-12-08 | 2009-09-01 | International Rectifier Corporation | Semiconductor package |
US20090057852A1 (en) * | 2007-08-27 | 2009-03-05 | Madrid Ruben P | Thermally enhanced thin semiconductor package |
US7371616B2 (en) * | 2006-01-05 | 2008-05-13 | Fairchild Semiconductor Corporation | Clipless and wireless semiconductor die package and method for making the same |
JP5152619B2 (ja) * | 2006-02-09 | 2013-02-27 | ダイヤモンド電機株式会社 | 半導体モジュール及びこれを備える半導体装置、並びに、半導体モジュールの製造方法 |
US7446375B2 (en) * | 2006-03-14 | 2008-11-04 | Ciclon Semiconductor Device Corp. | Quasi-vertical LDMOS device having closed cell layout |
DE102006015447B4 (de) * | 2006-03-31 | 2012-08-16 | Infineon Technologies Ag | Leistungshalbleiterbauelement mit einem Leistungshalbleiterchip und Verfahren zur Herstellung desselben |
DE102006017668B4 (de) * | 2006-04-12 | 2016-06-02 | Infineon Technologies Ag | Verfahren zur Herstellung von Leistungshalbleiterbauteilen mit Verwendung von Farbstoffen |
US20090272577A1 (en) * | 2006-04-27 | 2009-11-05 | Neomax Materials Co., Ltd. | Clad material for wiring connection and wiring connection member processed from the clad material |
US7812437B2 (en) * | 2006-05-19 | 2010-10-12 | Fairchild Semiconductor Corporation | Flip chip MLP with folded heat sink |
US7902660B1 (en) | 2006-05-24 | 2011-03-08 | Amkor Technology, Inc. | Substrate for semiconductor device and manufacturing method thereof |
DE102006025959B4 (de) * | 2006-06-02 | 2010-03-04 | Infineon Technologies Ag | Leistungshalbleiteranordnung mit vorderseitig aufgelötetem Clip und Verfahren zur Herstellung einer solchen |
US7968998B1 (en) | 2006-06-21 | 2011-06-28 | Amkor Technology, Inc. | Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package |
JP5165214B2 (ja) * | 2006-06-26 | 2013-03-21 | オンセミコンダクター・トレーディング・リミテッド | 半導体装置 |
US20080036078A1 (en) * | 2006-08-14 | 2008-02-14 | Ciclon Semiconductor Device Corp. | Wirebond-less semiconductor package |
JP2008078561A (ja) * | 2006-09-25 | 2008-04-03 | Toshiba Corp | 半導体装置及びその製造方法 |
DE102006060484B4 (de) * | 2006-12-19 | 2012-03-08 | Infineon Technologies Ag | Halbleiterbauelement mit einem Halbleiterchip und Verfahren zur Herstellung desselben |
US7705436B2 (en) * | 2007-08-06 | 2010-04-27 | Infineon Technologies Ag | Semiconductor device with semiconductor chip and method for producing it |
US7821111B2 (en) * | 2007-10-05 | 2010-10-26 | Texas Instruments Incorporated | Semiconductor device having grooved leads to confine solder wicking |
US7586179B2 (en) * | 2007-10-09 | 2009-09-08 | Fairchild Semiconductor Corporation | Wireless semiconductor package for efficient heat dissipation |
US10256385B2 (en) | 2007-10-31 | 2019-04-09 | Cree, Inc. | Light emitting die (LED) packages and related methods |
US8264084B2 (en) * | 2007-10-31 | 2012-09-11 | Alpha & Omega Semiconductor, Inc. | Solder-top enhanced semiconductor device for low parasitic impedance packaging |
US20090179315A1 (en) * | 2008-01-14 | 2009-07-16 | Armand Vincent Jereza | Semiconductor Die Packages Having Solder-free Connections, Systems Using the Same, and Methods of Making the Same |
US7843048B2 (en) | 2008-05-05 | 2010-11-30 | Fairchild Semiconductor Corporation | Multi-chip discrete devices in semiconductor packages |
US8680658B2 (en) * | 2008-05-30 | 2014-03-25 | Alpha And Omega Semiconductor Incorporated | Conductive clip for semiconductor device package |
JP5107839B2 (ja) | 2008-09-10 | 2012-12-26 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP5164793B2 (ja) * | 2008-11-04 | 2013-03-21 | 三菱電機株式会社 | 電力用半導体装置 |
US8680656B1 (en) | 2009-01-05 | 2014-03-25 | Amkor Technology, Inc. | Leadframe structure for concentrated photovoltaic receiver package |
US8049312B2 (en) * | 2009-01-12 | 2011-11-01 | Texas Instruments Incorporated | Semiconductor device package and method of assembly thereof |
US8022558B2 (en) * | 2009-02-13 | 2011-09-20 | Infineon Technologies Ag | Semiconductor package with ribbon with metal layers |
US8796837B2 (en) | 2009-03-03 | 2014-08-05 | Ixys Corporation | Lead and lead frame for power package |
JP4865829B2 (ja) * | 2009-03-31 | 2012-02-01 | シャープ株式会社 | 半導体装置およびその製造方法 |
US20100289129A1 (en) * | 2009-05-14 | 2010-11-18 | Satya Chinnusamy | Copper plate bonding for high performance semiconductor packaging |
US8866004B1 (en) | 2009-06-09 | 2014-10-21 | Amkor Technology, Inc. | Frame interconnect for concentrated photovoltaic module |
US8796561B1 (en) | 2009-10-05 | 2014-08-05 | Amkor Technology, Inc. | Fan out build up substrate stackable package and method |
US8076183B2 (en) * | 2009-10-27 | 2011-12-13 | Alpha And Omega Semiconductor, Inc. | Method of attaching an interconnection plate to a semiconductor die within a leadframe package |
US8937381B1 (en) | 2009-12-03 | 2015-01-20 | Amkor Technology, Inc. | Thin stackable package and method |
US9691734B1 (en) | 2009-12-07 | 2017-06-27 | Amkor Technology, Inc. | Method of forming a plurality of electronic component packages |
JP5473733B2 (ja) * | 2010-04-02 | 2014-04-16 | 株式会社日立製作所 | パワー半導体モジュール |
US8324511B1 (en) | 2010-04-06 | 2012-12-04 | Amkor Technology, Inc. | Through via nub reveal method and structure |
US8294276B1 (en) | 2010-05-27 | 2012-10-23 | Amkor Technology, Inc. | Semiconductor device and fabricating method thereof |
US9362437B1 (en) | 2010-06-14 | 2016-06-07 | Amkor Technology, Inc. | Concentrated photovoltaic receiver module with improved optical light guide assembly |
KR101101018B1 (ko) * | 2010-06-21 | 2011-12-29 | 김재구 | 리드선이 개량된 다이오드 패키지 및 그 제조방법 |
US8809677B1 (en) | 2010-07-02 | 2014-08-19 | Amkor Technology, Inc. | Molded light guide for concentrated photovoltaic receiver module |
US8440554B1 (en) | 2010-08-02 | 2013-05-14 | Amkor Technology, Inc. | Through via connected backside embedded circuit features structure and method |
JP5819052B2 (ja) * | 2010-09-09 | 2015-11-18 | ローム株式会社 | 半導体装置および半導体装置の製造方法 |
US8552517B1 (en) | 2010-09-14 | 2013-10-08 | Amkor Technology, Inc. | Conductive paste and mold for electrical connection of photovoltaic die to substrate |
US8487445B1 (en) | 2010-10-05 | 2013-07-16 | Amkor Technology, Inc. | Semiconductor device having through electrodes protruding from dielectric layer |
JP2012109455A (ja) * | 2010-11-18 | 2012-06-07 | Fujitsu Semiconductor Ltd | 半導体装置及びその製造方法 |
US8791501B1 (en) | 2010-12-03 | 2014-07-29 | Amkor Technology, Inc. | Integrated passive device structure and method |
US8502361B1 (en) | 2010-12-09 | 2013-08-06 | Amkor Technology, Inc. | Concentrated photovoltaic receiver package with stacked internal support features |
US8390130B1 (en) | 2011-01-06 | 2013-03-05 | Amkor Technology, Inc. | Through via recessed reveal structure and method |
DE202011100820U1 (de) * | 2011-05-17 | 2011-12-01 | Ixys Semiconductor Gmbh | Leistungshalbleiter |
US8941962B2 (en) | 2011-09-13 | 2015-01-27 | Fsp Technology Inc. | Snubber circuit and method of using bipolar junction transistor in snubber circuit |
US8552548B1 (en) | 2011-11-29 | 2013-10-08 | Amkor Technology, Inc. | Conductive pad on protruding through electrode semiconductor device |
CN102437134B (zh) * | 2011-12-07 | 2013-09-11 | 上海凯虹电子有限公司 | 一种超小型封装体及其制作方法 |
US20130175704A1 (en) * | 2012-01-05 | 2013-07-11 | Ixys Corporation | Discrete power transistor package having solderless dbc to leadframe attach |
US8883567B2 (en) * | 2012-03-27 | 2014-11-11 | Texas Instruments Incorporated | Process of making a stacked semiconductor package having a clip |
US9129943B1 (en) | 2012-03-29 | 2015-09-08 | Amkor Technology, Inc. | Embedded component package and fabrication method |
US9048298B1 (en) | 2012-03-29 | 2015-06-02 | Amkor Technology, Inc. | Backside warpage control structure and fabrication method |
JP2012235164A (ja) * | 2012-08-20 | 2012-11-29 | Renesas Electronics Corp | 半導体装置 |
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Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4189342A (en) * | 1971-10-07 | 1980-02-19 | U.S. Philips Corporation | Semiconductor device comprising projecting contact layers |
US4935803A (en) * | 1988-09-09 | 1990-06-19 | Motorola, Inc. | Self-centering electrode for power devices |
US5266834A (en) * | 1989-03-13 | 1993-11-30 | Hitachi Ltd. | Semiconductor device and an electronic device with the semiconductor devices mounted thereon |
JPH0671062B2 (ja) * | 1989-08-30 | 1994-09-07 | 株式会社東芝 | 樹脂封止型半導体装置 |
US5767546A (en) * | 1994-12-30 | 1998-06-16 | Siliconix Incorporated | Laternal power mosfet having metal strap layer to reduce distributed resistance |
US5665996A (en) * | 1994-12-30 | 1997-09-09 | Siliconix Incorporated | Vertical power mosfet having thick metal layer to reduce distributed resistance |
US5814884C1 (en) * | 1996-10-24 | 2002-01-29 | Int Rectifier Corp | Commonly housed diverse semiconductor die |
-
1999
- 1999-01-04 US US09/225,153 patent/US6040626A/en not_active Expired - Lifetime
- 1999-09-23 TW TW088116356A patent/TW425682B/zh not_active IP Right Cessation
- 1999-09-27 JP JP27342499A patent/JP3240292B2/ja not_active Expired - Fee Related
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
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US7449370B2 (en) | 2002-08-19 | 2008-11-11 | Nec Electronics Corporation | Production process for manufacturing such semiconductor package |
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US7656034B2 (en) | 2007-09-14 | 2010-02-02 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
DE102014223863B4 (de) | 2014-04-22 | 2022-10-13 | Mitsubishi Electric Corporation | Leistungshalbleitereinrichtungen |
Also Published As
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TW425682B (en) | 2001-03-11 |
JP2000114445A (ja) | 2000-04-21 |
US6040626A (en) | 2000-03-21 |
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