JP3226657B2 - ΔΣ modulator - Google Patents
ΔΣ modulatorInfo
- Publication number
- JP3226657B2 JP3226657B2 JP08451093A JP8451093A JP3226657B2 JP 3226657 B2 JP3226657 B2 JP 3226657B2 JP 08451093 A JP08451093 A JP 08451093A JP 8451093 A JP8451093 A JP 8451093A JP 3226657 B2 JP3226657 B2 JP 3226657B2
- Authority
- JP
- Japan
- Prior art keywords
- modulator
- output
- signal
- integrator
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- Analogue/Digital Conversion (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Description
【0001】[0001]
【産業上の利用分野】本発明はAD(アナログデジタ
ル)変換器に用いられるΔΣモジュレータ(デジタルシ
グマ変調器)に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a .DELTA..SIGMA. Modulator (digital sigma modulator) used for an AD (analog-digital) converter.
【0002】[0002]
【従来の技術】オーバサンプリング方式の一つであるΔ
Σ変調方式でAD変換を行う従来のΔΣ型AD変換器の
基本構成を図1に示す。ΔΣモジュレータ10は一般
に、アナログ入力信号を積分する積分器、積分器の出力
を量子化する量子化器、および量子化器から出力する量
子化信号を極性を反転して上記アナログ入力信号に加算
する加算器を有する。ΔΣモジュレータ10から出力す
る量子化信号はデジタルフィルタ20によりAD変換出
力として、上記アナログ入力信号に対応するデジタル信
号に変換される。2. Description of the Related Art One of the oversampling methods, Δ
FIG. 1 shows a basic configuration of a conventional ΔΣ AD converter that performs AD conversion by Σ modulation. The ΔΣ modulator 10 generally includes an integrator for integrating an analog input signal, a quantizer for quantizing an output of the integrator, and a quantized signal output from the quantizer with its polarity inverted and added to the analog input signal. It has an adder. The quantized signal output from the ΔΣ modulator 10 is converted as an AD conversion output by the digital filter 20 into a digital signal corresponding to the analog input signal.
【0003】一定電源電圧下で動作するΔΣ型AD変換
器は、絶対値が大きな過大信号入力に対してΔΣモジュ
レータ10の内部の積分器出力である状態変数値が発振
(振幅増大現象)を起し、変換の線形性が失われたり、
SN比(信号対雑音比)の低下が発生したり、また入力
が正常動作範囲に復帰後も発振を継続してしまうことが
ある。さらにまた、AC(交流)信号をAD変換するた
めのAD変換器では、できるだけ大きなAC信号入力に
対応することが必要という観点からも、入力信号のオフ
セットを取り除くことが好ましい。In a ΔΣ AD converter operating under a constant power supply voltage, a state variable value which is an integrator output inside the ΔΣ modulator 10 oscillates (amplitude increase phenomenon) in response to an excessive signal input having a large absolute value. And the linearity of the transformation is lost,
The SN ratio (signal-to-noise ratio) may decrease, or oscillation may continue even after the input returns to the normal operation range. Furthermore, in an AD converter for AD-converting an AC (alternating current) signal, it is preferable to remove the offset of the input signal from the viewpoint that it is necessary to support an AC signal input as large as possible.
【0004】図2はオフセットを取り除くための従来の
回路構成例を示す。この入力信号のオフセットの取り除
きは入力信号をΔΣモジュレータ10に入れる前にハイ
パスフィルタ30を通すことで行っている。この場合に
は、ΔΣモジュレータ10の出力(y)は、入力(x)
に対してそのオフセット分が取り除かれたもの(x′)
とΔΣモジュレータ10自身が発生するオフセット(O
S)との和、すなわちFIG. 2 shows an example of a conventional circuit configuration for removing an offset. The removal of the offset of the input signal is performed by passing the input signal through a high-pass filter 30 before entering the ΔΣ modulator 10. In this case, the output (y) of the ΔΣ modulator 10 becomes the input (x)
(X ') from which the offset is removed
And the offset (O) generated by the ΔΣ modulator 10 itself.
S), that is,
【0005】[0005]
【数1】 y=x′+OS …(1) となる。ただし、ここではΔΣモジュレータ10によっ
てノイズシェーピングされたノイズでの高域の成分は考
えていない。Y = x ′ + OS (1) However, here, a high-frequency component in noise that has been noise-shaped by the ΔΣ modulator 10 is not considered.
【0006】[0006]
【発明が解決しようとする課題】従来のΔΣ型AD変換
器では、上述のようにΔΣモジュレータ自身が発生する
オフセットがそのΔΣモジュレータの出力に加算される
という問題があった。The conventional ΔΣ AD converter has a problem that the offset generated by the ΔΣ modulator itself is added to the output of the ΔΣ modulator as described above.
【0007】そこで、本発明の目的は、上述の点に鑑み
て、入力信号のオフセットのみならず、ΔΣモジュレー
タ自身が発生するオフセットも取り除けるΔΣモジュレ
ータを提供することにある。In view of the above, an object of the present invention is to provide a ΔΣ modulator that can remove not only an offset of an input signal but also an offset generated by the ΔΣ modulator itself.
【0008】[0008]
【課題を解決するための手段】上記目的を達成するた
め、本発明は、アナログ入力信号を積分する第1の積分
手段と、該第1の積分手段の出力を量子化する量子化手
段と、該量子化手段の出力を極性を反転して前記アナロ
グ入力信号に加算する第1の加算手段と、前記量子化手
段の出力を積分する第2の積分手段と、該第2の積分手
段の出力を極性を反転して前記アナログ入力信号に加算
する第2の加算手段とを具備することを特徴とする。In order to achieve the above object, the present invention provides a first integrating means for integrating an analog input signal, a quantizing means for quantizing an output of the first integrating means, First adding means for inverting the polarity of the output of the quantizing means and adding the result to the analog input signal, second integrating means for integrating the output of the quantizing means, and output of the second integrating means And a second adding means for inverting the polarity of the signal and adding the inverted signal to the analog input signal.
【0009】[0009]
【作用】以下に図面を参照して本発明の作用を詳述す
る。図3は本発明の基本構成を示す。図3において、1
00は前述の従来のΔΣモジュレータ10と同様の構成
の回路部分であり、アナログ入力信号を積分する第1積
分器11,第1の積分器11の出力を量子化する量子化
器12,量子化器12の出力を第1のリファレンス信号
(VREF1)を参照してアナログ信号に変換する第1
のDA(デジタルアナログ)変換器13および第1のD
A変換器13の出力を上記アナログ入力信号に加算する
(極性は負)第1の加算器14を有する。41は量子化
器12の出力を第2のリファレンス信号(VREF2)
を参照してアナログ信号に変換する第2のDA変換器、
42は第2のDA変換器41の出力を積分する第2の積
分器、および43は第2の積分器42の出力を上記アナ
ログ入力信号に加算する(極性は負)第2の加算器であ
る。このように、本発明のΔΣモジュレータは、上記従
来例と同様の回路部分100にDA変換器41,第2の
積分器42および第2の加算器43とが追加されて構成
される。The operation of the present invention will be described below in detail with reference to the drawings. FIG. 3 shows a basic configuration of the present invention. In FIG. 3, 1
Reference numeral 00 denotes a circuit portion having a configuration similar to that of the above-described conventional Δ 前述 modulator 10, a first integrator 11 for integrating an analog input signal, a quantizer 12 for quantizing an output of the first integrator 11, and a quantizer 12. A first converter for converting an output of the detector 12 into an analog signal with reference to a first reference signal (VREF1)
(Digital / analog) converter 13 and the first D
It has a first adder 14 that adds the output of the A converter 13 to the analog input signal (the polarity is negative). Reference numeral 41 denotes an output of the quantizer 12 as a second reference signal (VREF2).
A second DA converter that converts the analog signal into an analog signal with reference to
42 is a second integrator that integrates the output of the second DA converter 41, and 43 is a second adder that adds the output of the second integrator 42 to the analog input signal (negative polarity). is there. As described above, the ΔΣ modulator of the present invention is configured by adding the DA converter 41, the second integrator 42, and the second adder 43 to the circuit portion 100 similar to the above-described conventional example.
【0010】上記基本構成における信号の入出力関係を
図4に示す。yはΔΣモジュレータからの出力である。
OSはΔΣモジュレータの入力ノイズでオフセット以外
の色々な周波数を含んでいる。ただし、高周波成分は考
えない。また積分器において高周波成分の積分値はゼロ
となると仮定する。図4から次式(2)が成立する。FIG. 4 shows the input / output relationship of signals in the above basic configuration. y is the output from the ΔΣ modulator.
The OS includes various frequencies other than the offset in the input noise of the ΔΣ modulator. However, high frequency components are not considered. It is also assumed that the integrated value of the high-frequency component in the integrator becomes zero. The following equation (2) is established from FIG.
【0011】[0011]
【数2】 (Equation 2)
【0012】上式(2)において、S(=jω)≒0、
つまり低周波成分のとき、In the above equation (2), S (= jω) ≒ 0,
In other words, for low frequency components,
【0013】[0013]
【数3】 (Equation 3)
【0014】となる。## EQU1 ##
【0015】従って、直流成分に近い信号のときy≒0
となる。xは入力信号(交流)とオフセット、OSは直
流成分が主であるから、上式(2)ではxのオフセット
と、OSとが≒0となり、xの信号成分のみが出力され
る。このように、入力信号(x)も低周波成分が除去さ
れ、ΔΣモジュレータのオフセット(OS)も同様に低
周波成分が除去され、ΔΣモジュレータの出力yはxの
信号成分のみとなる。Therefore, when the signal is close to the DC component, y ≒ 0
Becomes Since x is an input signal (alternating current) and an offset, and OS is mainly a DC component, the offset of x and OS become ≒ 0 in the above equation (2), and only the signal component of x is output. As described above, the low frequency component is also removed from the input signal (x), the low frequency component is similarly removed from the offset (OS) of the ΔΣ modulator, and the output y of the ΔΣ modulator becomes only the x signal component.
【0016】[0016]
【実施例】以下、図面を参照して本発明の実施例を詳細
に説明する。Embodiments of the present invention will be described below in detail with reference to the drawings.
【0017】(第1実施例)図5は本発明の一実施例の
ΔΣモジュレータの回路構成を示す。本例のΔΣモジュ
レータはCMOSプロセスによるLSI(大規模集積回
路)として実現され、その各スイッチはMOSトランジ
スタによるトランスファゲートでできている。図中のS
1,S2は各スイッチに印加される切換信号を表わす。
本例のΔΣモジュレータは、スイッチドキャパシタ回路
(以下、SC回路と略称する)による2次のΔΣモジュ
レータ回路部分111〜115と、その出力により極性
をコントロールされ第2のリファレンス信号(VREF
2)を積分するSC回路117付の積分器(118)
と、その積分器出力を入力部の信号へ加算(極性は負)
するSC回路119から成る。(First Embodiment) FIG. 5 shows a circuit configuration of a ΔΣ modulator according to an embodiment of the present invention. The .DELTA..SIGMA. Modulator of this example is realized as an LSI (Large Scale Integrated Circuit) using a CMOS process, and each switch is made of a transfer gate using a MOS transistor. S in the figure
1 and S2 represent switching signals applied to each switch.
The ΔΣ modulator of this example is composed of a second-order ΔΣ modulator circuit portions 111 to 115 formed by a switched capacitor circuit (hereinafter abbreviated as an SC circuit) and a second reference signal (VREF) whose polarity is controlled by its output.
2) Integrator with SC circuit 117 for integrating (118)
And its integrator output to the input signal (negative polarity)
The SC circuit 119 performs the following.
【0018】SC回路111,113はそれぞれ抵抗器
と等価であり、演算増幅器112,114とキャパシタ
C5,C8 とで図3の第1の積分器11を構成する。11
5は図3の量子化器12を構成する比較器であり、入力
クロック信号をノードa点の積分器出力でゲートして
“1”,“0”の2値の量子化信号を発生する。SC回
路116は図3の第1のDA変換器13と第1の加算器
14に相当する。SC回路117,演算増幅器118お
よびキャパシタC10とで図3の第2のDA変換器41と
第2の積分器42を構成する。SC回路119は図3の
第2の加算器43に相当する。The SC circuit 111 and 113 are equivalent to each resistor constituting the first integrator 11 of FIG. 3 in the operational amplifier 112 and the capacitor C 5, C 8. 11
Reference numeral 5 denotes a comparator constituting the quantizer 12 of FIG. 3, which gates an input clock signal with an integrator output at a point a to generate a binary quantized signal of "1" and "0". The SC circuit 116 corresponds to the first DA converter 13 and the first adder 14 in FIG. SC circuit 117, constituting the operational amplifier 118 and capacitor C 10 in the second DA converter 41 in FIG. 3 the second integrator 42. The SC circuit 119 corresponds to the second adder 43 in FIG.
【0019】図6は図5の回路の信号のタイミングと波
形を示すタイミングチャートである。FIG. 6 is a timing chart showing signal timings and waveforms of the circuit of FIG.
【0020】本例の実験例では、ΔΣモジュレータの出
力周波数およびSC回路のスイッチの動作周波数をそれ
ぞれ512kHz、デジタルフィルタ出力時の出力レー
トを8kHzとし、入力およびΔΣモジュレータの低周
波数16Hzをカットオフとして減衰させるように構成
した。この結果、デジタルフィルタ出力が14ビット出
力である場合には、オフセットが検出不能となるところ
まで、オフセットを低減させることができることが確認
できた。In the experimental example of this embodiment, the output frequency of the ΔΣ modulator and the operating frequency of the switch of the SC circuit are each 512 kHz, the output rate at the time of outputting the digital filter is 8 kHz, and the low frequency of the input and the ΔΣ modulator is 16 Hz. It was configured to attenuate. As a result, when the digital filter output was a 14-bit output, it was confirmed that the offset could be reduced to a point where the offset could not be detected.
【0021】(第2実施例)図7は第2の積分器出力を
ΔΣモジュレータの入力部の信号に加算する(極性は
負)別の構成例を示す。本例では、アナログ入力信号を
ΔΣモジュレータに導入するためのSC回路111のキ
ャパシタC1 の左端を、入力信号と第2積分器出力間で
交互に接続するようになっており、これにより、(入力
信号−第2積分器出力)×C1 なる電荷をΔΣモジュレ
ータの第1積分器に入力する。(Second Embodiment) FIG. 7 shows another configuration example in which the output of the second integrator is added to the signal at the input of the ΔΣ modulator (the polarity is negative). In this example, the left end of the capacitor C 1 of the SC circuit 111 for introducing the analog input signal to the ΔΣ modulator is adapted to connect to alternate between the input signal and the second integrator output, thereby, ( An electric charge of (input signal−output of second integrator) × C 1 is input to the first integrator of the ΔΣ modulator.
【0022】本例は、図5の第1実施例に比べ、SC回
路119を構成しているキャパシタC4 とこれに接続さ
れたスイッチを合計4個削減することができる利点があ
る。This embodiment has an advantage that the total number of the capacitors C 4 constituting the SC circuit 119 and the switches connected thereto can be reduced by four as compared with the first embodiment of FIG.
【0023】(その他の実施態様)上述した本発明の実
施例において、ΔΣモジュレータや積分器の次数を増減
することも可能であり、各回路ブロックの一部や全部を
SC回路でない回路、例えば抵抗器やキャパシタなどの
受動部品で組み、時間軸連続な系とすることも可能であ
る。また、上述した本発明の実施例では電圧を入力およ
びΔΣモジュレータ内の各状態変数としているが、電流
や電荷を信号表現媒体とすることも可能である。また、
参照信号(電圧)のVREF1およびVREF2はそれ
ぞれ異なる値とすることも、共通の値とすることもでき
る。(Other Embodiments) In the above-described embodiment of the present invention, it is possible to increase or decrease the order of the ΔΣ modulator and the integrator. It is also possible to build a system with a continuous time axis by assembling with passive components such as a vessel and a capacitor. Further, in the above-described embodiment of the present invention, voltage is used as an input and each state variable in the Δ 、 modulator, but current and charge can be used as a signal expression medium. Also,
VREF1 and VREF2 of the reference signal (voltage) may have different values or a common value.
【0024】[0024]
【発明の効果】以上説明したように、本発明によれば、
ΔΣモジュレータの出力を積分器で積分した出力を極性
を反転してΔΣモジュレータの入力部の入力信号へ加算
するようにしたので、入力信号のオフセットのみならず
ΔΣモジュレータのオフセットも同時に取り除くことが
できるという効果が得られる。As described above, according to the present invention,
Since the output obtained by integrating the output of the ΔΣ modulator by the integrator is inverted and added to the input signal at the input section of the ΔΣ modulator, not only the offset of the input signal but also the offset of the ΔΣ modulator can be removed at the same time. The effect is obtained.
【図1】従来例のΔΣ型AD変換器の構成を示すブロッ
ク図である。FIG. 1 is a block diagram showing a configuration of a conventional ΔΣ AD converter.
【図2】他の従来例のΔΣ型AD変換器の構成を示すブ
ロック図である。FIG. 2 is a block diagram showing a configuration of another conventional ΔΣ AD converter.
【図3】本発明の基本構成を示すブロック図である。FIG. 3 is a block diagram showing a basic configuration of the present invention.
【図4】図3の信号の関係を示す図である。FIG. 4 is a diagram illustrating a relationship between signals in FIG. 3;
【図5】本発明の一実施例の回路構成を示す回路図であ
る。FIG. 5 is a circuit diagram showing a circuit configuration of an embodiment of the present invention.
【図6】図5の信号のタイミングと波形を示すタイミン
グチャートである。FIG. 6 is a timing chart showing timings and waveforms of the signals in FIG.
【図7】本発明の他の実施例の回路構成を示す回路図で
ある。FIG. 7 is a circuit diagram showing a circuit configuration of another embodiment of the present invention.
10 ΔΣモジュレータ 11 第1の積分器 12 量子化器 13 第1のDA変換器 14 第1の加算器 20 デジタルフィルタ 41 第2のDA変換器 42 第2の積分器 43 第2の加算器 100 従来と同様なΔΣモジュレータ回路部分 111,113,116,117,119 スイッチド
キャパシタ回路 112,114,118 演算増幅器 115 比較器Reference Signs List 10 ΔΣ modulator 11 First integrator 12 Quantizer 13 First DA converter 14 First adder 20 Digital filter 41 Second DA converter 42 Second integrator 43 Second adder 100 Conventional ΔΣ modulator circuit portion similar to 111, 113, 116, 117, 119 Switched capacitor circuit 112, 114, 118 Operational amplifier 115 Comparator
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H03M 3/02 H03M 1/10 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H03M 3/02 H03M 1/10
Claims (1)
手段と、 該第1の積分手段の出力を量子化する量子化手段と、 該量子化手段の出力を極性を反転して前記アナログ入力
信号に加算する第1の加算手段と、 前記量子化手段の出力を積分する第2の積分手段と、 該第2の積分手段の出力を極性を反転して前記アナログ
入力信号に加算する第2の加算手段とを具備することを
特徴とするΔΣモジュレータ。A first integration means for integrating an analog input signal; a quantization means for quantizing an output of the first integration means; a polarity inversion of an output of the quantization means; First adding means for adding to the signal; second integrating means for integrating the output of the quantizing means; and second means for inverting the polarity of the output of the second integrating means and adding the output to the analog input signal. .DELTA..SIGMA. Modulator comprising:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP08451093A JP3226657B2 (en) | 1993-04-12 | 1993-04-12 | ΔΣ modulator |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP08451093A JP3226657B2 (en) | 1993-04-12 | 1993-04-12 | ΔΣ modulator |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH06318872A JPH06318872A (en) | 1994-11-15 |
JP3226657B2 true JP3226657B2 (en) | 2001-11-05 |
Family
ID=13832646
Family Applications (1)
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---|---|---|---|
JP08451093A Expired - Lifetime JP3226657B2 (en) | 1993-04-12 | 1993-04-12 | ΔΣ modulator |
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JP (1) | JP3226657B2 (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002247683A (en) * | 2001-02-02 | 2002-08-30 | Techtronic As | Microphone with internal a/d converter |
US20020106091A1 (en) | 2001-02-02 | 2002-08-08 | Furst Claus Erdmann | Microphone unit with internal A/D converter |
WO2006085605A1 (en) | 2005-02-10 | 2006-08-17 | National University Corporation Nagoya University | Δς modulator and δς analog/digital converting circuit |
JP2008028855A (en) * | 2006-07-24 | 2008-02-07 | Renesas Technology Corp | Semiconductor integrated circuit device |
-
1993
- 1993-04-12 JP JP08451093A patent/JP3226657B2/en not_active Expired - Lifetime
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