JPH06318872A - Deltasigma modulator - Google Patents
Deltasigma modulatorInfo
- Publication number
- JPH06318872A JPH06318872A JP8451093A JP8451093A JPH06318872A JP H06318872 A JPH06318872 A JP H06318872A JP 8451093 A JP8451093 A JP 8451093A JP 8451093 A JP8451093 A JP 8451093A JP H06318872 A JPH06318872 A JP H06318872A
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- signal
- input signal
- converter
- Prior art date
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- Compression, Expansion, Code Conversion, And Decoders (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はＡＤ（アナログデジタ
ル）変換器に用いられるΔΣモジュレータ（デジタルシ
グマ変調器）に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ΔΣ modulator (digital sigma modulator) used in an AD (analog / digital) converter.
【０００２】[0002]
【従来の技術】オーバサンプリング方式の一つであるΔ
Σ変調方式でＡＤ変換を行う従来のΔΣ型ＡＤ変換器の
基本構成を図１に示す。ΔΣモジュレータ１０は一般
に、アナログ入力信号を積分する積分器、積分器の出力
を量子化する量子化器、および量子化器から出力する量
子化信号を極性を反転して上記アナログ入力信号に加算
する加算器を有する。ΔΣモジュレータ１０から出力す
る量子化信号はデジタルフィルタ２０によりＡＤ変換出
力として、上記アナログ入力信号に対応するデジタル信
号に変換される。2. Description of the Related Art Δ which is one of oversampling methods
FIG. 1 shows the basic configuration of a conventional ΔΣ type AD converter that performs AD conversion by the Σ modulation method. The ΔΣ modulator 10 generally inverts the polarity of an integrator that integrates an analog input signal, a quantizer that quantizes the output of the integrator, and a quantized signal that is output from the quantizer, and adds the quantized signal to the analog input signal. It has an adder. The quantized signal output from the ΔΣ modulator 10 is converted by the digital filter 20 as an AD conversion output into a digital signal corresponding to the analog input signal.
【０００３】一定電源電圧下で動作するΔΣ型ＡＤ変換
器は、絶対値が大きな過大信号入力に対してΔΣモジュ
レータ１０の内部の積分器出力である状態変数値が発振
（振幅増大現象）を起し、変換の線形性が失われたり、
ＳＮ比（信号対雑音比）の低下が発生したり、また入力
が正常動作範囲に復帰後も発振を継続してしまうことが
ある。さらにまた、ＡＣ（交流）信号をＡＤ変換するた
めのＡＤ変換器では、できるだけ大きなＡＣ信号入力に
対応することが必要という観点からも、入力信号のオフ
セットを取り除くことが好ましい。In a ΔΣ AD converter that operates under a constant power supply voltage, a state variable value, which is an integrator output inside the ΔΣ modulator 10, causes oscillation (amplitude increase phenomenon) with respect to an excessive signal input having a large absolute value. And the linearity of the conversion is lost,
A decrease in the SN ratio (signal to noise ratio) may occur, or oscillation may continue even after the input returns to the normal operating range. Furthermore, it is preferable to remove the offset of the input signal in the AD converter for AD-converting the AC (alternating current) signal from the viewpoint that it is necessary to handle the input of the AC signal as large as possible.
【０００４】図２はオフセットを取り除くための従来の
回路構成例を示す。この入力信号のオフセットの取り除
きは入力信号をΔΣモジュレータ１０に入れる前にハイ
パスフィルタ３０を通すことで行っている。この場合に
は、ΔΣモジュレータ１０の出力（ｙ）は、入力（ｘ）
に対してそのオフセット分が取り除かれたもの（ｘ′）
とΔΣモジュレータ１０自身が発生するオフセット（Ｏ
Ｓ）との和、すなわちFIG. 2 shows a conventional circuit configuration example for removing an offset. The offset of the input signal is removed by passing the input signal through the high-pass filter 30 before entering the ΔΣ modulator 10. In this case, the output (y) of the ΔΣ modulator 10 is the input (x)
For which the offset has been removed (x ')
And the offset generated by the ΔΣ modulator 10 itself (O
Sum of S), that is,
【０００５】[0005]
【数１】 ｙ＝ｘ′＋ＯＳ …（１） となる。ただし、ここではΔΣモジュレータ１０によっ
てノイズシェーピングされたノイズでの高域の成分は考
えていない。## EQU1 ## y = x '+ OS (1) However, here, the high-frequency component of the noise that is noise-shaped by the ΔΣ modulator 10 is not considered.
【０００６】[0006]
【発明が解決しようとする課題】従来のΔΣ型ＡＤ変換
器では、上述のようにΔΣモジュレータ自身が発生する
オフセットがそのΔΣモジュレータの出力に加算される
という問題があった。The conventional ΔΣ AD converter has a problem that the offset generated by the ΔΣ modulator itself is added to the output of the ΔΣ modulator as described above.
【０００７】そこで、本発明の目的は、上述の点に鑑み
て、入力信号のオフセットのみならず、ΔΣモジュレー
タ自身が発生するオフセットも取り除けるΔΣモジュレ
ータを提供することにある。Therefore, in view of the above points, an object of the present invention is to provide a ΔΣ modulator capable of removing not only the offset of the input signal but also the offset generated by the ΔΣ modulator itself.
【０００８】[0008]
【課題を解決するための手段】上記目的を達成するた
め、本発明は、アナログ入力信号を積分する第１の積分
手段と、該第１の積分手段の出力を量子化する量子化手
段と、該量子化手段の出力を極性を反転して前記アナロ
グ入力信号に加算する第１の加算手段と、前記量子化手
段の出力を積分する第２の積分手段と、該第２の積分手
段の出力を極性を反転して前記アナログ入力信号に加算
する第２の加算手段とを具備することを特徴とする。In order to achieve the above object, the present invention comprises first integrating means for integrating an analog input signal, and quantizing means for quantizing the output of the first integrating means. First adding means for inverting the polarity of the output of the quantizing means and adding it to the analog input signal, second integrating means for integrating the output of the quantizing means, and output of the second integrating means. And a second adding means for inverting the polarity and adding it to the analog input signal.
【０００９】[0009]
【作用】以下に図面を参照して本発明の作用を詳述す
る。図３は本発明の基本構成を示す。図３において、１
００は前述の従来のΔΣモジュレータ１０と同様の構成
の回路部分であり、アナログ入力信号を積分する第１積
分器１１，第１の積分器１１の出力を量子化する量子化
器１２，量子化器１２の出力を第１のリファレンス信号
（ＶＲＥＦ１）を参照してアナログ信号に変換する第１
のＤＡ（デジタルアナログ）変換器１３および第１のＤ
Ａ変換器１３の出力を上記アナログ入力信号に加算する
（極性は負）第１の加算器１４を有する。４１は量子化
器１２の出力を第２のリファレンス信号（ＶＲＥＦ２）
を参照してアナログ信号に変換する第２のＤＡ変換器、
４２は第２のＤＡ変換器４１の出力を積分する第２の積
分器、および４３は第２の積分器４２の出力を上記アナ
ログ入力信号に加算する（極性は負）第２の加算器であ
る。このように、本発明のΔΣモジュレータは、上記従
来例と同様の回路部分１００にＤＡ変換器４１，第２の
積分器４２および第２の加算器４３とが追加されて構成
される。The operation of the present invention will be described in detail below with reference to the drawings. FIG. 3 shows the basic configuration of the present invention. In FIG. 3, 1
Reference numeral 00 denotes a circuit portion having a configuration similar to that of the conventional ΔΣ modulator 10 described above, including a first integrator 11 for integrating an analog input signal, a quantizer 12 for quantizing the output of the first integrator 11, and a quantizer. A first reference signal (VREF1) for converting the output of the converter 12 into an analog signal;
DA (digital-analog) converter 13 and first D
It has a first adder 14 that adds the output of the A converter 13 to the analog input signal (the polarity is negative). 41 designates the output of the quantizer 12 as a second reference signal (VREF2)
A second DA converter for converting into an analog signal by referring to
42 is a second integrator that integrates the output of the second DA converter 41, and 43 is a second adder that adds the output of the second integrator 42 to the analog input signal (the polarity is negative). is there. As described above, the ΔΣ modulator of the present invention is configured by adding the DA converter 41, the second integrator 42, and the second adder 43 to the circuit portion 100 similar to the above-mentioned conventional example.
【００１０】上記基本構成における信号の入出力関係を
図４に示す。ｙはΔΣモジュレータからの出力である。
ＯＳはΔΣモジュレータの入力ノイズでオフセット以外
の色々な周波数を含んでいる。ただし、高周波成分は考
えない。また積分器において高周波成分の積分値はゼロ
となると仮定する。図４から次式（２）が成立する。FIG. 4 shows the input / output relationship of signals in the above basic configuration. y is the output from the ΔΣ modulator.
OS is input noise of the ΔΣ modulator and includes various frequencies other than the offset. However, high frequency components are not considered. Further, it is assumed that the integrated value of the high frequency component is zero in the integrator. The following expression (2) is established from FIG.
【００１１】[0011]
【数２】 [Equation 2]
【００１２】上式（２）において、Ｓ（＝ｊω）≒０、
つまり低周波成分のとき、In the above equation (2), S (= jω) ≈0,
That is, when the low frequency component,
【００１３】[0013]
【数３】 [Equation 3]
【００１４】となる。[0014]
【００１５】従って、直流成分に近い信号のときｙ≒０
となる。ｘは入力信号（交流）とオフセット、ＯＳは直
流成分が主であるから、上式（２）ではｘのオフセット
と、ＯＳとが≒０となり、ｘの信号成分のみが出力され
る。このように、入力信号（ｘ）も低周波成分が除去さ
れ、ΔΣモジュレータのオフセット（ＯＳ）も同様に低
周波成分が除去され、ΔΣモジュレータの出力ｙはｘの
信号成分のみとなる。Therefore, when the signal is close to the DC component, y≈0
Becomes Since x mainly has an input signal (AC) and an offset, and OS mainly has a DC component, the offset of x and OS become ≈0 in the above equation (2), and only the signal component of x is output. Thus, the low frequency component is removed from the input signal (x), the low frequency component is also removed from the offset (OS) of the ΔΣ modulator, and the output y of the ΔΣ modulator is only the signal component of x.
【００１６】[0016]
【実施例】以下、図面を参照して本発明の実施例を詳細
に説明する。Embodiments of the present invention will now be described in detail with reference to the drawings.
【００１７】（第１実施例）図５は本発明の一実施例の
ΔΣモジュレータの回路構成を示す。本例のΔΣモジュ
レータはＣＭＯＳプロセスによるＬＳＩ（大規模集積回
路）として実現され、その各スイッチはＭＯＳトランジ
スタによるトランスファゲートでできている。図中のＳ
１，Ｓ２は各スイッチに印加される切換信号を表わす。
本例のΔΣモジュレータは、スイッチドキャパシタ回路
（以下、ＳＣ回路と略称する）による２次のΔΣモジュ
レータ回路部分１１１〜１１５と、その出力により極性
をコントロールされ第２のリファレンス信号（ＶＲＥＦ
２）を積分するＳＣ回路１１７付の積分器（１１８）
と、その積分器出力を入力部の信号へ加算（極性は負）
するＳＣ回路１１９から成る。(First Embodiment) FIG. 5 shows a circuit configuration of a ΔΣ modulator according to an embodiment of the present invention. The ΔΣ modulator of this example is realized as an LSI (large-scale integrated circuit) by a CMOS process, and each switch thereof is made of a transfer gate by a MOS transistor. S in the figure
1, S2 represent switching signals applied to the respective switches.
The ΔΣ modulator of this example includes secondary ΔΣ modulator circuit portions 111 to 115 formed by a switched capacitor circuit (hereinafter, abbreviated as SC circuit) and a second reference signal (VREF) whose polarity is controlled by its output.
Integrator (118) with SC circuit 117 for integrating 2)
And its integrator output is added to the input signal (polarity is negative)
And an SC circuit 119 for performing the operation.
【００１８】ＳＣ回路１１１，１１３はそれぞれ抵抗器
と等価であり、演算増幅器１１２，１１４とキャパシタ
Ｃ5,Ｃ8 とで図３の第１の積分器１１を構成する。１１
５は図３の量子化器１２を構成する比較器であり、入力
クロック信号をノードａ点の積分器出力でゲートして
“１”，“０”の２値の量子化信号を発生する。ＳＣ回
路１１６は図３の第１のＤＡ変換器１３と第１の加算器
１４に相当する。ＳＣ回路１１７，演算増幅器１１８お
よびキャパシタＣ10とで図３の第２のＤＡ変換器４１と
第２の積分器４２を構成する。ＳＣ回路１１９は図３の
第２の加算器４３に相当する。The SC circuit 111 and 113 are equivalent to each resistor constituting the first integrator 11 of FIG. 3 in the operational amplifier 112 and the capacitor C 5, C 8. 11
Reference numeral 5 denotes a comparator which constitutes the quantizer 12 of FIG. 3, which gates the input clock signal with the integrator output at the node a to generate a binary quantized signal of "1" and "0". The SC circuit 116 corresponds to the first DA converter 13 and the first adder 14 in FIG. The SC circuit 117, the operational amplifier 118, and the capacitor C 10 form the second DA converter 41 and the second integrator 42 in FIG. The SC circuit 119 corresponds to the second adder 43 in FIG.
【００１９】図６は図５の回路の信号のタイミングと波
形を示すタイミングチャートである。FIG. 6 is a timing chart showing signal timings and waveforms of the circuit of FIG.
【００２０】本例の実験例では、ΔΣモジュレータの出
力周波数およびＳＣ回路のスイッチの動作周波数をそれ
ぞれ５１２ｋＨｚ、デジタルフィルタ出力時の出力レー
トを８ｋＨｚとし、入力およびΔΣモジュレータの低周
波数１６Ｈｚをカットオフとして減衰させるように構成
した。この結果、デジタルフィルタ出力が１４ビット出
力である場合には、オフセットが検出不能となるところ
まで、オフセットを低減させることができることが確認
できた。In the experimental example of this example, the output frequency of the ΔΣ modulator and the operating frequency of the switch of the SC circuit are 512 kHz, the output rate at the time of digital filter output is 8 kHz, and the low frequency of the input and ΔΣ modulator of 16 Hz is cut off. It was configured to attenuate. As a result, it was confirmed that when the digital filter output is a 14-bit output, the offset can be reduced to the point where the offset cannot be detected.
【００２１】（第２実施例）図７は第２の積分器出力を
ΔΣモジュレータの入力部の信号に加算する（極性は
負）別の構成例を示す。本例では、アナログ入力信号を
ΔΣモジュレータに導入するためのＳＣ回路１１１のキ
ャパシタＣ1 の左端を、入力信号と第２積分器出力間で
交互に接続するようになっており、これにより、（入力
信号−第２積分器出力）×Ｃ1 なる電荷をΔΣモジュレ
ータの第１積分器に入力する。(Second Embodiment) FIG. 7 shows another configuration example in which the output of the second integrator is added to the signal of the input portion of the ΔΣ modulator (the polarity is negative). In this example, the left end of the capacitor C 1 of the SC circuit 111 for introducing the analog input signal into the ΔΣ modulator is alternately connected between the input signal and the output of the second integrator. Input signal−second integrator output) × C 1 is input to the first integrator of the ΔΣ modulator.
【００２２】本例は、図５の第１実施例に比べ、ＳＣ回
路１１９を構成しているキャパシタＣ4 とこれに接続さ
れたスイッチを合計４個削減することができる利点があ
る。This example has an advantage over the first example shown in FIG. 5 in that the total number of capacitors C 4 constituting the SC circuit 119 and the switches connected thereto can be reduced by four.
【００２３】（その他の実施態様）上述した本発明の実
施例において、ΔΣモジュレータや積分器の次数を増減
することも可能であり、各回路ブロックの一部や全部を
ＳＣ回路でない回路、例えば抵抗器やキャパシタなどの
受動部品で組み、時間軸連続な系とすることも可能であ
る。また、上述した本発明の実施例では電圧を入力およ
びΔΣモジュレータ内の各状態変数としているが、電流
や電荷を信号表現媒体とすることも可能である。また、
参照信号（電圧）のＶＲＥＦ１およびＶＲＥＦ２はそれ
ぞれ異なる値とすることも、共通の値とすることもでき
る。(Other Embodiments) In the embodiments of the present invention described above, it is possible to increase or decrease the order of the ΔΣ modulator or integrator, and a part or all of each circuit block is a circuit other than the SC circuit, for example, a resistor. It is also possible to construct a system that is continuous on the time axis by combining passive components such as capacitors and capacitors. Further, in the above-described embodiment of the present invention, the voltage is used as the input and each state variable in the ΔΣ modulator, but it is also possible to use the current or the electric charge as the signal expressing medium. Also,
The reference signals (voltages) VREF1 and VREF2 may have different values or common values.
【００２４】[0024]
【発明の効果】以上説明したように、本発明によれば、
ΔΣモジュレータの出力を積分器で積分した出力を極性
を反転してΔΣモジュレータの入力部の入力信号へ加算
するようにしたので、入力信号のオフセットのみならず
ΔΣモジュレータのオフセットも同時に取り除くことが
できるという効果が得られる。As described above, according to the present invention,
Since the polarity of the output obtained by integrating the output of the ΔΣ modulator by the integrator is inverted and added to the input signal of the input part of the ΔΣ modulator, not only the offset of the input signal but also the offset of the ΔΣ modulator can be removed at the same time. The effect is obtained.
【図１】従来例のΔΣ型ＡＤ変換器の構成を示すブロッ
ク図である。FIG. 1 is a block diagram showing a configuration of a conventional ΔΣ AD converter.
【図２】他の従来例のΔΣ型ＡＤ変換器の構成を示すブ
ロック図である。FIG. 2 is a block diagram showing a configuration of another conventional ΔΣ AD converter.
【図３】本発明の基本構成を示すブロック図である。FIG. 3 is a block diagram showing a basic configuration of the present invention.
【図４】図３の信号の関係を示す図である。FIG. 4 is a diagram showing a relationship of signals in FIG.
【図５】本発明の一実施例の回路構成を示す回路図であ
る。FIG. 5 is a circuit diagram showing a circuit configuration of an embodiment of the present invention.
【図６】図５の信号のタイミングと波形を示すタイミン
グチャートである。6 is a timing chart showing timings and waveforms of the signals of FIG.
【図７】本発明の他の実施例の回路構成を示す回路図で
ある。FIG. 7 is a circuit diagram showing a circuit configuration of another embodiment of the present invention.
１０ ΔΣモジュレータ １１ 第１の積分器 １２ 量子化器 １３ 第１のＤＡ変換器 １４ 第１の加算器 ２０ デジタルフィルタ ４１ 第２のＤＡ変換器 ４２ 第２の積分器 ４３ 第２の加算器 １００ 従来と同様なΔΣモジュレータ回路部分 １１１，１１３，１１６，１１７，１１９ スイッチド
キャパシタ回路 １１２，１１４，１１８ 演算増幅器 １１５ 比較器10 ΔΣ modulator 11 first integrator 12 quantizer 13 first DA converter 14 first adder 20 digital filter 41 second DA converter 42 second integrator 43 second adder 100 conventional ΔΣ modulator circuit portion similar to the above 111, 113, 116, 117, 119 Switched capacitor circuit 112, 114, 118 Operational amplifier 115 Comparator
Claims (1)
手段と、 該第１の積分手段の出力を量子化する量子化手段と、 該量子化手段の出力を極性を反転して前記アナログ入力
信号に加算する第１の加算手段と、 前記量子化手段の出力を積分する第２の積分手段と、 該第２の積分手段の出力を極性を反転して前記アナログ
入力信号に加算する第２の加算手段とを具備することを
特徴とするΔΣモジュレータ。1. A first integrating means for integrating an analog input signal, a quantizing means for quantizing the output of the first integrating means, and an analog input by inverting the polarity of the output of the quantizing means. First adding means for adding to the signal, second integrating means for integrating the output of the quantizing means, and second for adding the output of the second integrating means to the analog input signal by inverting the polarity. ΔΣ modulator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP08451093A JP3226657B2 (en) | 1993-04-12 | 1993-04-12 | ΔΣ modulator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP08451093A JP3226657B2 (en) | 1993-04-12 | 1993-04-12 | ΔΣ modulator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06318872A true JPH06318872A (en) | 1994-11-15 |
| JP3226657B2 JP3226657B2 (en) | 2001-11-05 |
Family
ID=13832646
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP08451093A Expired - Lifetime JP3226657B2 (en) | 1993-04-12 | 1993-04-12 | ΔΣ modulator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3226657B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002247683A (en) * | 2001-02-02 | 2002-08-30 | Techtronic As | Microphone with internal a/d converter |
| JP2008028855A (en) * | 2006-07-24 | 2008-02-07 | Renesas Technology Corp | Semiconductor integrated circuit device |
| US7609187B2 (en) | 2005-02-10 | 2009-10-27 | National University Corporation Nagoya University | ΔΣ modulator and ΔΣ analog-digital converter |
| US8649528B2 (en) | 2001-02-02 | 2014-02-11 | Techtronic A/S | Microphone unit with internal A/D converter |
-
1993
- 1993-04-12 JP JP08451093A patent/JP3226657B2/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002247683A (en) * | 2001-02-02 | 2002-08-30 | Techtronic As | Microphone with internal a/d converter |
| JP2012019543A (en) * | 2001-02-02 | 2012-01-26 | Sonion Aktie Selsxab | Microphone with built-in a/d converter |
| US8649528B2 (en) | 2001-02-02 | 2014-02-11 | Techtronic A/S | Microphone unit with internal A/D converter |
| US7609187B2 (en) | 2005-02-10 | 2009-10-27 | National University Corporation Nagoya University | ΔΣ modulator and ΔΣ analog-digital converter |
| JP2008028855A (en) * | 2006-07-24 | 2008-02-07 | Renesas Technology Corp | Semiconductor integrated circuit device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3226657B2 (en) | 2001-11-05 |
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