JP3223708B2 - Multilayer electronic component and method of manufacturing the same - Google Patents
Multilayer electronic component and method of manufacturing the sameInfo
- Publication number
- JP3223708B2 JP3223708B2 JP16964794A JP16964794A JP3223708B2 JP 3223708 B2 JP3223708 B2 JP 3223708B2 JP 16964794 A JP16964794 A JP 16964794A JP 16964794 A JP16964794 A JP 16964794A JP 3223708 B2 JP3223708 B2 JP 3223708B2
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- electronic component
- substrate
- hole
- via hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/403—Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
- H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
- H05K3/4069—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
- H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
Landscapes
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Coils Or Transformers For Communication (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、電子機器に内蔵される
積層電子部品、とくに移動体通信機用のモジュール、半
導体パッケージ、およびハイブリッドＩＣ等を構成する
積層電子部品に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laminated electronic component built in an electronic device, and more particularly to a laminated electronic component constituting a module for a mobile communication device, a semiconductor package, a hybrid IC, and the like.
【０００２】[0002]
【従来の技術】従来の積層電子部品の構成を図６、図７
を用いて説明する。図６において、４１は積層電子部品
であり、基板４２の各側面４２ａ、４２ｂに外部電極４
３を形成してなるものである。ここで、基板４２は、内
部回路（図示せず）を備える絶縁性シート（図示せず）
を含む複数枚の絶縁性シートを積層して親積層体（図示
せず）を形成し、この親積層体を個々の基板４２の寸法
に合わせて切断、分割した後、焼成してなるものであ
る。また、外部電極４３は、基板４２の側面に、厚み方
向に導体を塗布してなるものである。このように構成さ
れる積層電子部品４１においては、基板４２の各側面４
２ａ、４２ｂに導体を塗布する際、必然的に基板４２の
両主面４２ｃにも導体が付着し、その結果、外部電極４
３の両端部４３ａが基板４２の両主面４２ｃに形成され
ることとなる。2. Description of the Related Art FIGS. 6 and 7 show the structure of a conventional laminated electronic component.
This will be described with reference to FIG. In FIG. 6, reference numeral 41 denotes a laminated electronic component, and external electrodes 4 are provided on the side surfaces 42a and 42b of the substrate 42, respectively.
3 is formed. Here, the substrate 42 is an insulating sheet (not shown) having an internal circuit (not shown).
Are laminated to form a parent laminate (not shown), and the parent laminate is cut and divided according to the dimensions of the individual substrates 42, and then fired. is there. The external electrode 43 is formed by applying a conductor on the side surface of the substrate 42 in the thickness direction. In the multilayer electronic component 41 configured as described above, each side surface 4 of the substrate 42
When the conductor is applied to 2a and 42b, the conductor also inevitably adheres to both main surfaces 42c of the substrate 42. As a result, the external electrode 4
3 are formed on both main surfaces 42c of the substrate 42.
【０００３】次に、図７において、５１は積層電子部品
であり、基板５２の各側面５２ａ、５２ｂに形成された
凹部５３に、外部電極５４を備えてなるものである。こ
こで、基板５２は、内部回路（図示せず）を備える絶縁
性シート（図示せず）を含む複数枚の絶縁性シートを積
層して親積層体５５を形成し、この親積層体５５に設け
たスルーホール５６の内周面に導体を塗布し、さらに、
個々の基板５２の寸法に合わせて親積層体５５を切断、
分割した後、焼成してなるものである。そして、親積層
体５５を切断する際、スルーホール５６を分断すること
により、凹部５３が形成されるとともに、この凹部５３
内に露出した導体が、外部電極５４となるものである。
このように構成される積層電子部品５１においては、ス
ルーホール５６の内周面に導体を塗布する際、必然的
に、スルーホール５６の開口部周辺にも導体が付着し、
その結果、外部電極５４の両端部５４ａが、基板５２の
両主面５２ｃ上の凹部５３の両端部５３ａ周辺に形成さ
れることとなる。Next, in FIG. 7, reference numeral 51 denotes a laminated electronic component, which is provided with an external electrode 54 in a concave portion 53 formed on each side surface 52a, 52b of a substrate 52. Here, the substrate 52 is formed by stacking a plurality of insulating sheets including an insulating sheet (not shown) having an internal circuit (not shown) to form a parent laminate 55, and A conductor is applied to the inner peripheral surface of the provided through hole 56, and further,
Cutting the parent laminate 55 in accordance with the dimensions of the individual substrates 52;
After dividing, it is fired. When the parent laminate 55 is cut, the through-holes 56 are divided to form the recesses 53, and the recesses 53 are formed.
The conductor exposed inside becomes the external electrode 54.
In the laminated electronic component 51 thus configured, when the conductor is applied to the inner peripheral surface of the through hole 56, the conductor naturally adheres also around the opening of the through hole 56,
As a result, both ends 54a of the external electrode 54 are formed around both ends 53a of the concave portion 53 on both the main surfaces 52c of the substrate 52.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、図６に
示す積層電子部品４１において、外部電極４３は、導体
を塗布して形成されるため、基板４２の両主面４２ｃに
設けられる外部電極４３の両端部４３ａの形状は一定で
なく、その寸法も所定のものより大きくなる場合があ
る。このため、基板４２に別の電子部品を実装する場
合、このような別の電子部品を実装できる面積が制限さ
れるとともに、外部電極４３の配置ピッチを細かくする
ことが困難となるものである。さらに、外部電極４３を
形成するために、基板４２の各側面４２ａ、４２ｂに別
々に金属ペーストを塗布しなければならず、作業の手間
がかさむものである。However, in the multilayer electronic component 41 shown in FIG. 6, since the external electrodes 43 are formed by applying a conductor, the external electrodes 43 are formed on both main surfaces 42c of the substrate 42. The shape of the both end portions 43a is not constant, and its size may be larger than a predetermined one. Therefore, when another electronic component is mounted on the substrate 42, the area in which such another electronic component can be mounted is limited, and it is difficult to reduce the arrangement pitch of the external electrodes 43. Further, in order to form the external electrodes 43, it is necessary to separately apply a metal paste to each of the side surfaces 42a and 42b of the substrate 42, which requires much labor.
【０００５】また、積層電子部品４１と同様に、図７に
示す積層電子部品５１においても、基板５２の両主面５
４ｃに設けられる外部電極５４の両端部５４ａの形状は
一定でなく、その寸法も所定のものより大きくなる場合
がある。このため、基板５２に別の電子部品を実装する
場合、このような別の電子部品を実装できる面積が制限
されるとともに、外部電極５４の配置ピッチを細かくす
ることが困難となるものである。さらに、スルーホール
５６は、ドリルを用いて形成されるが、そのときの直径
は一定の寸法、例えば０．３mmより小さくすることが困
難であり、このことも、外部電極５４の配置ピッチに制
約を加えることとなる。[0005] Similarly to the multilayer electronic component 41, the multilayer electronic component 51 shown in FIG.
The shape of both ends 54a of the external electrode 54 provided on the 4c is not constant, and its size may be larger than a predetermined one. For this reason, when another electronic component is mounted on the substrate 52, the area in which such another electronic component can be mounted is limited, and it is difficult to reduce the arrangement pitch of the external electrodes 54. Further, the through hole 56 is formed by using a drill, but it is difficult to make the diameter at that time smaller than a certain dimension, for example, 0.3 mm. This also restricts the arrangement pitch of the external electrodes 54. Will be added.
【０００６】さらに、積層電子部品４１、５１はいずれ
も、少なくとも需要者側に出荷する前に特性測定を行わ
なければならない。しかしながら、原則として、機能的
に独立したチップの状態にしてからでないと、これらの
特性測定は不可能である。すなわち、積層電子部品４１
においては、基板４２に金属ペーストを塗布し、外部電
極４３を形成しなければ特性測定ができず、積層電子部
品５１においては、スルーホール５６を分断した状態
で、親積層体５５を切断、分割することにより外部電極
５４を形成しなければ、特性測定ができないものであ
る。In addition, the characteristics of each of the laminated electronic components 41 and 51 must be measured at least before shipment to the consumer side. However, in principle, these characteristics cannot be measured unless the chip is functionally independent. That is, the multilayer electronic component 41
In the above, the characteristic measurement cannot be performed unless a metal paste is applied to the substrate 42 and the external electrode 43 is formed, and in the multilayer electronic component 51, the parent laminate 55 is cut and divided while the through holes 56 are divided. By doing so, the characteristics cannot be measured unless the external electrode 54 is formed.
【０００７】そこで、本発明においては、基板の主面を
別の電子部品を実装するために広く利用することがで
き、外部電極の配置ピッチを細かくすることができる積
層電子部品を提供するとともに、外部電極を形成する作
業が簡便で、しかも、製造中の親基板の状態で、個々の
積層電子部品の特性測定が行える積層電子部品の製造方
法を提供することを目的とする。In view of the above, the present invention provides a multilayer electronic component which can be widely used for mounting the main surface of a substrate for mounting another electronic component, and which can reduce the arrangement pitch of external electrodes. An object of the present invention is to provide a method of manufacturing a multilayer electronic component in which the operation of forming an external electrode is simple and the characteristics of each multilayer electronic component can be measured in a state of a parent substrate during manufacturing.
【０００８】[0008]
【課題を解決するための手段】上記の目的を達成するた
め、本発明にかかる積層電子部品においては、少なくと
もビアホールを備える絶縁性シートを含む複数枚の絶縁
性シートを積層してなる基板を備え、該基板の厚み方向
に凹部を設けるとともに、該凹部内の一部に、前記ビア
ホールに充填された導体を前記基板の厚み方向に沿って
帯状に露出させ、該導体を外部電極としたことを特徴と
する。また、前記凹部の両端部を、前記基板の両主面に
開口させて設けたことを特徴とする。さらに、前記凹部
の両端部のうち、一方の端部を前記基板の主面に開口さ
せて設け、他方の端部を前記基板の側面に設けたことを
特徴とする。また、前記外部電極の両端部のうち、少な
くとも一方の端部を、前記基板の主面に開口させて設け
たことを特徴とする。さらに、前記凹部内に溝を形成す
るとともに、該溝および前記凹部内の一部に導体を付与
し、該導体を前記外部電極としたことを特徴とする。SUMMARY OF THE INVENTION In order to achieve the above object, in the laminated electronic component according to the present invention, at least:
Comprising a substrate formed by laminating a plurality of insulating sheets including an insulating sheet also includes a via-hole Le, provided with a recess in the thickness direction of the substrate, a portion of the recess, filled in the via hole A conductor is exposed in a strip shape along the thickness direction of the substrate, and the conductor is used as an external electrode. Further, both ends of the concave portion are provided so as to be opened on both main surfaces of the substrate. Further, one end of both ends of the concave portion is provided so as to be opened on the main surface of the substrate, and the other end is provided on a side surface of the substrate. Further, at least one end of both ends of the external electrode is provided so as to be opened on the main surface of the substrate. Further, a groove is formed in the recess, and a conductor is provided in the groove and a part of the recess, and the conductor is used as the external electrode.
【０００９】また、本発明にかかる積層電子部品の製造
方法においては、導体を有するビアホールと、前記導体
に接続する内部回路と、を備える絶縁性シートを含む複
数枚の絶縁性シートを積層してなる親積層体を用い、前
記ビアホールの位置に合わせて、該親積層体にスルーホ
ールを形成することにより、前記ビアホールおよび前記
導体を前記親積層体の厚み方向に沿って分断し、前記ス
ルーホール内に前記導体を露出させる工程と、前記スル
ーホールに連続する切断面を形成して、前記親積層体を
切断、分割する工程と、を含むことを特徴とする。さら
に、前記導体が、前記ビアホールに充填されることを特
徴とする。また、前記導体が、前記ビアホールの内周面
に塗布されることを特徴とする。In the method for manufacturing a laminated electronic component according to the present invention, a plurality of insulating sheets including an insulating sheet having a via hole having a conductor and an internal circuit connected to the conductor are laminated. By forming a through hole in the parent laminate in accordance with the position of the via hole using the parent laminate, the via hole and the conductor are divided along the thickness direction of the parent laminate, and the through hole is formed. A step of exposing the conductor therein, and a step of forming a continuous cut surface in the through hole to cut and divide the parent laminate. Further, the conductor is filled in the via hole. Further, the conductor is applied to an inner peripheral surface of the via hole.
【００１０】[0010]
【作用】本発明にかかる積層電子部品によれば、ビアホ
ールに付与された導体を外部電極とするので、外部電極
の端部が基板の主面に設けられる場合、その端部の形状
および寸法は、ビアホールの開口部の形状および寸法に
よって規定され、一定のものとなる。According to the multilayer electronic component of the present invention, since the conductor provided in the via hole is used as the external electrode, when the end of the external electrode is provided on the main surface of the substrate, the shape and dimensions of the end are Is defined by the shape and size of the opening of the via hole and is constant.
【００１１】また、本発明にかかる積層電子部品の製造
方法によれば、親基板にスルーホールを形成し、そのス
ルーホール内に、予めビアホールに付与された導体を露
出させることにより、個々の積層電子部品の外部電極が
簡便に形成される。Further, according to the method of manufacturing a laminated electronic component of the present invention, a through hole is formed in a parent substrate, and a conductor previously provided to a via hole is exposed in the through hole, whereby each laminated electronic component is exposed. External electrodes of the electronic component are easily formed.
【００１２】さらに、本発明にかかる積層電子部品の製
造方法によれば、親基板にスルーホールを形成し、予め
ビアホールに付与された導体を分断することにより、個
々の積層電子部品が、互いに機能的に独立した状態とな
る。Further, according to the method for manufacturing a multilayer electronic component of the present invention, a through hole is formed in the parent substrate, and the conductor provided in advance to the via hole is divided so that the individual multilayer electronic components can function with each other. It becomes an independent state.
【００１３】[0013]
【実施例】本発明の一実施例にかかる積層電子部品の構
成を、図１を用いて説明する。図１において、１は積層
電子部品であり、内部回路（図示せず）を備える基板２
の各側面２ａ、２ｂに形成された凹部３の内部に、内部
回路に接続する外部電極４を備えてなるものである。こ
こで、凹部３は、その内部が曲面をなし、その両端部３
ａを基板２の両主面２ｃに開口させてなるものである。
また、外部電極４は、凹部３内の一部に、基板２の厚み
方向に沿って帯状に形成され、その両端部４ａを基板２
の両主面２ｃに設けてなるものである。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of a laminated electronic component according to an embodiment of the present invention will be described with reference to FIG. In FIG. 1, reference numeral 1 denotes a laminated electronic component, and a substrate 2 having an internal circuit (not shown).
An external electrode 4 connected to an internal circuit is provided inside the concave portion 3 formed on each of the side surfaces 2a and 2b. Here, the inside of the concave portion 3 forms a curved surface, and both ends 3
a is opened in both main surfaces 2c of the substrate 2.
The external electrode 4 is formed in a part of the recess 3 in a strip shape along the thickness direction of the substrate 2, and both ends 4 a of the external electrode 4
Are provided on both main surfaces 2c.
【００１４】次に、このような構成を備える積層電子部
品１の製造方法を、図２、図３を用いて説明する。ま
ず、図２に示す親積層体５が準備される。親積層体５
は、例えばセラミックから構成される絶縁性シート６を
複数枚積層してなるものである。ここで、絶縁性シート
６を積層する際、各シート６に、開口部が長方形をなす
ビアホール７が、その開口部が切断線８に直交した状態
で形成される。このビアホール７は、例えばパンチング
により、複数個の孔を、互いの開口部が重なり合うよう
に並設した状態で形成することにより、長方形の開口部
をなすものである。そして、これら絶縁性シート６に導
電膜や抵抗膜（図示せず）を印刷することにより、切断
線８によって区画される個々の積層電子部品１の内部回
路（図示せず）が形成される。さらに、ビアホール７に
導体９が充填され、この導体９と内部回路が接続され
る。また、各絶縁性シート６に設けられたビアホール
７、およびビアホール７に充填された導体９は、絶縁性
シート６の積層方向に連続した状態となり、親積層体５
の両主面５ａ上のビアホール７の開口部には、導体９が
露出するものである。Next, a method of manufacturing the laminated electronic component 1 having such a configuration will be described with reference to FIGS. First, the parent laminate 5 shown in FIG. 2 is prepared. Parent laminate 5
Is formed by laminating a plurality of insulating sheets 6 made of, for example, ceramic. Here, when the insulating sheets 6 are laminated, a via hole 7 having a rectangular opening is formed in each sheet 6 in a state where the opening is orthogonal to the cutting line 8. The via hole 7 forms a rectangular opening by, for example, punching and forming a plurality of holes in a state of being juxtaposed so that the openings overlap each other. Then, by printing a conductive film or a resistive film (not shown) on these insulating sheets 6, internal circuits (not shown) of the individual laminated electronic components 1 defined by the cutting lines 8 are formed. Further, the via hole 7 is filled with a conductor 9, and the conductor 9 and the internal circuit are connected. Further, the via holes 7 provided in each insulating sheet 6 and the conductors 9 filled in the via holes 7 are continuous in the laminating direction of the insulating sheets 6, so that the parent laminate 5 is formed.
The conductor 9 is exposed at the opening of the via hole 7 on both main surfaces 5a.
【００１５】次に、図３に示すように、ドリル等を用い
て、親積層体５を貫通するスルーホール１０が、切断線
８に沿って、ビアホール７の開口部の位置に対応して形
成される。ここで、スルーホール１０は、開口部の径寸
法がビアホール７の開口部の短辺寸法より大きいもので
あり、親積層体５の厚み方向に沿って、ビアホール７お
よび、ビアホール７に充填された導体９を分断するもの
である。そして、スルーホール１０内に導体９が露出
し、こうして露出した導体９は、図１に示す積層電子部
品１の外部電極４となるものである。この後、親積層体
５は焼成される。このように、スルーホール１０が形成
され、導体９が分断されることにより、切断線８によっ
て区画される個々の積層電子部品１となる部分は、互い
に他のものに対して機能的に独立した状態となる。した
がって、焼成後の親積層体５の状態のまま、スルーホー
ル１０内に露出した導体９（外部電極４）を介して、個
々の積層電子部品１の特性測定を行うことができるもの
である。なお、積層電子部品１の需要者側への出荷をこ
の段階で行ってもよいものである。Next, as shown in FIG. 3, a through hole 10 penetrating through the parent laminate 5 is formed along a cutting line 8 at a position corresponding to the opening of the via hole 7 using a drill or the like. Is done. Here, the through hole 10 has a diameter dimension of the opening larger than a short side dimension of the opening of the via hole 7, and is filled in the via hole 7 and the via hole 7 along the thickness direction of the parent laminate 5. This is for dividing the conductor 9. Then, the conductor 9 is exposed in the through hole 10, and the exposed conductor 9 becomes the external electrode 4 of the multilayer electronic component 1 shown in FIG. Thereafter, the parent laminate 5 is fired. As described above, the through-holes 10 are formed, and the conductors 9 are divided, so that the portions to be the individual laminated electronic components 1 defined by the cutting lines 8 are functionally independent from each other. State. Therefore, it is possible to measure the characteristics of each multilayer electronic component 1 via the conductor 9 (external electrode 4) exposed in the through hole 10 in the state of the parent laminate 5 after firing. Note that the multilayer electronic component 1 may be shipped to the consumer at this stage.
【００１６】そして、最終的に、スルーホール１０に連
続する切断面を形成して、親積層体５を切断、分割する
ことにより、機能的に独立した複数個の積層電子部品１
が形成される。このとき、スルーホール１０は親積層体
５の厚み方向に沿って分断され、積層電子部品１の凹部
３が形成されるものである。Finally, by forming a continuous cut surface in the through-hole 10 and cutting and dividing the parent laminate 5, a plurality of functionally independent laminated electronic components 1 are formed.
Is formed. At this time, the through hole 10 is divided along the thickness direction of the parent laminate 5, and the recess 3 of the multilayer electronic component 1 is formed.
【００１７】このように、本発明にかかる積層電子部品
１によれば、ビアホール７に充填された導体９が外部電
極４となるので、基板２の両主面２ｃに設けられる外部
電極４の両端部４ａの形状および寸法は、ビアホール７
の開口部の形状および寸法によって規定され、一定のも
のとなる。したがって、基板の側面に塗布した導体を外
部電極とする場合に比べて、基板２の両主面２ｃを、別
の電子部品を実装するために広く利用することができ、
しかも、外部電極４（凹部３）の配置ピッチを細かくす
ることができる。As described above, according to the multilayer electronic component 1 of the present invention, since the conductor 9 filled in the via hole 7 becomes the external electrode 4, both ends of the external electrode 4 provided on both main surfaces 2 c of the substrate 2 are provided. The shape and size of the portion 4 a
Is defined by the shape and dimensions of the opening of the first member. Therefore, both main surfaces 2c of the substrate 2 can be widely used for mounting another electronic component as compared with the case where the conductor applied to the side surface of the substrate is used as the external electrode.
In addition, the arrangement pitch of the external electrodes 4 (concave portions 3) can be reduced.
【００１８】また、本発明にかかる積層電子部品の製造
方法によれば、親積層体５にスルーホール１０を形成
し、このスルーホール１０の内部に、予めビアホール７
に充填された導体９を露出させることにより、外部電極
４を形成するので、基板の各側面に導体を塗布して外部
電極を形成する場合に比べて、外部電極を形成する作業
が簡便である。Further, according to the method for manufacturing a multilayer electronic component of the present invention, a through hole 10 is formed in the parent laminate 5 and a via hole 7 is previously formed in the through hole 10.
Since the external electrode 4 is formed by exposing the conductor 9 filled in the substrate, the operation of forming the external electrode is simpler than the case where the external electrode is formed by applying a conductor to each side surface of the substrate. .
【００１９】さらに、本発明にかかる積層電子部品の製
造方法によれば、親積層体５にスルーホール１０を形成
し、予めビアホール７に充填された導体９を分断するこ
とにより、個々の積層電子部品１となる部分を、互いに
機能的に独立した状態にすることができ、これにより、
焼成後の親積層体５の状態で、個々の積層電子部品１の
特性測定を効率的に行うことができる。Further, according to the method of manufacturing a laminated electronic component according to the present invention, a through-hole 10 is formed in the parent laminate 5 and the conductor 9 previously filled in the via hole 7 is divided so that the individual laminated electronic components are separated. The parts that become part 1 can be functionally independent of each other,
In the state of the parent laminate 5 after firing, the characteristic measurement of each laminated electronic component 1 can be efficiently performed.
【００２０】なお、本実施例の積層電子部品１は、凹部
３の両端部３ａおよび外部電極４の両端部４ａを、基板
２の両主面２ｃに設けてなるものであるが、例えば、図
４に示すように、凹部２３および外部電極２４の一方の
端部２３ａ、２４ａを、それぞれ基板２の一方の主面２
ｃに設け、他方の端部２３ｂ、２４ｂを、それぞれ基板
２の各側面２ａ、２ｂに設けて、積層電子部品２１を形
成してもよいものである。このような積層電子部品２１
は、図２における親積層体５の上部を構成する絶縁性シ
ート６にのみビアホール７を設け、このビアホール７に
導体９を充填し、親積層体５の上部のみを打ち抜くスル
ーホール１０を設け、焼成した後、この親積層体５を切
断、分割してなるものである。このように構成される積
層電子部品２１においては、基板２の一方の主面２ｃに
ついて、その全面を、別の電子部品を実装するために利
用することができる。The laminated electronic component 1 of this embodiment has both ends 3a of the concave portion 3 and both ends 4a of the external electrode 4 provided on both main surfaces 2c of the substrate 2, for example. As shown in FIG. 4, one end 23a, 24a of the recess 23 and the external electrode 24 is connected to one main surface 2 of the substrate 2 respectively.
c, and the other end portions 23b, 24b may be provided on the side surfaces 2a, 2b of the substrate 2, respectively, to form the laminated electronic component 21. Such a laminated electronic component 21
Is provided with a via hole 7 only in the insulating sheet 6 constituting the upper part of the parent laminate 5 in FIG. 2, filled with a conductor 9 in the via hole 7, and provided with a through hole 10 for punching out only the upper part of the parent laminate 5, After firing, the parent laminate 5 is cut and divided. In the laminated electronic component 21 configured as described above, the entire surface of one main surface 2c of the substrate 2 can be used for mounting another electronic component.
【００２１】また、必要に応じて、例えば、図１に示す
凹部３および外部電極４とともに、図４に示す凹部２３
および外部電極２４を、一個の積層電子部品に形成し、
これらを混在させてもよいものである。また、例えば、
図１に示す外部電極４と、基板２の各側面２ａ、２ｂに
導体を塗布してなる外部電極を一個の積層電子部品に混
在させてもよいものである。If necessary, for example, together with the concave portion 3 and the external electrode 4 shown in FIG.
And the external electrodes 24 are formed on one laminated electronic component,
These may be mixed. Also, for example,
The external electrode 4 shown in FIG. 1 and the external electrode formed by applying a conductor to each of the side surfaces 2a and 2b of the substrate 2 may be mixed in one laminated electronic component.
【００２２】さらに、本実施例の積層電子部品１は、基
板２の凹部３内に露出した導体９を、外部電極４とする
ものであるが、例えば、図５に示すように、凹部３３内
に溝３４を形成してなる基板２を備え、この溝３４内に
付与した導体９を外部電極３５とする積層電子部品３１
を形成しても良いものである。ここで、積層電子部品３
１は、図２に示す絶縁性シート６に設けたビアホール７
の内周面に導体９を塗布し、これら絶縁性シート６を積
層してなる親積層体５にスルーホール１０を設け、この
スルーホール１０内に、ビアホール７の内周面に沿って
溝状をなす導体９を露出させ、焼成した後、親積層体５
を切断、分割してなるものである。このように構成され
る積層電子部品３１においては、ビアホールに充填され
た導体を外部電極とする場合に比べて、外部電極３５を
構成する導体９が少量でよいため、製造コストを低減す
ることができる。Further, in the laminated electronic component 1 of the present embodiment, the conductor 9 exposed in the concave portion 3 of the substrate 2 is used as the external electrode 4. For example, as shown in FIG. Electronic component 31 including a substrate 2 having a groove 34 formed therein, and using the conductor 9 provided in the groove 34 as an external electrode 35.
May be formed. Here, the laminated electronic component 3
1 is a via hole 7 provided in the insulating sheet 6 shown in FIG.
A conductor 9 is applied to the inner peripheral surface of the substrate, and a through-hole 10 is provided in the parent laminate 5 formed by laminating the insulating sheets 6. A groove is formed in the through-hole 10 along the inner peripheral surface of the via hole 7. After exposing the conductor 9 and firing, the parent laminate 5
Is cut and divided. In the multilayer electronic component 31 configured as described above, the conductor 9 constituting the external electrode 35 may be smaller in number than in the case where the conductor filled in the via hole is used as the external electrode. it can.
【００２３】また、本実施例においては、導体９を充填
するためビアホール７の開口部が矩形をなし、スルーホ
ール１０の開口部が円形をなす場合について説明した
が、開口部がこれら以外の形状を有するビアホールおよ
びスルーホールを形成し、充填した導体を露出させて、
外部電極を形成してもよいものである。In this embodiment, the case where the opening of the via hole 7 has a rectangular shape to fill the conductor 9 and the opening of the through hole 10 has a circular shape has been described. Forming a via hole and a through hole having, and exposing the filled conductor,
External electrodes may be formed.
【００２４】[0024]
【発明の効果】本発明にかかる積層電子部品によれば、
ビアホールに付与された導体を外部電極とするので、外
部電極の端部が基板の主面に設けられる場合、その端部
の形状および寸法は、ビアホールの開口部の形状および
寸法によって規定され、一定のものとなる。したがっ
て、外部電極の配置ピッチを細かくすることができると
ともに、基板の主面を、別の電子部品を実装するため
に、広く利用することができ、部品実装の高密度化が図
れるものである。According to the multilayer electronic component of the present invention,
Since the conductor provided to the via hole is used as the external electrode, when the end of the external electrode is provided on the main surface of the substrate, the shape and size of the end are defined by the shape and size of the opening of the via hole, and are constant. It will be. Therefore, the arrangement pitch of the external electrodes can be reduced, and the main surface of the substrate can be widely used for mounting another electronic component, thereby achieving high component mounting density.
【００２５】また、本発明にかかる積層電子部品の製造
方法によれば、親積層体にスルーホールを設け、このス
ルーホールの内部に、予めビアホールに付与された導体
を露出させることにより、外部電極を形成することがで
き、外部電極を形成する作業が簡便である。According to the method of manufacturing a laminated electronic component of the present invention, a through hole is provided in the parent laminate, and a conductor previously provided to the via hole is exposed inside the through hole, so that the external electrode is formed. Can be formed, and the operation of forming the external electrodes is simple.
【００２６】さらに、本発明にかかる積層電子部品の製
造方法によれば、親積層体にスルーホールを設け、予め
ビアホールに付与された導体を分断することにより、個
々の積層電子部品となる部分を、互いに機能的に独立し
た状態にすることができる。これにより、焼成後の親積
層体の状態で、個々の積層電子部品の特性測定を効率的
に行うことができる。さらに、特性測定を行った後、こ
の親積層体の状態で需要者側に出荷すれば、個々の積層
電子部品がチップの状態にある場合に比べて、梱包等の
取り扱いが容易である。しかも、この状態であれば、需
要者側において、親積層体を切断、分割するだけで、複
数個の積層電子部品を得ることができ、積層電子部品の
実装が効率的に行えるものである。Further, according to the method for manufacturing a laminated electronic component of the present invention, a through-hole is provided in the parent laminate, and the conductor provided in advance to the via hole is divided so that a portion to be an individual laminated electronic component can be formed. , Can be functionally independent of each other. Thereby, in the state of the parent laminate after firing, the characteristic measurement of each laminated electronic component can be efficiently performed. Furthermore, if the parent laminate is shipped to the consumer after the characteristic measurement, the packaging and the like can be handled more easily than when the individual multilayer electronic components are in a chip state. Moreover, in this state, a plurality of laminated electronic components can be obtained by simply cutting and dividing the parent laminate on the customer side, and mounting of the laminated electronic components can be performed efficiently.
【図１】本発明の一実施例にかかる積層電子部品の斜視
図である。FIG. 1 is a perspective view of a multilayer electronic component according to one embodiment of the present invention.
【図２】図１に示す積層電子部品を製造するために用い
られる親積層体の斜視図である。FIG. 2 is a perspective view of a parent laminate used for manufacturing the multilayer electronic component shown in FIG.
【図３】図２に示す親積層体に、スルーホールが形成さ
れた状態を示す要部拡大斜視図である。FIG. 3 is an enlarged perspective view of a main part showing a state in which through holes are formed in the parent laminate shown in FIG. 2;
【図４】本発明の他の実施例にかかる積層電子部品の斜
視図である。FIG. 4 is a perspective view of a laminated electronic component according to another embodiment of the present invention.
【図５】本発明のさらに他の実施例にかかる積層電子部
品の斜視図である。FIG. 5 is a perspective view of a laminated electronic component according to still another embodiment of the present invention.
【図６】従来の積層電子部品の斜視図である。FIG. 6 is a perspective view of a conventional laminated electronic component.
【図７】他の従来の積層電子部品の斜視図である。FIG. 7 is a perspective view of another conventional laminated electronic component.
１、２１、３１ 積層電子
部品 ２ 基板 ２ａ、２ｂ 側面 ２ｃ 主面 ３、２３、３３ 凹部 ３ａ、２３ａ、２３ｂ、３３ａ 端部 ４、２４、３５ 外部電極 ４ａ、２４ａ、２４ｂ、３５ａ 端部 ５ 親積層体 ６ 絶縁性シ
ート ７ ビアホー
ル ９ 導体 １０ スルーホ
ール ３４ 溝1, 21, 31 laminated electronic component 2 substrate 2a, 2b side surface 2c main surface 3, 23, 33 concave portion 3a, 23a, 23b, 33a end portion 4, 24, 35 external electrode 4a, 24a, 24b, 35a end portion 5 parent Laminated body 6 Insulating sheet 7 Via hole 9 Conductor 10 Through hole 34 Groove
Claims (8)
ートを含む複数枚の絶縁性シートを積層してなる基板を
備え、該基板の厚み方向に凹部を設けるとともに、該凹
部内の一部に、前記ビアホールに充填された導体を前記
基板の厚み方向に沿って帯状に露出させ、該導体を外部
電極としたことを特徴とする積層電子部品。1. A comprising a substrate formed by laminating a plurality of insulating sheets including an insulating sheet comprising at least the via holes le, provided with a recess in the thickness direction of the substrate, a portion of the recess, the A laminated electronic component, wherein a conductor filled in a via hole is exposed in a strip shape along a thickness direction of the substrate, and the conductor is used as an external electrode.
面に開口させて設けたことを特徴とする請求項１に記載
の積層電子部品。2. The multilayer electronic component according to claim 1, wherein both ends of the concave portion are provided with openings on both main surfaces of the substrate.
を前記基板の一方の主面に開口させて設け、他方の端部
を前記基板の側面に設けたことを特徴とする請求項１に
記載の積層電子部品。3. The semiconductor device according to claim 1, wherein one of the two ends of the concave portion is provided so as to be opened on one main surface of the substrate, and the other end is provided on a side surface of the substrate. 2. The laminated electronic component according to 1.
とも一方の端部を、前記基板の主面に配置したことを特
徴とする請求項２または３に記載の積層電子部品。4. The multilayer electronic component according to claim 2, wherein at least one end of both ends of the external electrode is arranged on a main surface of the substrate.
該溝および前記凹部内の一部に導体を付与し、該導体を
前記外部電極としたことを特徴とする請求項１乃至４の
いずれかに記載の積層電子部品。5. A method for forming a groove in the recess,
The multilayer electronic component according to any one of claims 1 to 4, wherein a conductor is provided in a part of the groove and the recess, and the conductor is used as the external electrode.
に接続する内部回路と、を備えた絶縁性シートを含む複
数枚の絶縁性シートを積層してなる親積層体を用い、前
記ビアホールの位置に合わせて、該親積層体にスルーホ
ールを形成することにより、前記ビアホールおよび前記
導体を前記親積層体の厚み方向に沿って分断し、前記ス
ルーホール内に前記導体を露出させる工程と、前記スル
ーホールに連続する切断面を形成して、前記親積層体を
切断、分割する工程と、を含むことを特徴とする積層電
子部品の製造方法。6. A parent laminate formed by laminating a plurality of insulating sheets including an insulating sheet having a via hole having a conductor and an internal circuit connected to the conductor, and provided at a position of the via hole. Forming a through hole in the parent laminate, dividing the via hole and the conductor along a thickness direction of the parent laminate, and exposing the conductor in the through hole; Forming a continuous cut surface in the hole, and cutting and dividing the parent laminate.
れることを特徴とする請求項６に記載の積層電子部品の
製造方法。7. The method according to claim 6, wherein the conductor is filled in the via hole.
に塗布されることを特徴とする請求項６に記載の積層電
子部品の製造方法。8. The method according to claim 6, wherein the conductor is applied to an inner peripheral surface of the via hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16964794A JP3223708B2 (en) | 1994-07-21 | 1994-07-21 | Multilayer electronic component and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16964794A JP3223708B2 (en) | 1994-07-21 | 1994-07-21 | Multilayer electronic component and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0837251A JPH0837251A (en) | 1996-02-06 |
| JP3223708B2 true JP3223708B2 (en) | 2001-10-29 |
Family
ID=15890362
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16964794A Expired - Lifetime JP3223708B2 (en) | 1994-07-21 | 1994-07-21 | Multilayer electronic component and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3223708B2 (en) |
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| JP2006147901A (en) * | 2004-11-22 | 2006-06-08 | Murata Mfg Co Ltd | Stacked electronic component, its manufacturing method, and measuring method of its characteristics |
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| US10559723B2 (en) * | 2017-08-25 | 2020-02-11 | Rohm Co., Ltd. | Optical device |
-
1994
- 1994-07-21 JP JP16964794A patent/JP3223708B2/en not_active Expired - Lifetime
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|---|---|---|---|---|
| JP2004179338A (en) * | 2002-11-26 | 2004-06-24 | Kyocera Corp | Package for housing semiconductor device |
| JP2013239559A (en) * | 2012-05-15 | 2013-11-28 | Denso Corp | Method for manufacturing multilayer circuit board |
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| JPH0837251A (en) | 1996-02-06 |
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