JP3200880B2 - Combination structure of semiconductor device - Google Patents
Combination structure of semiconductor deviceInfo
- Publication number
- JP3200880B2 JP3200880B2 JP23577891A JP23577891A JP3200880B2 JP 3200880 B2 JP3200880 B2 JP 3200880B2 JP 23577891 A JP23577891 A JP 23577891A JP 23577891 A JP23577891 A JP 23577891A JP 3200880 B2 JP3200880 B2 JP 3200880B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- imposition
- semiconductor
- register
- semiconductor devices
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体装置に関し、特に
投影露光法によって製造する半導体装置において一回の
投影で複数の半導体装置に露光を施こすことによって製
造される半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device manufactured by exposing a plurality of semiconductor devices by one projection in a semiconductor device manufactured by a projection exposure method.
【0002】[0002]
【従来の技術】従来の半導体装置は、縮少投影露光によ
ってパターンを焼き付ける際に、一回の露光で投影面積
に入る限りの複数の同一パターンを同時に焼き付けてい
る。2. Description of the Related Art In a conventional semiconductor device, when a pattern is printed by reduced projection exposure, a plurality of identical patterns as long as they fall within a projection area in one exposure are simultaneously printed.
【0003】たとえば、縮少投影露光の面積が16mm
角で、一つの半導体装置の面積が7mm角の場合、一枚
のレチクルに同一のパターンを4つ面付けし、同時に4
つの同一の半導体装置を露光するようにしていた。[0003] For example, the area of reduced projection exposure is 16 mm.
When the area of one semiconductor device is 7 mm square, four identical patterns are imposed on one reticle, and
Two identical semiconductor devices were exposed.
【0004】前述の面付け露光方式によって製造された
半導体ウェハは、ウェハ完成後切り離され、面付け位置
にかかわらず別個の半導体装置としてパッケージに組み
立てられるので、半導体装置の完成後は、この面付け位
置を知る方法はなかった。A semiconductor wafer manufactured by the above-described imposition exposure method is cut off after completion of the wafer, and is assembled into a package as a separate semiconductor device regardless of the imposition position. There was no way to know where it was.
【0005】[0005]
【発明が解決しようとする課題】このような従来の面付
け露光法により製造した半導体装置では、レチクルの一
箇所に欠陥があった場合、半導体装置として完成した後
では、実際には一括露光した半導体装置のうち一つだけ
に欠陥が露光されているのに、欠陥を露光した半導体装
置とそうでない半導体装置の区別が付かないという問題
点があった。In a semiconductor device manufactured by such a conventional imposition exposure method, if there is a defect in one portion of a reticle, after the semiconductor device is completed, it is actually subjected to collective exposure. Although only one of the semiconductor devices is exposed to the defect, there is a problem that it is difficult to distinguish between the semiconductor device that has exposed the defect and the semiconductor device that is not exposed.
【0006】本発明の目的は、前記問題点を解決し、面
付け位置が直ちに判別できるようにした半導体装置を提
供することにある。SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device which solves the above-mentioned problem and enables an imposition position to be immediately determined.
【0007】[0007]
【課題を解決するための手段】本発明の特徴は、露光の
際の面付け位置を電気的に判別する手段を設けた半導体
装置を複数個用い、互いに異なった面付け位置の前記半
導体装置を複数個組み合わせた半導体装置の組合わせ構
造にある。 A feature of the present invention is that a semiconductor provided with a means for electrically determining an imposition position at the time of exposure is provided.
Using a plurality of devices, the halves at different imposition positions are used.
Combination structure of semiconductor devices combining multiple conductor devices
It is in construction.
【0008】[0008]
【実施例】図1は本発明の第1の実施例の半導体装置を
示す平面図である。FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present invention.
【0009】図1において、本発明の第1の実施例の4
面付けした半導体装置1は、互いに独立した4つの半導
体装置2,3,4,5から成っている。これら半導体装
置2,3,4,5は、それぞれレジスタ6,7,8,9
を有しており、これらレジスタ6,7,8,9には、そ
れぞれ〔11〕,〔10〕,〔01〕,FIG. 1 shows a fourth embodiment of the present invention.
The imposed semiconductor device 1 comprises four independent semiconductor devices 2, 3, 4, and 5. These semiconductor devices 2, 3, 4, and 5 have registers 6, 7, 8, 9 respectively.
And these registers 6, 7, 8, and 9 have [11], [10], [01],
〔00〕のデー
タをホトリソグラフィ技術により焼き付ける。The data of [00] is printed by photolithography.
【0010】これら半導体装置を分離してパッケージに
封止した後、レジスタ6,7,8,9のデータを電気的
に読出すことにより、半導体装置が縮少投影露光された
際の面付け位置を知ることができる。After these semiconductor devices are separated and sealed in a package, the data of the registers 6, 7, 8, and 9 are electrically read out, so that the imposition position when the semiconductor devices are subjected to the reduced projection exposure. You can know.
【0011】図2は本発明の第2の実施例の半導体装置
のブロック図である。FIG. 2 is a block diagram of a semiconductor device according to a second embodiment of the present invention.
【0012】図2において、本実施例は、半導体装置1
0と半導体装置11とが2面付けの露光によって製造さ
れた半導体装置で、互いに異なった面付け位置で製造さ
れたものである。レジスタ12,レジスタ13は、それ
ぞれ面付け位置を示すデータとしてレジスタ12には
〔1〕が、レジスタ13にはIn FIG. 2, a semiconductor device 1 according to this embodiment
The semiconductor device 0 and the semiconductor device 11 are manufactured by two imposition exposures, and are manufactured at different imposition positions. The register 12 and the register 13 each have [1] in the register 12 as data indicating the imposition position.
〔0〕がホトリソグラフィ
技術により焼付けられている。[0] is printed by the photolithography technique.
【0013】半導体装置10,11は、それぞれ排他的
論理和14を有しており、排他的論理和14にはその半
導体装置のレジスタ出力と、もう一つの半導体装置のレ
ジスタ出力とが接続され、面付け位置の異なる半導体装
置を接続した時だけ排他的論理和14の出力は〔1〕と
なる。半導体装置10,11は、排他的論理和14の出
力が〔1〕の時だけ動作をする。Each of the semiconductor devices 10 and 11 has an exclusive OR 14. The exclusive OR 14 is connected to a register output of the semiconductor device and a register output of another semiconductor device. The output of the exclusive OR 14 is [1] only when semiconductor devices having different imposition positions are connected. The semiconductor devices 10 and 11 operate only when the output of the exclusive OR 14 is [1].
【0014】本実施例は、2個の半導体装置に同等の機
能をさせ、2個の半導体装置の出力が一致することを確
めながら使う際に用いる。The present embodiment is used when two semiconductor devices are provided with the same function and used while confirming that the outputs of the two semiconductor devices match.
【0015】[0015]
【発明の効果】以上説明したように、本発明は、投影露
光の際の面付け位置を電気的に判別できるようにしたの
で、高信頼性を要求される用途に、たとえばマイクロコ
ンピュータを2個使い、2個のマイクロコンピュータの
出力の一致を確認しながら使う応用に際し、レチクルの
偶発的な欠陥や、レチクル上にゴミがあっても、2個の
マイクロコンピュータが同等の誤動作をすることがない
ように異なった面付け位置のマイクロコンピュータを使
用できるという効果を有する。As described above, according to the present invention, the imposition position at the time of projection exposure can be electrically determined. Therefore, for example, two microcomputers are required for applications requiring high reliability. In applications where the two microcomputers are used while checking the coincidence of the outputs of the two microcomputers, even if an accidental defect of the reticle or dust is present on the reticle, the two microcomputers do not perform the same malfunction. Thus, there is an effect that microcomputers having different imposition positions can be used.
【図1】本発明の第1の実施例の半導体装置を示す平面
図である。FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present invention.
【図2】本発明の第2の実施例の半導体装置を示す平面
図である。FIG. 2 is a plan view showing a semiconductor device according to a second embodiment of the present invention.
1 4面付けされた半導体装置 2,3,4,5 半導体装置 6,7,8,9 レジスタ 10,11 半導体装置 12,13 レジスタ 14 排他的論理和 1 4 Semiconductor devices with imposition 2,3,4,5 Semiconductor devices 6,7,8,9 Registers 10,11 Semiconductor devices 12,13 Registers 14 Exclusive OR
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H01L 21/027 H01L 21/66 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 21/027 H01L 21/66
Claims (2)
る手段を設けた半導体装置を複数個用い、互いに異なっ
た面付け位置の前記半導体装置を複数個組み合わせたこ
とを特徴とする半導体装置の組合わせ構造。A plurality of semiconductor devices provided with means for electrically determining an imposition position at the time of exposure;
A plurality of the semiconductor devices in the imposition positions
And a combination structure of a semiconductor device.
データを記憶したレジスタと排他的論理和とを有し、第
1の半導体装置の排他的論理和に第1の半導体装置のレ
ジスタの出力と第2の半導体装置のレジスタの出力とを
入力し、第2の半導体装置の排他的論理和に第2の半導
体装置のレジスタの出力と第1の半導体装置のレジスタ
の出力とを入力し、これらの排他的論理和の出力により
第1および第2の半導体装置が互いに異なった面付け位
置であることを認識し、この時だけ第1および第2の半
導体装置が動作するようにしたことを特徴とする請求項
1記載の半導体装置の組合わせ構造。2. The method according to claim 1, wherein the means for electrically discriminating is an imposition position.
A register storing data and an exclusive OR, and
The exclusive OR of the first semiconductor device is added to the exclusive OR of the first semiconductor device.
Between the output of the register and the output of the register of the second semiconductor device.
The second semiconductor device to the exclusive OR of the second semiconductor device.
Output of register of body device and register of first semiconductor device
And the output of
The first and second semiconductor devices have different imposition positions.
The first and second half only at this time.
2. The combination structure of a semiconductor device according to claim 1, wherein the conductor device operates .
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23577891A JP3200880B2 (en) | 1991-09-17 | 1991-09-17 | Combination structure of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23577891A JP3200880B2 (en) | 1991-09-17 | 1991-09-17 | Combination structure of semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0574679A JPH0574679A (en) | 1993-03-26 |
JP3200880B2 true JP3200880B2 (en) | 2001-08-20 |
Family
ID=16991104
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP23577891A Expired - Fee Related JP3200880B2 (en) | 1991-09-17 | 1991-09-17 | Combination structure of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3200880B2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1366889A3 (en) | 2002-05-16 | 2004-04-14 | Kuraray Co., Ltd. | Roller brush structure for painting, and method for producing it |
-
1991
- 1991-09-17 JP JP23577891A patent/JP3200880B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH0574679A (en) | 1993-03-26 |
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