JP3102590B2 - Boost circuit - Google Patents
Boost circuitInfo
- Publication number
- JP3102590B2 JP3102590B2 JP03272140A JP27214091A JP3102590B2 JP 3102590 B2 JP3102590 B2 JP 3102590B2 JP 03272140 A JP03272140 A JP 03272140A JP 27214091 A JP27214091 A JP 27214091A JP 3102590 B2 JP3102590 B2 JP 3102590B2
- Authority
- JP
- Japan
- Prior art keywords
- capacitor
- voltage
- power supply
- timing
- switch means
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Description
【０００１】[0001]
【産業上の利用分野】本発明は、単一直流電源からその
電源電圧の４倍（正又は負）の電圧を発生させる昇圧回
路に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a booster circuit for generating a voltage four times (positive or negative) of a single DC power supply.
【０００２】[0002]
【従来の技術】従来、入力電圧の４倍（正又は負）の電
圧を必要とする場合、それぞれ別に電源を外部から供給
していた。2. Description of the Related Art Conventionally, when a voltage four times (positive or negative) of an input voltage is required, power is separately supplied from the outside.
【０００３】[0003]
【発明が解決しようとする課題】このように、外部から
別電源を供給する場合、新たに電源を用意しなければな
らないという問題があった。As described above, when another power source is supplied from the outside, there is a problem that a new power source must be prepared.
【０００４】本発明の目的は、別電源を使用せずに電源
電圧の４倍の電圧を発生する昇圧回路を提供することで
ある。An object of the present invention is to provide a booster circuit which generates a voltage four times the power supply voltage without using a separate power supply.
【０００５】[0005]
【課題を解決するための手段】このため第１の発明の昇
圧回路は、第１のコンデンサ（Ｃ１）、第２のコンデン
サ（Ｃ２）、第３のコンデンサ（Ｃ３）、一端が第１の
出力端子（３）に接続され他端が接地（２）に接続され
た第４のコンデンサ（Ｃ４）、第５のコンデンサ（Ｃ
５）、および一端が第２の出力端子（４）に接続され他
端が前記接地に接続された第６のコンデンサ（Ｃ６）
と、第１のタイミングで前記第１，第２，第３のコンデ
ンサを電源端子（１）と前記接地との間に各々接続する
第１、第４，第５，第７、第８，第１１のスイッチ手段
（Ｓ１，Ｓ４，Ｓ５，Ｓ７，Ｓ８，Ｓ１１）と、前記第
１のタイミングで前記第５，第６のコンデンサを閉ルー
プ状に接続する第１２，第１４のスイッチ手段（Ｓ１
２，Ｓ１４）と、前記第１のタイミングと交互に発生す
る第２のタイミングで前記第１，第２，第３、第４のコ
ンデンサを第１のコンデンサが電源側、第４のコンデン
サが接地側となるよう前記電源端子と前記接地との間に
直列接続する第３、第２、第６，第１０のスイッチ手段
（Ｓ３，Ｓ２、Ｓ６，Ｓ１０）と、前記第２のタイミン
グで前記第１，第２，第３，第５のコンデンサを第１の
コンデンサが電源側、第５のコンデンサが接地側となる
よう前記電源端子と前記接地間との間に前記第３，第
２，第６のスイッチ手段を介して直列接続する第９，第
１３のスイッチ手段（Ｓ９，Ｓ１３）とを具備し、前記
第１のタイミングで前記第１、第２，第３のコンデンサ
を前記電源端子の電圧で各々充電し、前記第２のタイミ
ングで前記第４のコンデンサを前記第１，第２，第３の
コンデンサの電圧と前記電源端子の電圧を同極性で加算
した電圧で充電して、前記第１の出力端子から前記電源
端子の電圧の４倍の電圧を出力し、前記第２のタイミン
グで前記第５のコンデンサを前記第１，第２，第３のコ
ンデンサの電圧と前記電源端子の電圧を同極性で加算し
た電圧で充電し、前記第１のタイミングで前記第６のコ
ンデンサを前記第５のコンデンサの電圧で充電して、前
記第２の出力端子から前記電源端子の電圧の−４倍の電
圧を出力するよう構成した。Therefore, a booster circuit according to a first aspect of the present invention comprises a first capacitor (C1), a second capacitor (C2), a third capacitor (C3), and one end having a first output. A fourth capacitor (C4) and a fifth capacitor (C4) connected to the terminal (3) and the other end connected to the ground (2).
5) and a sixth capacitor (C6) having one end connected to the second output terminal (4) and the other end connected to the ground.
A first , a fourth, a fifth, a seventh, an eighth, and a eighth, respectively, connecting the first , second, and third capacitors between a power supply terminal (1) and the ground at a first timing . Eleventh switch means (S1, S4, S5, S7, S8, S11) and twelfth and fourteenth switch means (S1) for connecting the fifth and sixth capacitors in a closed loop at the first timing.
2, S14), and at a second timing alternately generated with the first timing, the first, second, third, and fourth capacitors are connected to the power supply side and the fourth capacitor is grounded. Third , second, sixth, and tenth switch means (S3, S2, S6, S10) connected in series between the power supply terminal and the ground so as to be on the side. The first, second, third, and fifth capacitors are connected between the power supply terminal and the ground so that the first capacitor is on the power supply side and the fifth capacitor is on the ground side .
Ninth and thirteenth switch means (S9, S13) connected in series via second and sixth switch means , wherein the first, second and third capacitors are connected at the first timing. Each of the capacitors is charged with a voltage of a power supply terminal, and at the second timing, the fourth capacitor is charged with a voltage obtained by adding the voltages of the first, second, and third capacitors and the voltage of the power supply terminal with the same polarity. Outputting a voltage four times the voltage of the power supply terminal from the first output terminal, and connecting the fifth capacitor with the voltages of the first, second, and third capacitors at the second timing. The power supply terminal is charged with a voltage obtained by adding the voltages of the same polarity with the same polarity, the sixth capacitor is charged with the voltage of the fifth capacitor at the first timing, and the power supply terminal is charged from the second output terminal. Output a voltage -4 times the voltage Form was.
【０００６】第２の発明の昇圧回路は、第１のコンデン
サ（Ｃ７）、一端が電源端子（１）に接続された第２の
コンデンサ（Ｃ８）、該第２のコンデンサの他端に一端
が接続された他端が第１の出力端子（３）に接続された
第３のコンデンサ（Ｃ９）、第４のコンデンサ（Ｃ１
０）、第５のコンデンサ（Ｃ１１）、および一端が接地
（２）に接続され他端が第２の出力端子（４）に接続さ
れた第６のコンデンサ（Ｃ１２）と、第１のタイミング
で前記第１のコンデンサを前記電源端子と前記接地との
間に接続する第１６，第１８のスイッチ手段（Ｓ１６，
Ｓ１８）と、前記第１のタイミングで前記第３，４のコ
ンデンサを閉ループ状に接続する第２０，第２１のスイ
ッチ手段（Ｓ２０，Ｓ２１）と、前記第１のタイミング
で前記第４，第５のコンデンサを前記第４のコンデンサ
が前記第２のコンデンサの他端側、前記第５のコンデン
サが前記接地側となるよう前記第２０のスイッチ手段を
介して直列接続する第２２，第２６のスイッチ手段（Ｓ
２２，Ｓ２６）と、前記第１のタイミングと交互に発生
する第２のタイミングで前記第１，第２のコンデンサを
閉ループ状に接続する第１５，第１９のスイッチ手段
（Ｓ１５，Ｓ１９）と、前記第２のタイミングで前記第
１，第４のコンデンサを第１のコンデンサが電源側、第
４のコンデンサが接地側となるよう前記電源端子と前記
接地との間に前記第１９のスイッチ手段を介して直列接
続する第５のスイッチ手段（Ｓ１７，Ｓ２３）と、前記
第２のタイミングで前記第５，第６のコンデンサを閉ル
ープ状に接続する第２４，第２５のスイッチ手段（Ｓ２
４，Ｓ２５）とを具備し、前記第１のタイミングで前記
第１のコンデンサを前記電源端子の電圧で充電し、前記
第２のタイミングで前記第２のコンデンサを前記第１の
コンデンサの電圧で充電すると共に、前記第４のコンデ
ンサを前記第１のコンデンサの電圧と前記電源端子の電
圧とを同極性で加算した電圧で充電し、且つ前記第４の
コンデンサを前記第２のコンデンサの電圧と前記電源端
子の電圧とを同極性で加算した電圧で充電し、前記第１
のタイミングで前記第３のコンデンサを前記第４のコン
デンサの電圧で充電して、前記第１の出力端子から電源
電圧の４倍の電圧を出力し、前記第１のタイミングで前
記第５のコンデンサを前記第４のコンデンサの電圧と前
記第２のコンデンサの電圧と前記電源端子の電圧とを同
極性で加算した電圧で充電し、前記第２のタイミングで
前記第６のコンデンサを前記第５のコンデンサの電圧で
充電して、前記第２の出力端子から電源電圧の−４倍の
電圧を出力するよう構成した。A booster circuit according to a second aspect of the present invention includes a first capacitor (C7), a second capacitor (C8) having one end connected to the power supply terminal (1), and one end connected to the other end of the second capacitor. A third capacitor (C9) whose other end is connected to the first output terminal (3), a fourth capacitor (C1).
0), a fifth capacitor (C11), and a sixth capacitor (C12) having one end connected to the ground (2) and the other end connected to the second output terminal (4), at the first timing. Sixteenth and eighteenth switch means for connecting the first capacitor between the power supply terminal and the ground (S16,
S18), 20th and 21st switch means (S20, S21) for connecting the third and fourth capacitors in a closed loop at the first timing, and the fourth and fourth switch means at the first timing. The twentieth switch means is arranged such that the fourth capacitor is on the other end side of the second capacitor and the fifth capacitor is on the ground side.
22, 26 of the switch means connected in series via (S
22, 15th and 19th switch means (S15, S19) for connecting the first and second capacitors in a closed loop at a second timing alternately generated with the first timing; At the second timing, the nineteenth switch means is connected between the power supply terminal and the ground so that the first and fourth capacitors are on the power supply side and the fourth capacitor is on the ground side. Fifth switch means (S17, S23) connected in series via a switch, and twenty-fourth and twenty-fifth switch means (S2) for connecting the fifth and sixth capacitors in a closed loop at the second timing.
4, S25), the first capacitor is charged with the voltage of the power supply terminal at the first timing, and the second capacitor is charged with the voltage of the first capacitor at the second timing. Charging, charging the fourth capacitor with a voltage obtained by adding the voltage of the first capacitor and the voltage of the power supply terminal with the same polarity, and charging the fourth capacitor with the voltage of the second capacitor. Charging with a voltage obtained by adding the voltage of the power supply terminal with the same polarity;
The third capacitor is charged with the voltage of the fourth capacitor at the timing of outputting a voltage four times the power supply voltage from the first output terminal, and the fifth capacitor is charged at the first timing. Is charged with a voltage obtained by adding the voltage of the fourth capacitor, the voltage of the second capacitor, and the voltage of the power supply terminal with the same polarity, and the sixth capacitor is charged at the second timing with the fifth voltage. The battery was charged with the voltage of the capacitor, and a voltage of -4 times the power supply voltage was output from the second output terminal.
【０００７】[0007]
【０００８】[0008]
【０００９】[0009]
【００１０】[0010]
【実施例】以下、本発明について詳細に説明する。図１
はその第１の実施例の昇圧回路の原理回路図である。１
は電源端子（入力端子）、２は接地（ＧＮＤ）、３は第
１出力端子、４は第２出力端子、Ｃ１〜Ｃ６はコンデン
サ、Ｓ１〜Ｓ１４はスイッチである。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail. FIG.
FIG. 3 is a principle circuit diagram of the booster circuit of the first embodiment. 1
Is a power supply terminal (input terminal), 2 is ground (GND), 3 is a first output terminal, 4 is a second output terminal, C1 to C6 are capacitors, and S1 to S14 are switches.
【００１１】この回路では、次のシーケンスでスイッチ
Ｓ１〜Ｓ１４のオン／オフを制御する。 （１）．Ｓ１、Ｓ４、Ｓ５、Ｓ７、Ｓ８、Ｓ１１、Ｓ１
２、Ｓ１４をオンし、残りのＳ２、Ｓ３、Ｓ６、Ｓ９、
Ｓ１０、Ｓ１３をオフする。 （２）．Ｓ２、Ｓ３、Ｓ６、Ｓ９、Ｓ１０、Ｓ１３をオ
ンし、残りのＳ１、Ｓ４、Ｓ５、Ｓ７、Ｓ８、Ｓ１１、
Ｓ１２、Ｓ１４をオフする。 （３）．（１）と（２）を繰り返す。In this circuit, on / off of the switches S1 to S14 is controlled in the following sequence. (1). S1, S4, S5, S7, S8, S11, S1
2, S14 is turned on, and the remaining S2, S3, S6, S9,
S10 and S13 are turned off. (2). S2, S3, S6, S9, S10, S13 are turned on, and the remaining S1, S4, S5, S7, S8, S11,
S12 and S14 are turned off. (3). (1) and (2) are repeated.
【００１２】この結果、（１）のステップでは、コンデ
ンサＣ１、Ｃ２、Ｃ３が各々電源端子１と接地間に接続
されてその各々に電源電圧Ｖｃｃが充電される。また、
コンデンサＣ５とＣ６がループ接続されて、コンデンサ
Ｃ５の電荷（後記するように４Ｖｃｃ）がコンデンサＣ
６に接地側が正となるよう反転転移する。As a result, in the step (1), the capacitors C1, C2 and C3 are respectively connected between the power supply terminal 1 and the ground, and each of them is charged with the power supply voltage Vcc. Also,
The capacitors C5 and C6 are connected in a loop, and the charge of the capacitor C5 (4 Vcc as described later) is
Inversion transition is made to 6 so that the ground side is positive.
【００１３】（２）のステップでは、コンデンサＣ１〜
Ｃ３が電源端子１とコンデンサＣ４との間に直列接続さ
れ、そのコンデンサＣ４に対して各コンデンサＣ１〜Ｃ
３の電荷の合計（３Ｖｃｃ）に電源端子１の電圧Ｖｃｃ
を加えた４Ｖｃｃの電圧が接地側を負として充電され
る。また、コンデンサＣ１〜Ｃ３は電源端子１とコンデ
ンサＣ５との間にも直列接続され、そのコンデンサＣ５
に対しても各コンデンサＣ１〜Ｃ３の電荷の合計（３Ｖ
ｃｃ）に電源端子１の電圧Ｖｃｃを加えた４Ｖｃｃの電
圧が接地側を負として充電される。In the step (2), the capacitors C1 to C1
C3 is connected in series between the power supply terminal 1 and the capacitor C4.
(3Vcc) to the voltage Vcc of the power supply terminal 1
Is charged with the ground side being negative. The capacitors C1 to C3 are also connected in series between the power supply terminal 1 and the capacitor C5.
, The sum of the charges of the capacitors C1 to C3 (3V
cc) and the voltage Vcc of the power supply terminal 1 plus 4 Vcc is charged with the ground side being negative.
【００１４】このように、コンデンサＣ４には４Ｖｃｃ
が、コンデンサＣ６には−４Ｖｃｃが交互に充電され
て、各々第１出力端子３、第２出力端子４から出力す
る。Thus, 4 Vcc is applied to the capacitor C4.
However, the capacitor C6 is charged with -4 Vcc alternately and output from the first output terminal 3 and the second output terminal 4, respectively.
【００１５】図２は上記図１の回路を具体化した昇圧回
路である。ここでは、スイッチＳ１〜Ｓ３、Ｓ５、Ｓ
６、Ｓ８〜Ｓ１０、Ｓ１２をＰチャンネルＭＯＳトラン
ジスタＭＰ１〜ＭＰ３、ＭＰ５、ＭＰ６、ＭＰ８〜ＭＰ
１０で構成し、またスイッチＳ４、Ｓ７、Ｓ１１、Ｓ１
３、Ｓ１４をＮチャンネルＭＯＳトランジスタＭＮ４、
ＭＮ７、ＭＮ１１〜ＭＮ１４で構成している。５はイン
バータ、６はクロック入力端子である。FIG. 2 shows a booster circuit that embodies the circuit of FIG. Here, the switches S1 to S3, S5, S
6, S8-S10 and S12 are P-channel MOS transistors MP1-MP3, MP5, MP6, MP8-MP
10 and switches S4, S7, S11, S1
3, S14 is an N-channel MOS transistor MN4,
MN7, MN11 to MN14. 5 is an inverter and 6 is a clock input terminal.
【００１６】この回路では、クロック入力端子６に印加
するクロックが“Ｌ”レベルのとき、ＭＰ１、ＭＮ４、
ＭＰ５、ＭＮ７、ＭＰ８、ＭＮ１１、ＭＮ１２、ＭＮ１
４のみがオンして上記ステップ（１）が実行される。ま
た、“Ｈ”レベルのときは、ＭＰ２、ＭＰ３、ＭＰ６、
ＭＰ９、ＭＰ１０、ＭＮ１３のみがオンして上記ステッ
プ（２）が実行される。ここでは、クロックの半周期毎
に、コンデンサＣ４への４Ｖｃｃの充電と、コンデンサ
Ｃ６への−４Ｖｃｃの充電が繰り返される。In this circuit, when the clock applied to the clock input terminal 6 is at "L" level, MP1, MN4,
MP5, MN7, MP8, MN11, MN12, MN1
Only step 4 is turned on, and the above step (1) is executed. When the signal is at the “H” level, MP2, MP3, MP6,
Only MP9, MP10 and MN13 are turned on, and the above step (2) is executed. Here, charging of the capacitor C4 with 4 Vcc and charging of the capacitor C6 with -4 Vcc are repeated every half cycle of the clock.
【００１７】図３は第２の実施例の昇圧回路の原理回路
図である。図１、２におけるものと同一のものには同一
の符号を付した。Ｃ７〜Ｃ１２はコンデンサ、Ｓ１５〜
Ｓ２６はスイッチである。FIG. 3 is a principle circuit diagram of the booster circuit of the second embodiment. 1 and 2 are denoted by the same reference numerals. C7 to C12 are capacitors, S15 to
S26 is a switch.
【００１８】この回路では、次のシーケンスでスイッチ
Ｓ１５〜Ｓ２６のオン／オフを制御する。 （Ａ）．Ｓ１６、Ｓ１８、Ｓ２０〜Ｓ２２、Ｓ２６をオ
ンし、残りのＳ１５、Ｓ１７、Ｓ１９、Ｓ２３〜Ｓ２５
をオフする。 （Ｂ）．Ｓ１５、Ｓ１７、Ｓ１９、Ｓ２３〜Ｓ２５をオ
ンし、残りのＳ１６、Ｓ１８、Ｓ２０〜Ｓ２２、Ｓ２６
をオフする。 （Ｃ）．（Ａ）と（Ｂ）を繰り返す。In this circuit, on / off of the switches S15 to S26 is controlled in the following sequence. (A). S16, S18, S20-S22, S26 are turned on, and the remaining S15, S17, S19, S23-S25
Turn off. (B). S15, S17, S19, S23 to S25 are turned on, and the remaining S16, S18, S20 to S22, S26
Turn off. (C). (A) and (B) are repeated.
【００１９】この結果、（Ａ）のステップでは、コンデ
ンサＣ７に図の極性でＶｃｃが充電する。また、コンデ
ンサＣ１０に図の極性で充電されていた２Ｖｃｃの電荷
が、コンデンサＣ９に放電して、第１出力端子３には、
このコンデンサＣ９の電荷（２Ｖｃｃ）とコンデンサＣ
８の電荷（Ｖｃｃ）と電源端子１の電圧Ｖｃｃを加算し
た電圧４Ｖｃｃが現れる。更に、コンデンサＣ１０の２
Ｖｃｃの電荷に加えてコンデンサＣ８の電荷（Ｖｃｃ）
と電源端子１の電圧Ｖｃｃを加算した電圧（４Ｖｃｃ）
が図示の極性でコンデンサＣ１１に充電される。As a result, in the step (A), the capacitor C7 is charged with Vcc with the polarity shown in the figure. The charge of 2 Vcc charged to the capacitor C10 with the polarity shown in the figure is discharged to the capacitor C9, and the first output terminal 3
The charge (2Vcc) of the capacitor C9 and the capacitor C9
8 (Vcc) and the voltage Vcc of the power supply terminal 1 are added to generate a voltage 4Vcc. Furthermore, the capacitor C10 2
Charge of capacitor C8 (Vcc) in addition to charge of Vcc
(4Vcc) obtained by adding the voltage Vcc of the power supply terminal 1
Is charged in the capacitor C11 with the polarity shown.
【００２０】（Ｂ）のステップでは、コンデンサＣ７と
Ｃ８が電源端子１を介してループ接続されるので、コン
デンサＣ７の電荷がコンデンサＣ８に図示の極性で充電
される。また、このコンデンサＣ７の電荷に電源端子１
の電圧Ｖｃｃを加えた２Ｖｃｃの電荷がコンデンサＣ１
０に図示の極性で充電される。更に、コンデンサＣ１１
とＣ１２がループ接続されて、コンデンサＣ１１の電荷
が逆極性でコンデンサＣ１２に転移され、第２出力端子
４に−４Ｖｃｃの電圧が現れる。In the step (B), since the capacitors C7 and C8 are connected in a loop via the power supply terminal 1, the charge of the capacitor C7 is charged to the capacitor C8 with the polarity shown. The charge of the capacitor C7 is connected to the power supply terminal 1
The voltage of 2 Vcc to which the voltage Vcc of the
It is charged to 0 with the polarity shown. Further, the capacitor C11
And C12 are connected in a loop, and the charge of the capacitor C11 is transferred to the capacitor C12 with the opposite polarity, and a voltage of -4 Vcc appears at the second output terminal 4.
【００２１】このように図３の回路では、特に第１出力
端子３の出力電圧が、電源端子１の電圧Ｖｃｃに、コン
デンサＣ８のＶｃｃ、コンデンサＣ９の２Ｖｃｃを加算
した値の電圧４Ｖｃｃとして現れる。負電源回路部分の
転移方法は図１の場合と同様である。As described above, in the circuit of FIG. 3, the output voltage of the first output terminal 3 appears as a voltage 4Vcc of a value obtained by adding the Vcc of the capacitor C8 and the 2Vcc of the capacitor C9 to the voltage Vcc of the power supply terminal 1. The transition method of the negative power supply circuit is the same as that in FIG.
【００２２】図４は上記図３の回路を具体化した昇圧回
路である。ここでは、スイッチＳ１５〜Ｓ１７、Ｓ１９
〜Ｓ２１をＰチャンネルＭＯＳトランジスタＭＰ１５〜
ＭＰ１７、ＭＰ１９〜ＭＰ２１で構成し、スイッチＳ１
８、Ｓ２２〜Ｓ２６をＮチャンネルＭＯＳトランジスタ
ＭＮ１８、ＭＮ２２〜ＭＮ２６で構成している。FIG. 4 shows a step-up circuit which embodies the circuit of FIG. Here, the switches S15 to S17, S19
~ S21 is a P-channel MOS transistor MP15 ~
MP17, MP19 to MP21, and a switch S1
8, S22 to S26 are constituted by N-channel MOS transistors MN18 and MN22 to MN26.
【００２３】この回路においては、クロック入力端子６
に入力するクロックが“Ｌ”レベルのとき、ＭＰ１６、
ＭＮ１８、ＭＰ２０、ＭＰ２１、ＭＰ２２、ＭＮ２６の
みがオンしてステップ（Ａ）が実行され、“Ｈ”レベル
のときは、ＭＰ１５、ＭＰ１７、ＭＰ１９、ＭＮ２３〜
ＭＮ２５のみがオンして、ステップ（Ｂ）が実行され
る。ここでは、クロックの半周期毎に、コンデンサＣ９
とＣ１２に交互に充電が行われる。In this circuit, the clock input terminal 6
, When the clock input to the L is at the “L” level,
Only MN18, MP20, MP21, MP22 and MN26 are turned on to execute step (A), and when "H" level, MP15, MP17, MP19, MN23-
Only the MN 25 is turned on, and the step (B) is executed. Here, every half cycle of the clock, the capacitor C9
And C12 are charged alternately.
【００２４】なお、上記実施例ではスイッチＳ１〜Ｓ２
６をＭＯＳトランジスタで構成したが、通常のバイポー
ラトランジスタで構成することもできる。In the above embodiment, the switches S1 to S2
Although the MOS transistor 6 is composed of a MOS transistor, it can be composed of a normal bipolar transistor.
【００２５】[0025]
【発明の効果】以上から本発明によれば、外部電源を使
用することなく、入力電源電圧の４倍、−４倍の電圧を
得ることができる。As described above, according to the present invention, a voltage that is four times or -4 times the input power supply voltage can be obtained without using an external power supply.
【図１】 本発明の第１実施例の昇圧回路の原理説明
用の回路図である。FIG. 1 is a circuit diagram for explaining the principle of a booster circuit according to a first embodiment of the present invention.
【図２】 該第１実施例の昇圧回路の具体的回路図で
ある。FIG. 2 is a specific circuit diagram of the booster circuit of the first embodiment.
【図３】 本発明の第２実施例の昇圧回路の原理説明
用の回路図である。FIG. 3 is a circuit diagram for explaining the principle of a booster circuit according to a second embodiment of the present invention.
【図４】 該第２実施例の昇圧回路の具体的回路図で
ある。FIG. 4 is a specific circuit diagram of the booster circuit of the second embodiment.
１：電源端子（入力端子）、２：接地（ＧＮＤ）、３：
第１出力端子、４：第２出力端子、５：インバータ、
６：クロック入力端子。1: power supply terminal (input terminal), 2: ground (GND), 3:
First output terminal, 4: second output terminal, 5: inverter,
6: Clock input terminal.
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 実開 昭59−8290（ＪＰ，Ｕ) 実開 昭55−59589（ＪＰ，Ｕ) 実開 昭63−198382（ＪＰ，Ｕ) (58)調査した分野(Int.Cl.7，ＤＢ名) H02M 3/07 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References Japanese Utility Model Showa 59-8290 (JP, U) Japanese Utility Model Showa 55-59589 (JP, U) Japanese Utility Model Showa 63-198382 (JP, U) (58) Field (Int.Cl. 7 , DB name) H02M 3/07
Claims (2)
ンサ（Ｃ２）、第３のコンデンサ（Ｃ３）、一端が第１
の出力端子（３）に接続され他端が接地（２）に接続さ
れた第４のコンデンサ（Ｃ４）、第５のコンデンサ（Ｃ
５）、および一端が第２の出力端子（４）に接続され他
端が前記接地に接続された第６のコンデンサ（Ｃ６）
と、 第１のタイミングで前記第１，第２，第３のコンデンサ
を電源端子（１）と前記接地との間に各々接続する第
１、第４，第５，第７、第８，第１１のスイッチ手段
（Ｓ１，Ｓ４，Ｓ５，Ｓ７，Ｓ８，Ｓ１１）と、 前記第１のタイミングで前記第５，第６のコンデンサを
閉ループ状に接続する第１２，第１４のスイッチ手段
（Ｓ１２，Ｓ１４）と、 前記第１のタイミングと交互に発生する第２のタイミン
グで前記第１，第２，第３、第４のコンデンサを第１の
コンデンサが電源側、第４のコンデンサが接地側となる
よう前記電源端子と前記接地との間に直列接続する第
３、第２、第６，第１０のスイッチ手段（Ｓ３，Ｓ２、
Ｓ６，Ｓ１０）と、 前記第２のタイミングで前記第１，第２，第３，第５の
コンデンサを第１のコンデンサが電源側、第５のコンデ
ンサが接地側となるよう前記電源端子と前記接地間との
間に前記第３，第２，第６のスイッチ手段を介して直列
接続する第９，第１３のスイッチ手段（Ｓ９，Ｓ１３）
とを具備し、 前記第１のタイミングで前記第１、第２，第３のコンデ
ンサを前記電源端子の電圧で各々充電し、前記第２のタ
イミングで前記第４のコンデンサを前記第１，第２，第
３のコンデンサの電圧と前記電源端子の電圧を同極性で
加算した電圧で充電して、前記第１の出力端子から前記
電源端子の電圧の４倍の電圧を出力し、 前記第２のタイミングで前記第５のコンデンサを前記第
１，第２，第３のコンデンサの電圧と前記電源端子の電
圧を同極性で加算した電圧で充電し、前記第１のタイミ
ングで前記第６のコンデンサを前記第５のコンデンサの
電圧で充電して、前記第２の出力端子から前記電源端子
の電圧の−４倍の電圧を出力することを特徴とする昇圧
回路。1. A first capacitor (C1), a second capacitor (C2), a third capacitor (C3), one end of which is a first capacitor (C1).
A fourth capacitor (C4) and a fifth capacitor (C4) connected to the output terminal (3) of the
5) and a sixth capacitor (C6) having one end connected to the second output terminal (4) and the other end connected to the ground.
A first , a fourth, a fifth, a seventh, an eighth, and a eighth, respectively, connecting the first , second, and third capacitors between a power supply terminal (1) and the ground at a first timing . Eleventh switch means (S1, S4, S5, S7, S8, S11) and twelfth and fourteenth switch means (S12, S12, S11) for connecting the fifth and sixth capacitors in a closed loop at the first timing. S14) and, at a second timing alternately generated with the first timing, the first, second, third, and fourth capacitors are connected to the power supply side and the fourth capacitor is connected to the ground side. Third , second, sixth, and tenth switch means (S3, S2,
S6, S10), and at the second timing, the first, second, third, and fifth capacitors are connected to the power supply terminal such that the first capacitor is on the power supply side and the fifth capacitor is on the ground side. and between the ground
Ninth and thirteenth switch means (S9, S13) connected in series via the third, second, and sixth switch means therebetween
And charging the first, second, and third capacitors with the voltage of the power supply terminal at the first timing, and charging the fourth capacitor at the second timing. 2, charging with a voltage obtained by adding the voltage of the third capacitor and the voltage of the power supply terminal with the same polarity, outputting a voltage four times the voltage of the power supply terminal from the first output terminal; The fifth capacitor is charged with the voltage obtained by adding the voltages of the first, second, and third capacitors and the voltage of the power supply terminal with the same polarity at the timing of, and the sixth capacitor is charged at the first timing. Wherein the voltage of the fifth capacitor is charged, and a voltage of -4 times the voltage of the power supply terminal is output from the second output terminal.
子（１）に接続された第２のコンデンサ（Ｃ８）、該第
２のコンデンサの他端に一端が接続された他端が第１の
出力端子（３）に接続された第３のコンデンサ（Ｃ
９）、第４のコンデンサ（Ｃ１０）、第５のコンデンサ
（Ｃ１１）、および一端が接地（２）に接続され他端が
第２の出力端子（４）に接続された第６のコンデンサ
（Ｃ１２）と、 第１のタイミングで前記第１のコンデンサを前記電源端
子と前記接地との間に接続する第１６，第１８のスイッ
チ手段（Ｓ１６，Ｓ１８）と、 前記第１のタイミングで前記第３，４のコンデンサを閉
ループ状に接続する第２０，第２１のスイッチ手段（Ｓ
２０，Ｓ２１）と、 前記第１のタイミングで前記第４，第５のコンデンサを
前記第４のコンデンサが前記第２のコンデンサの他端
側、前記第５のコンデンサが前記接地側となるよう前記
第２０のスイッチ手段を介して直列接続する第２２，第
２６のスイッチ手段（Ｓ２２，Ｓ２６）と、 前記第１のタイミングと交互に発生する第２のタイミン
グで前記第１，第２のコンデンサを閉ループ状に接続す
る第１５，第１９のスイッチ手段（Ｓ１５，Ｓ１９）
と、 前記第２のタイミングで前記第１，第４のコンデンサを
第１のコンデンサが電源側、第４のコンデンサが接地側
となるよう前記電源端子と前記接地との間に前記第１９
のスイッチ手段を介して直列接続する第５のスイッチ手
段（Ｓ１７，Ｓ２３）と、 前記第２のタイミングで前記第５，第６のコンデンサを
閉ループ状に接続する第２４，第２５のスイッチ手段
（Ｓ２４，Ｓ２５）とを具備し、 前記第１のタイミングで前記第１のコンデンサを前記電
源端子の電圧で充電し、前記第２のタイミングで前記第
２のコンデンサを前記第１のコンデンサの電圧で充電す
ると共に、前記第４のコンデンサを前記第１のコンデン
サの電圧と前記電源端子の電圧とを同極性で加算した電
圧で充電し、且つ前記第４のコンデンサを前記第２のコ
ンデンサの電圧と前記電源端子の電圧とを同極性で加算
した電圧で充電し、前記第１のタイミングで前記第３の
コンデンサを前記第４のコンデンサの電圧で充電して、
前記第１の出力端子から電源電圧の４倍の電圧を出力
し、 前記第１のタイミングで前記第５のコンデンサを前記第
４のコンデンサの電圧と前記第２のコンデンサの電圧と
前記電源端子の電圧とを同極性で加算した電圧で充電
し、前記第２のタイミングで前記第６のコンデンサを前
記第５のコンデンサの電圧で充電して、前記第２の出力
端子から電源電圧の−４倍の電圧を出力するようにした
ことを特徴とする昇圧回路。2. A first capacitor (C7), a second capacitor (C8) having one end connected to the power supply terminal (1), and a second end having one end connected to the other end of the second capacitor. 1 is connected to a third capacitor (C) connected to the output terminal (3).
9), a fourth capacitor (C10), a fifth capacitor (C11), and a sixth capacitor (C12) having one end connected to the ground (2) and the other end connected to the second output terminal (4). ), Sixteenth and eighteenth switch means (S16, S18) for connecting the first capacitor between the power supply terminal and the ground at a first timing, and the third switch means at the first timing. , 4th and 21st switch means (S
20, S21 and), wherein at a first timing fourth, said to the other end of said fifth capacitor and the fourth capacitor a second capacitor, said fifth capacitor serving as the ground side
22 to be connected in series via a first 20 of the switch means, first
26 switch means (S22, S26); and fifteenth and nineteenth switch means (S15) for connecting the first and second capacitors in a closed loop at a second timing alternately generated with the first timing. , S19)
At the second timing, the first and fourth capacitors are connected between the power supply terminal and the ground so that the first capacitor is on the power supply side and the fourth capacitor is on the ground side .
Fifth switch means (S17, S23) connected in series via the second switch means , and twenty- fourth and twenty-fifth switch means ( 25) for connecting the fifth and sixth capacitors in a closed loop at the second timing. S24, S25), wherein the first capacitor is charged with the voltage of the power supply terminal at the first timing, and the second capacitor is charged with the voltage of the first capacitor at the second timing. While charging, the fourth capacitor is charged with a voltage obtained by adding the voltage of the first capacitor and the voltage of the power supply terminal with the same polarity, and the fourth capacitor is charged with the voltage of the second capacitor. Charging with a voltage obtained by adding the voltage of the power supply terminal with the same polarity, charging the third capacitor with the voltage of the fourth capacitor at the first timing,
A voltage four times the power supply voltage is output from the first output terminal. At the first timing, the fifth capacitor is connected to the voltage of the fourth capacitor, the voltage of the second capacitor, and the power supply terminal. And the second capacitor is charged at the second timing with the voltage of the fifth capacitor, and is supplied from the second output terminal by -4 times the power supply voltage. A booster circuit characterized in that the voltage is outputted.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP03272140A JP3102590B2 (en) | 1991-09-24 | 1991-09-24 | Boost circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP03272140A JP3102590B2 (en) | 1991-09-24 | 1991-09-24 | Boost circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0591724A JPH0591724A (en) | 1993-04-09 |
| JP3102590B2 true JP3102590B2 (en) | 2000-10-23 |
Family
ID=17509648
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP03272140A Expired - Fee Related JP3102590B2 (en) | 1991-09-24 | 1991-09-24 | Boost circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3102590B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4001856B2 (en) * | 2003-10-30 | 2007-10-31 | ローム株式会社 | LIGHT EMITTING ELEMENT DRIVE DEVICE, DISPLAY MODULE HAVING LIGHT EMITTING ELEMENT DRIVE DEVICE, AND ELECTRONIC DEVICE HAVING DISPLAY MODULE |
-
1991
- 1991-09-24 JP JP03272140A patent/JP3102590B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0591724A (en) | 1993-04-09 |
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