CN110708044A - Sawtooth wave generating circuit and buck-boost converter - Google Patents

Abstract

The invention discloses a sawtooth wave generating circuit which comprises a current mirror module, a clock generating module, a voltage reduction sawtooth wave module and a voltage boosting sawtooth wave module, wherein the clock generating module comprises a first charging and discharging unit and a comparator unit; the first to fourth charge and discharge units have the same circuit structure. Correspondingly, the invention also discloses a buck-boost converter. According to the embodiment of the invention, the amplitude of the sawtooth wave can be flexibly set, so that the anti-interference capability of the buck-boost converter is improved, the peak value of the buck sawtooth wave can be equal to the valley value of the boost sawtooth wave, the smooth switching of the working mode of the buck-boost converter is ensured, and the efficiency of the buck-boost converter and the stability of the output voltage are improved.

Description

Sawtooth wave generating circuit and buck-boost converter

Technical Field

The invention relates to the technical field of electronics, in particular to a sawtooth wave generating circuit and a buck-boost converter.

Background

The BUCK-BOOST converter, also known as a BUCK-BOOST transformer, is a dc converter whose output voltage may be higher, lower or equal to the input voltage. Because the dual-mode control mode of the BUCK-BOOST converter works in the BUCK mode or the BOOST mode in one clock cycle, the situation that the BUCK mode and the BOOST mode work simultaneously does not occur, namely, the situation that a BUCK switching tube and a BOOST switching tube are switched simultaneously does not exist, and the efficiency is higher than that of other control modes, the current BUCK-BOOST converter generally adopts dual-mode control.

The dual-mode control mode of the BUCK-BOOST converter generally has the following two control strategies: firstly, a double modulation signal-single sawtooth wave control strategy is adopted; second, a single modulation signal-dual sawtooth control strategy is employed. The BUCK switching tube and the BOOST switching tube of the BUCK-BOOST converter adopting the single modulation signal-double sawtooth wave control strategy have the same modulation signal and are both from the output of the same error amplifier, and the sawtooth wave signal of the BOOST switching tube is obtained by superposing the sawtooth wave signal of the BUCK switching tube with a direct current bias voltage, so that only one sawtooth wave is in alternating load with the modulation signal at any time, namely only one switching tube is controlled.

Fig. 1 shows a buck sawtooth wave generating circuit provided in the prior art, a current source 7202 provides a charging current I1 to charge a capacitor C11 according to an input voltage Vin, a control circuit 7204 includes a switch SW1 connected in parallel with the capacitor C11, a frequency Clk switches over the switch SW1 to control charging and discharging of the capacitor C11, when a clock Clk is at a low level, the capacitor C11 is charged through the current I1, the voltage of the SAWbuck gradually rises until the level of the Clk is at a high level, the capacitor is rapidly discharged, the voltage of the SAWbuck recovers to Vbe, and then the capacitor is charged again when the level of the Clk is at a low level, the previous process is repeated to generate a buck sawtooth wave signal SAWbuck, and a limiting circuit 7206 is used for fixing a valley value of the buck sawtooth wave signal SAWbuck at Vbe. Fig. 2 shows a boost sawtooth wave generating circuit provided by the prior art, a current source 7210 provides a charging current I2 to charge a capacitor C22 according to an input voltage Vin, a control circuit 7212 includes a switch SW2 connected in parallel with the capacitor C22, a frequency Clk switches over the switch SW2 to control charging and discharging of the capacitor C22, when a clock Clk is at a low level, the capacitor C22 is charged through the current I2, the SAWboost voltage gradually rises until the Clk level is at a high level, the capacitor C22 is rapidly discharged, the SAWboost voltage returns to 2Vbe, and then the charging is performed again when the Clk is at a low level, the previous process is repeated to generate a boost sawtooth wave signal SAWboost, and a limiting circuit 7214 is used to fix the valley value of the charging voltage V1 at 2 Vbe. On one hand, the amplitude of the generated voltage reduction sawtooth wave and the amplitude of the generated voltage boosting sawtooth wave are Vbe, so that the noise resistance is poor; on the other hand, to make the amplitudes of the two sawtooth waves the same and equal to Vbe, and ensure that the peak value of the SAWbuck is equal to the valley value of the SAWboost, to implement smooth switching, the sawtooth waves need an accurate rising Vbe voltage within the low level time of the clock Clk, which is difficult to implement in practice. When the two sawtooth waves are intersected, the situation that two modes work simultaneously appears in one clock period, and two switching tubes are switched once, so that the switching loss is large, and the efficiency is low; when the double-sawtooth phase is separated, the switching time of the BUCK mode and the BOOST mode is longer, the output voltage greatly oscillates, and the output voltage is unstable.

Disclosure of Invention

The technical problem to be solved by the present invention is to provide a sawtooth wave generating circuit and a buck-boost converter, which can realize flexible setting of the amplitude of a sawtooth wave, thereby improving the anti-interference capability of the buck-boost converter, ensuring that the peak value of the buck sawtooth wave is equal to the valley value of the boost sawtooth wave, realizing smooth switching of the working mode of the buck-boost converter, and thus improving the efficiency of the buck-boost converter and the stability of the output voltage.

In order to solve the technical problem, the invention provides a sawtooth wave generation circuit, which comprises a current mirror module, a clock generation module, a buck sawtooth wave module and a boost sawtooth wave module, wherein the clock generation module comprises a first charge and discharge unit and a comparator unit, the buck sawtooth wave module comprises a second charge and discharge unit, and the boost sawtooth wave module comprises a third charge and discharge unit, a fourth charge and discharge unit and a control unit; the first to fourth charge and discharge units have the same circuit structure;

the current mirror module is used for providing charging current for the first to fourth charging and discharging units so as to charge the first to fourth charging and discharging units;

the first charging and discharging unit is used for generating a sawtooth wave with a target amplitude value according to the charging current; the comparator unit is used for generating a clock signal according to the sawtooth wave with the target amplitude value and sending the clock signal to the control unit and the second charging and discharging unit;

the second charging and discharging unit is used for charging and discharging according to the clock signal and outputting charging voltage;

the control unit is configured to generate a control signal according to the clock signal to control the third charge and discharge unit and the fourth charge and discharge unit to discharge once every two continuously charged clock cycles, so as to control the third charge and discharge unit and the fourth charge and discharge unit to start charging when each other completes one charging clock cycle and enters another charging clock cycle, and to control the third charge and discharge unit and the fourth charge and discharge unit to output a charging voltage when each other completes one charging clock cycle and enters another charging clock cycle.

Furthermore, the first to fourth charging and discharging units each include a control signal input terminal, a ground terminal, a charging terminal, and a charging voltage output terminal, and the comparator unit includes a voltage signal input terminal, a reference signal input terminal, and a clock signal output terminal;

the charging end of the first charging and discharging unit is connected with the current mirror module, the charging voltage output end of the first charging and discharging unit is connected with the voltage signal input end of the comparator unit, the reference signal input end of the comparator unit is connected to a reference voltage source, and the clock signal output end of the comparator unit is connected with the control signal input end of the first charging and discharging unit.

Further, the comparator unit includes a comparator and an inverter;

the non-inverting input end of the comparator is connected with the reference signal input end, the inverting input end of the comparator is connected with the voltage signal input end, the output end of the comparator is connected with the input end of the phase inverter, and the output end of the phase inverter is connected with the clock signal output end.

Furthermore, the step-down sawtooth wave module further comprises a step-down sawtooth wave output end, the charging end of the second charging and discharging unit is connected with the current mirror module, the control signal input end of the second charging and discharging unit is connected with the clock signal output end of the comparator unit, and the charging voltage output end of the second charging and discharging unit is connected with the step-down sawtooth wave output end.

Furthermore, the boost sawtooth wave module further comprises a boost sawtooth wave output end, the control unit comprises a logic control circuit, a first switch tube and a second switch tube, and the logic control circuit comprises a clock signal input end, a first charge and discharge control output end, a second charge and discharge control output end, a first switch control output end and a second switch control output end;

the charging end of the third charging and discharging unit and the charging end of the fourth charging and discharging unit are connected with the current mirror module, the first charge-discharge control output end is connected with the control signal input end of the third charge-discharge unit, the charging voltage output end of the third charging and discharging unit is connected with the first end of the first switch tube, the control end of the first switch tube is connected with the first switch control output end of the logic control circuit, the second charge-discharge control output end is connected with the control signal input end of the fourth charge-discharge unit, a charging voltage output end of the fourth charging and discharging unit is connected with a first end of the second switching tube, the control end of the second switch tube is connected with the control output end of the second switch, and the second end of the second switch tube and the second end of the first switch tube are connected with the boost sawtooth wave output end.

Furthermore, the logic control circuit also comprises a D trigger, a first AND gate and a second AND gate;

the clock input end of the D trigger is connected with the clock signal input end, the data input end of the D trigger is connected with the second output end of the D trigger, the first output end of the D trigger is respectively connected with the second switch control output end and the first input end of the first AND gate, the clock input end of the D trigger is respectively connected with the second input end of the first AND gate and the second input end of the second AND gate, the output end of the first AND gate is connected with the first charge-discharge control output end, the second output end of the D trigger is respectively connected with the first input end of the second AND gate and the first switch control output end, and the output end of the second AND gate is connected with the second charge-discharge control output end.

Furthermore, the first to fourth charge and discharge units also comprise discharge switch tubes and capacitors;

the first end of the discharge switch tube is connected with the charging end and the first end of the capacitor respectively, the first end of the capacitor is connected with the charging voltage output end, the control end of the discharge switch tube is connected with the control signal input end, and the second end of the discharge switch tube and the second end of the capacitor are connected with the grounding end.

Preferably, the discharge switch tube is an N-channel MOS tube, a drain of the N-channel MOS tube is a first end of the discharge switch tube, a source of the N-channel MOS tube is a second end of the discharge switch tube, and a gate of the N-channel MOS tube is a control end of the discharge switch tube.

Further, the current mirror module comprises a current input end, a third switching tube, a fourth switching tube, a fifth switching tube, a sixth switching tube and a seventh switching tube;

the current input end is connected to a current source, the second end of the third switching tube is connected with the current input end, the control end of the third switching tube, the second end of the third switching tube, the control end of the fourth switching tube, the control end of the fifth switching tube and the control end of the sixth switching tube are all connected with the control end of the seventh switching tube, the first end of the third switching tube, the first end of the fourth switching tube, the first end of the fifth switching tube and the first end of the sixth switching tube are all connected with the first end of the seventh switching tube, the first end of the seventh switching tube is connected to a power supply, and the second ends of the fourth to seventh switching tubes are respectively connected with the charging ends of the first to fourth charging and discharging units in a one-to-one correspondence manner.

Correspondingly, the invention also provides a buck-boost converter which comprises the sawtooth wave generating circuit.

According to the sawtooth wave generation circuit and the buck-boost converter, the current mirror module provides charging current for the first charging and discharging unit, the first charging and discharging unit generates sawtooth waves with target amplitude values according to the charging current, the comparator unit generates clock signals according to the sawtooth waves with the target amplitude values, and the second charging and discharging unit charges and discharges according to the clock signals and outputs charging voltage; the control unit generates a control signal according to the clock signal to control the third charge-discharge unit and the fourth charge-discharge unit to discharge once every two continuously charged clock cycles, so as to control the third charge-discharge unit and the fourth charge-discharge unit to start charging when the other side completes one charging clock cycle and enters the other charging clock cycle, and to control the third charge-discharge unit and the fourth charge-discharge unit to output charging voltage when the other side completes one charging clock cycle and enters the other charging clock cycle. Because the first to fourth charging and discharging units have the same circuit structure and are controlled by the same clock signal, when the charging current is the same, the charging voltage output by the second charging and discharging unit is also a buck sawtooth wave with a target amplitude value; and because the third charging and discharging unit and the fourth charging and discharging unit start charging when the other side finishes one charging clock cycle and enters another charging clock cycle, the third charging and discharging unit outputs charging voltage when finishing one charging clock cycle and entering another charging clock cycle, and the third charging and discharging unit discharges once every two clock cycles of continuous charging, a boosting sawtooth wave with a valley value equal to the peak value of the buck sawtooth wave and a target amplitude value is generated. The target amplitude value can be flexibly set by changing a reference voltage source of the comparator unit, so that the anti-interference capability of the buck-boost converter is improved; the peak value of the buck sawtooth wave can be equal to the valley value of the boost sawtooth wave, smooth switching of the working mode of the buck-boost converter is guaranteed, and therefore efficiency of the buck-boost converter and stability of output voltage are improved.

Drawings

FIG. 1 is a schematic circuit diagram of a buck sawtooth generation circuit provided in the prior art;

FIG. 2 is a schematic circuit diagram of a boost sawtooth generation circuit provided in the prior art;

FIG. 3 is a circuit block diagram of a sawtooth generation circuit provided by the present invention;

FIG. 4 is a circuit schematic of one embodiment of a sawtooth generation circuit provided by the present invention;

FIG. 5 is a circuit schematic of one embodiment of a logic control circuit of the sawtooth generation circuit provided by the present invention;

FIG. 6 is a logic control timing diagram and a sawtooth waveform diagram of the logic control circuit of the sawtooth wave generating circuit according to the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 3, it is a block diagram of the sawtooth wave generating circuit provided in the present invention.

The embodiment of the invention provides a sawtooth wave generation circuit, which comprises a current mirror module 1, a clock generation module 2, a buck sawtooth wave module 3 and a boost sawtooth wave module 4, wherein the clock generation module 2 comprises a first charging and discharging unit 21 and a comparator unit 22, the buck sawtooth wave module 3 comprises a second charging and discharging unit 31, and the boost sawtooth wave module 4 comprises a third charging and discharging unit 41, a fourth charging and discharging unit 42 and a control unit 43; wherein the first to fourth charge and discharge units (21,31,41,42) have the same circuit structure;

a current mirror module 1 for supplying a charging current to the first to fourth charge and discharge units (21,31,41,42) to charge the first to fourth charge and discharge units (21,31,41, 42);

a first charge and discharge unit 21 for generating a sawtooth wave having a target amplitude value according to the charging current; a comparator unit 22 for generating a clock signal according to the sawtooth wave having the target amplitude value and transmitting the clock signal to the control unit 43 and the second charge and discharge unit 31;

the second charge and discharge unit 31 performs charge and discharge according to the clock signal and outputs a charge voltage;

and a control unit 43 for generating a control signal according to the clock signal to control the third charge and discharge unit 41 and the fourth charge and discharge unit 42 to discharge once every two consecutive charging clock cycles, to control the third charge and discharge unit 41 and the fourth charge and discharge unit 42 to start charging when each other completes one charging clock cycle and enters another charging clock cycle, and to control the third charge and discharge unit 41 and the fourth charge and discharge unit 42 to output a charging voltage when each other completes one charging clock cycle and enters another charging clock cycle.

In specific implementation, the current mirror module 1 provides a charging current to the first to fourth charging and discharging units (21,31,41,42), the first charging and discharging unit 21 generates a sawtooth wave with a target amplitude value according to the charging current, the comparator unit 22 generates a clock signal according to the sawtooth wave with the target amplitude value and sends the clock signal to the control unit 43 and the second charging and discharging unit 31, and the second charging and discharging unit 31 performs charging and discharging according to the clock signal and outputs a charging voltage; the control unit 43 generates a control signal according to the clock signal to control the third charge and discharge unit 41 and the fourth charge and discharge unit 42 to discharge once every two consecutive charge clock cycles, so as to control the third charge and discharge unit 41 and the fourth charge and discharge unit 42 to start charging when each other completes one charge clock cycle and enters another charge clock cycle, and to control the third charge and discharge unit 41 and the fourth charge and discharge unit 42 to output a charging voltage when each other completes one charge clock cycle and enters another charge clock cycle. Since the first to fourth charging and discharging units (21,31,41,42) have the same circuit structure and are controlled by the same clock signal, when the charging current Ic0 ═ Ic1 ═ Ic2 ═ Ic4, the charging voltage output by the second charging and discharging unit 31 is also a buck sawtooth wave having a target amplitude value; and since the third charge and discharge unit 41 and the fourth charge and discharge unit 42 both output the charging voltage when completing one charging clock cycle and entering another charging clock cycle, and discharge once every two consecutive charging clock cycles, a boost sawtooth wave having a valley value equal to the peak value of the buck sawtooth wave and also having a target amplitude value is generated, and since the boost sawtooth wave and the buck sawtooth wave generated under the control of the same clock signal, the phase shift of the two sawtooth wave signals can be ensured to be the same. The target amplitude value can be flexibly set by changing the reference voltage source of the comparator unit 22, so that the anti-interference capability of the buck-boost converter is improved; the peak value of the buck sawtooth wave can be equal to the valley value of the boost sawtooth wave, smooth switching of the working mode of the buck-boost converter is guaranteed, and therefore efficiency of the buck-boost converter and stability of output voltage are improved.

Further, the first to fourth charge and discharge units (21,31,41,42) each include a control signal input terminal (c1, c2, c3, c4), a ground terminal (b1, b2, b3, b4), a charge terminal (a1, a2, a3, a4), and a charge voltage output terminal (d1, d2, d3, d4), and the comparator unit 22 includes a voltage signal input terminal VI, a reference signal input terminal VR, and a clock signal output terminal CLK;

the charging terminal a1 of the first charging and discharging unit 21 is connected to the current mirror module 1, the charging voltage output terminal d1 of the first charging and discharging unit 21 is connected to the voltage signal input terminal VI of the comparator unit 22, the reference signal input terminal VR of the comparator unit 22 is connected to the reference voltage source Vsaw, and the clock signal output terminal CLK of the comparator unit 22 is connected to the control signal input terminal c1 of the first charging and discharging unit 21.

In practical implementation, the current mirror module 1 provides the charging current Ic0 to the charging terminal a1 of the first charging/discharging unit 21, the first charging/discharging unit 21 is charged, when the voltage output from the charging voltage output terminal d1 of the first charging and discharging unit 21 is greater than the reference voltage Vsaw input from the reference signal input terminal VR of the comparator unit 22, the comparator unit 22 turns over, outputs a clock signal to control the first charging and discharging unit 21 to discharge rapidly, when the voltage output by the charging voltage output terminal d1 of the first charging and discharging unit 21 is less than the reference voltage Vsaw input by the reference signal input terminal VR of the comparator unit 22, the comparator unit 22 flips again, and outputs a clock signal to control the first charging and discharging unit 21 to charge, and repeats the above processes, the first charging and discharging unit 21 outputs a sawtooth wave with an amplitude value equal to Vsaw, and the comparator unit 22 outputs a clock signal through the clock signal output terminal CLK.

It should be noted that the sawtooth wave signal generated by the charging and discharging process of the first charging and discharging unit 21 is compared with a reference voltage Vsaw to generate a clock signal, so that the amplitude values of the boost sawtooth wave and the buck sawtooth wave of the embodiment of the present invention are the reference voltages of the comparator unit, and thus the amplitudes of the boost sawtooth wave and the buck sawtooth wave can be flexibly set.

Referring to fig. 4, a schematic circuit diagram of an embodiment of a sawtooth wave generating circuit according to the present invention is shown. As shown in fig. 3 and 4, the comparator unit 22 includes a comparator U1 and an inverter U2;

the non-inverting input terminal of the comparator U1 is connected to the reference signal input terminal VR, the inverting input terminal of the comparator U1 is connected to the voltage signal input terminal VI, the output terminal of the comparator U1 is connected to the input terminal of the inverter U2, and the output terminal of the inverter U2 is connected to the clock signal output terminal CLK.

Further, each of the first to fourth charge and discharge units (21,31,41,42) further comprises a discharge switching tube (MN1, MN3, MN7, MN8) and a capacitor (CO, C1, C2, C3);

taking the first charge/discharge unit 21 as an example, the first terminal of the discharge switch MN1 is connected to the charging terminal a1 and the first terminal of the capacitor CO, the first terminal of the capacitor CO is connected to the charging voltage output terminal d1, the control terminal of the discharge switch MN1 is connected to the control signal input terminal C1, and the second terminal of the discharge switch MN1 and the second terminal of the capacitor C0 are connected to the ground terminal b 1.

It should be noted that, the clock generation module 2 composed of the first charging and discharging unit 21 and the comparator unit 22 uses the relaxation oscillator principle, when the clock signal output by the output end of the inverter U2 is at a low level, the capacitor C0 is charged through the current Ic0, the voltage at both ends of the capacitor CO starts to rise, when the voltage rises to be equal to Vsaw, the voltage at the output end of the inverter U2 is inverted to a high level, then the switching tube MN1 is turned on to rapidly discharge the capacitor CO, when the voltage of the capacitor CO drops to be lower than Vsaw, the voltage at the output end of the inverter U2 is inverted to a low level again, the foregoing processes are repeated, so as to form the clock signal, and the high level time of the voltage at the output end of the inverter U2 is determined by the delay of the comparator U1 and the time when the voltage on the capacitor C0 drops to be lower than vs. The capacitances of the second charge and discharge unit 31 and the first charge and discharge unit 21 are matched, and the currents are also matched, that is, C0 is C1, Ic0 is Ic1, and the clock signals are also matched, so that the voltage output by the second charge and discharge unit 31 is a sawtooth wave with an amplitude value equal to Vsaw.

Preferably, the discharge switch tubes (MN1, MN3, MN7, MN8) are N-channel MOS tubes, drains of the N-channel MOS tubes are first ends of the discharge switch tubes (MN1, MN3, MN7, MN8), sources of the N-channel MOS tubes are second ends of the discharge switch tubes (MN1, MN3, MN7, MN8), and gates of the N-channel MOS tubes are control ends of the discharge switch tubes (MN1, MN3, MN7, MN 8).

Further, the buck sawtooth wave module 3 further includes a buck sawtooth wave output terminal Vsaw-buck, the charging terminal a2 of the second charge and discharge unit 3 is connected with the current mirror module 1, the control signal input terminal c2 of the second charge and discharge unit 31 is connected with the clock signal output terminal CLK of the comparator unit 22, and the charging voltage output terminal d2 of the second charge and discharge unit 31 is connected with the buck sawtooth wave output terminal Vsaw-buck.

It should be noted that, the current mirror module 1 provides a charging current to the charging terminal a2 of the second charging/discharging unit 31, the second charging/discharging unit 31 charges, the comparator unit 22 outputs a clock signal to the second charging/discharging unit 31 through the clock signal output terminal CLK to control the charging and discharging of the second charging/discharging unit 31, and since the clock signals for controlling the charging and discharging of the second charging/discharging unit 31 and the first charging/discharging unit 31 are the same and the circuit structures of the two are the same, when the current Ic0 is Ic1, the second charging/discharging unit 31 generates a sawtooth wave with the same amplitude value as that of the first charging/discharging unit 21.

Further, the boost sawtooth wave module 4 further includes a boost sawtooth wave output terminal Vsaw-boost, the control unit 43 includes a logic control circuit 431, a first switch tube MN5 and a second switch tube MN6, the logic control circuit 431 includes a clock signal input terminal CLK1, a first charge and discharge control output terminal CLK2, a second charge and discharge control output terminal CLK3, a first switch control output terminal CLKC and a second switch control output terminal CLKD;

the charging end a3 of the third charging and discharging unit 31 and the charging end a4 of the fourth charging and discharging unit 32 are connected to the current mirror module 1, the first charging and discharging control output terminal CLK2 is connected to the control signal input terminal c3 of the third charging and discharging unit 41, the charging voltage output terminal d3 of the third charging and discharging unit 41 is connected to the first end of the first switching tube MN5, the control terminal of the first switching tube MN5 is connected to the first switching control output terminal CLKC of the logic control circuit 431, the second charging and discharging control output terminal CLK3 is connected to the control signal input terminal c4 of the fourth charging and discharging unit 42, the charging voltage output terminal d4 of the fourth charging and discharging unit 42 is connected to the first end of the second switching tube MN6, the control terminal of the second switching tube MN6 is connected to the second switching control output terminal CLKD, and the second terminal of the second switching tube MN6 and the first switching tube MN5 are connected to the boost sawtooth wave output terminal Vsaw-boost.

In specific implementation, the current mirror module 1 provides charging currents Ic2 and Ic4 for the third charging and discharging unit 41 and the fourth charging and discharging unit 42, respectively, the logic control circuit 431 outputs a charging control signal through the first charging and discharging control output terminal CLK2 to control the third charging and discharging unit 41 to charge, when the third charging and discharging unit 41 completes one clock cycle of charging, the logic control circuit 431 outputs a charging control signal through the second charging and discharging control output terminal CLK3 to control the fourth charging and discharging unit 42 to charge, the third charging and discharging unit 41 continues to charge, and simultaneously outputs a high-level signal through the first switch control output terminal CLKC to turn on the first switch tube MN 5; when the third charge-discharge unit 41 completes two clock cycles after charging, the logic control circuit 431 outputs a discharge control signal through the first charge-discharge control output terminal CLK2 to control the third charge-discharge unit 41 to discharge rapidly, at this time, the fourth charge-discharge unit 42 completes one clock cycle after charging and continues charging, the logic control circuit 431 outputs a high level signal through the second switch control output terminal CLKD to turn on the second switch tube MN6, the logic control circuit 431 outputs a charge control signal through the first charge-discharge control output terminal CLK2 again to control the third charge-discharge unit 41 to charge, and thus a boost sawtooth wave having a target amplitude value and a valley value equal to the peak value of the buck sawtooth wave is output through the boost sawtooth wave output terminal Vsaw-boost.

Preferably, the first switch tube MN5 is an N-channel MOS tube, a drain of the N-channel MOS tube is a first end of the first switch tube MN5, a source of the N-channel MOS tube is a second end of the first switch tube MN5, and a gate of the N-channel MOS tube is a control end of the first switch tube MN 5;

the second switch tube MN6 is an N-channel MOS tube, a drain of the N-channel MOS tube is a first end of the second switch tube MN6, a source of the N-channel MOS tube is a second end of the second switch tube MN6, and a gate of the N-channel MOS tube is a control end of the second switch tube MN 6.

Further, the current mirror module 1 includes a current input end IB, a third switching tube MP1, a fourth switching tube MP2, a fifth switching tube MP4, a sixth switching tube MP5, and a seventh switching tube MP 8;

the current input end IB is connected to a current source, the second end of the third switching tube MP1 is connected to the current input end IB, the control end of the third switching tube MP1, the second end of the third switching tube MP1, the control end of the fourth switching tube MP2, the control end of the fifth switching tube MP4 and the control end of the sixth switching tube MP5 are connected to the control end of the seventh switching tube MP8, the first end of the third switching tube MP1, the first end of the fourth switching tube MP2, the first end of the fifth switching tube MP4 and the first end of the sixth switching tube MP5 are connected to the first end of the seventh switching tube MP8, the first end of the seventh switching tube MP8 is connected to a power supply VDD, and the second ends of the fourth to seventh switching tubes (MP2, MP4, MP5, MP8) are connected to the charging ends (a1, a 4642 a, a4 a) of the first to the fourth charging and discharging units (21,31,41, 42).

Referring to fig. 5, a schematic circuit diagram of an embodiment of a logic control circuit of a sawtooth wave generating circuit according to the present invention is shown. As shown in fig. 5, the logic control circuit 431 further includes a D flip-flop U3, a first and gate U4, and a second and gate U5;

a clock input end of the D flip-flop U3 is connected with a clock signal input end CLK1, a data input end of the D flip-flop U1 is connected with a second output end of the D flip-flop U3, a first output end of the D flip-flop U3 is connected with a second switch control output end CLKD and a first input end of a first and gate, respectively, a clock input end of the D flip-flop U3 is connected with a second input end of a first and gate U4 and a second input end of a second and gate U5, an output end of the first and gate U4 is connected with a first charge-discharge control output end CLK2, a second output end of the D flip-flop U2 is connected with a first input end of a second and gate U5 and a first switch control output end CLKC, and an output end of the second and gate is connected with a second charge-discharge control output end CLK 3.

As shown in fig. 3 and 4, in an implementation, the capacitances of the first to fourth charge/discharge units (21,31,41,42) are matched, that is, C0 ═ C1 ═ C2 ═ C3, and the currents are also matched, that is, Ic0 ═ Ic1 ═ Ic2 ═ Ic 4. The control clock signals output by the first switch control output terminal CLKC, the second switch control output terminal CLKD, the first charge and discharge control output terminal CLK2 and the second charge and discharge control output terminal CLK3 are generated by the logic control circuit in fig. 5.

Referring to fig. 6, a logic control timing diagram and a sawtooth waveform diagram of the logic control circuit of the sawtooth wave generating circuit provided by the present invention are shown. Now, referring to fig. 4, 5 and 6, when a high pulse of the clock signal at the output terminal CLK of the comparator arrives, the capacitor C1 discharges to 0 potential quickly, the first charge-discharge control output terminal CLK2 outputs a high pulse signal, the capacitor C2 discharges to 0 potential quickly, the second charge-discharge control output terminal CLK3 outputs a low level signal, and the capacitor C3 charges continuously; when the clock signal at the output terminal CLK of the comparator is at a low level, the charging voltage of the capacitor C1 gradually rises, the first and second charge/discharge control output terminals CLK2 and CLK3 both output low level signals, so that the voltages of the capacitor C2 and the capacitor C3 rise, and the second switch control output terminal CLKD outputs a high level signal, so that the voltage of the boost sawtooth wave output terminal Vsaw _ boost takes the potential of the capacitor C3. After a clock period, the second charge-discharge control output terminal CLK3 outputs a high pulse signal, the clock signal at the comparator output terminal CLK is a high pulse signal, so that the voltages on the capacitor C1 and the capacitor C3 are rapidly discharged to 0, the first charge-discharge control output terminal CLK2 outputs a low level signal, the voltage on the capacitor C2 continues to rise, during the clock period, the charging time of the capacitor C1 is the same as that of the capacitor C0, and the capacitor capacity is the same because the current is the same, so that the period of the sawtooth wave output by the buck sawtooth wave output terminal Vsaw _ buck is equal to the period of the clock signal output by the comparator output terminal CLK, the amplitude is equal to Vsaw, the capacitor C2 is charged for one clock period, and the voltage amplitude of the capacitor C2 is also equal to Vsaw at this time; thereafter, when the first and second charge/discharge control output terminals CLK2 and CLK3 output low level signals, the voltages of the capacitor C2 and the capacitor C3 rise, and the first switch control output terminal CLKC outputs a high level signal, so that the voltage of the boost sawtooth wave output terminal Vsaw _ boost takes the potential of the capacitor C2, and the voltage of the capacitor C2 is equal to Vsaw. After another clock cycle, the first charge-discharge control output terminal CLK2 outputs a high pulse signal, the capacitor C1 and the capacitor C2 are rapidly discharged to 0 potential, the capacitor C3 is continuously charged, during this clock cycle, the buck sawtooth output terminal Vsaw _ buck is also charged from 0 to Vsaw, the capacitor C2 is entirely charged for two clock cycles, and thus the peak value of the output voltage is 2Vsaw, i.e., the boost sawtooth output terminal Vsaw _ boost is raised from the initial value Vsaw to 2Vsaw, so that the sawtooth amplitude value output by the boost sawtooth output terminal Vsaw _ boost is Vsaw, and the valley potential is Vsaw. Since the value of Vsaw can be set by itself, the magnitudes of the step-up sawtooth wave and the step-down sawtooth wave can be flexibly set.

The invention provides a buck-boost converter, which comprises the sawtooth wave generating circuit in the embodiment.

It should be noted that, in the sawtooth wave generating circuit and the buck-boost converter provided in the foregoing embodiment, the discharge switch tubes (MN1, MN3, MN7, MN8), the first switch tube MN5, and the second switch tube MN6 are N-channel MOS tubes, which is only one implementation manner among them, in other implementations, the discharge switch tubes (MN1, MN3, MN7, MN8), the first switch tube MN5, and the second switch tube MN6 may also be replaced by P-channel MOS tubes or other three-terminal control switch devices or derivatives thereof, and in different application occasions, the selection and the setting of the switch tubes are a common design process in the prior art according to requirements such as power consumption, cost, driving power of an actual circuit, parameter matching with a driving control element of the switch tubes, and the like, and are not described herein.

According to the sawtooth wave generation circuit and the buck-boost converter, the current mirror module provides charging current for the first charging and discharging unit, the first charging and discharging unit generates sawtooth waves with target amplitude values according to the charging current, the comparator unit generates clock signals according to the sawtooth waves with the target amplitude values, and the second charging and discharging unit charges and discharges according to the clock signals and outputs charging voltage; the control unit generates a control signal according to the clock signal to control the third charge-discharge unit and the fourth charge-discharge unit to discharge once every two continuously charged clock cycles, so as to control the third charge-discharge unit and the fourth charge-discharge unit to start charging when the other side completes one charging clock cycle and enters the other charging clock cycle, and to control the third charge-discharge unit and the fourth charge-discharge unit to output charging voltage when the other side completes one charging clock cycle and enters the other charging clock cycle. Because the first to fourth charging and discharging units have the same circuit structure and are controlled by the same clock signal, when the charging current is the same, the charging voltage output by the second charging and discharging unit is also a buck sawtooth wave with a target amplitude value; and because the third charging and discharging unit and the fourth charging and discharging unit start charging when the other side finishes one charging clock cycle and enters another charging clock cycle, the third charging and discharging unit outputs charging voltage when finishing one charging clock cycle and entering another charging clock cycle, and the third charging and discharging unit discharges once every two clock cycles of continuous charging, a boosting sawtooth wave with a valley value equal to the peak value of the buck sawtooth wave and a target amplitude value is generated. The target amplitude value can be flexibly set by changing a reference voltage source of the comparator unit, so that the anti-interference capability of the buck-boost converter is improved; the peak value of the buck sawtooth wave can be equal to the valley value of the boost sawtooth wave, smooth switching of the working mode of the buck-boost converter is guaranteed, and therefore efficiency of the buck-boost converter and stability of output voltage are improved.

While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention.

Claims (10)

1. A sawtooth wave generation circuit is characterized by comprising a current mirror module, a clock generation module, a voltage reduction sawtooth wave module and a voltage boosting sawtooth wave module, wherein the clock generation module comprises a first charge-discharge unit and a comparator unit, the voltage reduction sawtooth wave module comprises a second charge-discharge unit, and the voltage boosting sawtooth wave module comprises a third charge-discharge unit, a fourth charge-discharge unit and a control unit; the first to fourth charge and discharge units have the same circuit structure;

the current mirror module is used for providing charging current for the first to fourth charging and discharging units so as to charge the first to fourth charging and discharging units;

the first charging and discharging unit is used for generating a sawtooth wave with a target amplitude value according to the charging current; the comparator unit is used for generating a clock signal according to the sawtooth wave with the target amplitude value and sending the clock signal to the control unit and the second charging and discharging unit;

the second charging and discharging unit is used for charging and discharging according to the clock signal and outputting charging voltage;

the control unit is configured to generate a control signal according to the clock signal to control the third charge and discharge unit and the fourth charge and discharge unit to discharge once every two continuously charged clock cycles, so as to control the third charge and discharge unit and the fourth charge and discharge unit to start charging when each other completes one charging clock cycle and enters another charging clock cycle, and to control the third charge and discharge unit and the fourth charge and discharge unit to output a charging voltage when each other completes one charging clock cycle and enters another charging clock cycle.

2. The sawtooth wave generating circuit of claim 1 wherein the first to fourth charge and discharge units each comprise a control signal input terminal, a ground terminal, a charge terminal, and a charge voltage output terminal, and the comparator unit comprises a voltage signal input terminal, a reference signal input terminal, and a clock signal output terminal;

the charging end of the first charging and discharging unit is connected with the current mirror module, the charging voltage output end of the first charging and discharging unit is connected with the voltage signal input end of the comparator unit, the reference signal input end of the comparator unit is connected to a reference voltage source, and the clock signal output end of the comparator unit is connected with the control signal input end of the first charging and discharging unit.

3. The sawtooth generation circuit of claim 2 wherein the comparator unit comprises a comparator and an inverter;

the non-inverting input end of the comparator is connected with the reference signal input end, the inverting input end of the comparator is connected with the voltage signal input end, the output end of the comparator is connected with the input end of the phase inverter, and the output end of the phase inverter is connected with the clock signal output end.

4. The sawtooth wave generation circuit of claim 2 wherein the buck sawtooth wave module further comprises a buck sawtooth wave output, the charge terminal of the second charge and discharge unit is connected to the current mirror module, the control signal input terminal of the second charge and discharge unit is connected to a clock signal output terminal of the comparator unit, and the charge voltage output terminal of the second charge and discharge unit is connected to the buck sawtooth wave output terminal.

5. The sawtooth wave generation circuit of any one of claims 2 to 4 wherein the boost sawtooth wave module further comprises a boost sawtooth wave output, the control unit comprises a logic control circuit, a first switch tube and a second switch tube, the logic control circuit comprises a clock signal input, a first charge and discharge control output, a second charge and discharge control output, a first switch control output and a second switch control output;

the charging end of the third charging and discharging unit and the charging end of the fourth charging and discharging unit are connected with the current mirror module, the first charge-discharge control output end is connected with the control signal input end of the third charge-discharge unit, the charging voltage output end of the third charging and discharging unit is connected with the first end of the first switch tube, the control end of the first switch tube is connected with the first switch control output end of the logic control circuit, the second charge-discharge control output end is connected with the control signal input end of the fourth charge-discharge unit, a charging voltage output end of the fourth charging and discharging unit is connected with a first end of the second switching tube, the control end of the second switch tube is connected with the control output end of the second switch, and the second end of the second switch tube and the second end of the first switch tube are connected with the boost sawtooth wave output end.

6. The sawtooth generation circuit of claim 5 wherein the logic control circuit further comprises a D flip-flop, a first AND gate, and a second AND gate;

the clock input end of the D trigger is connected with the clock signal input end, the data input end of the D trigger is connected with the second output end of the D trigger, the first output end of the D trigger is respectively connected with the second switch control output end and the first input end of the first AND gate, the clock input end of the D trigger is respectively connected with the second input end of the first AND gate and the second input end of the second AND gate, the output end of the first AND gate is connected with the first charge-discharge control output end, the second output end of the D trigger is respectively connected with the first input end of the second AND gate and the first switch control output end, and the output end of the second AND gate is connected with the second charge-discharge control output end.

7. The sawtooth wave generation circuit of any one of claims 2 to 4 wherein the first to fourth charge and discharge units each further comprise a discharge switch and a capacitor;

the first end of the discharge switch tube is connected with the charging end and the first end of the capacitor respectively, the first end of the capacitor is connected with the charging voltage output end, the control end of the discharge switch tube is connected with the control signal input end, and the second end of the discharge switch tube and the second end of the capacitor are connected with the grounding end.

8. The sawtooth wave generating circuit as claimed in claim 7, wherein the discharge switch is an N-channel MOS transistor, a drain of the N-channel MOS transistor is a first terminal of the discharge switch, a source of the N-channel MOS transistor is a second terminal of the discharge switch, and a gate of the N-channel MOS transistor is a control terminal of the discharge switch.

9. The sawtooth wave generation circuit of any one of claims 2 to 4 wherein the current mirror module comprises a current input, a third switching tube, a fourth switching tube, a fifth switching tube, a sixth switching tube and a seventh switching tube;

the current input end is connected to a current source, the second end of the third switching tube is connected with the current input end, the control end of the third switching tube, the second end of the third switching tube, the control end of the fourth switching tube, the control end of the fifth switching tube and the control end of the sixth switching tube are all connected with the control end of the seventh switching tube, the first end of the third switching tube, the first end of the fourth switching tube, the first end of the fifth switching tube and the first end of the sixth switching tube are all connected with the first end of the seventh switching tube, the first end of the seventh switching tube is connected to a power supply, and the second ends of the fourth to seventh switching tubes are respectively connected with the charging ends of the first to fourth charging and discharging units in a one-to-one correspondence manner.

10. A buck-boost converter comprising a sawtooth wave generation circuit as claimed in any one of claims 1 to 9.

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