JP3097383B2 - Power semiconductor device - Google Patents
Power semiconductor deviceInfo
- Publication number
- JP3097383B2 JP3097383B2 JP05087080A JP8708093A JP3097383B2 JP 3097383 B2 JP3097383 B2 JP 3097383B2 JP 05087080 A JP05087080 A JP 05087080A JP 8708093 A JP8708093 A JP 8708093A JP 3097383 B2 JP3097383 B2 JP 3097383B2
- Authority
- JP
- Japan
- Prior art keywords
- wire
- power semiconductor
- bonding
- electrode
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/4501—Shape
- H01L2224/45012—Cross-sectional shape
- H01L2224/45015—Cross-sectional shape being circular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4943—Connecting portions the connecting portions being staggered
- H01L2224/49431—Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01028—Nickel [Ni]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01042—Molybdenum [Mo]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/20—Parameters
- H01L2924/207—Diameter ranges
- H01L2924/2076—Diameter ranges equal to or larger than 100 microns
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
【0001】[0001]
【産業上の利用分野】本発明はパワー半導体装置に関
し、とくに大電流を通電しても高信頼性の得られるワイ
ヤボンデイング材料,構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power semiconductor device and, more particularly, to a wire bonding material and a structure capable of obtaining high reliability even when a large current is applied.
【0002】[0002]
【従来の技術】従来からIGBT,GTO,パワートラ
ンジスタなどのパワー半導体スイッチング素子が絶縁容
器内に封入されたパワー半導体モジュールが知られてい
る。これらの素子は、その耐圧や電流容量に応じて各種
インバータ装置などに応用されている。中でもIGBT
は電圧制御素子のため制御が容易であり、大電流の高周
波動作が可能なことから近年注目されている素子であ
る。パワー半導体モジュールはインバータ装置に応用さ
れることが多いため、素子としては前記IGBTとフリ
ーホイール用のダイオードが同一モジュール内に並列に
設置されることが多い。また、パワー半導体モジュール
を大容量化するためにはパワー半導体素子を数個ないし
それ以上同一モジュール内に並列して配置する必要があ
る。ダイオード或いはIGBTのアルミ電極表面と共通
電極,制御電極とは太さ500μmから300μmのワ
イヤで超音波接続されている。2. Description of the Related Art A power semiconductor module in which a power semiconductor switching element such as an IGBT, a GTO, or a power transistor is sealed in an insulating container has been known. These elements are applied to various inverter devices and the like according to their withstand voltage and current capacity. IGBT among them
Is an element that has attracted attention in recent years because it is easy to control because it is a voltage control element and is capable of high-frequency operation with a large current. Since the power semiconductor module is often applied to an inverter device, the IGBT and the diode for freewheel are often installed in the same module in parallel as elements. Further, in order to increase the capacity of the power semiconductor module, it is necessary to arrange several or more power semiconductor elements in parallel in the same module. The surface of the diode or IGBT aluminum electrode is ultrasonically connected to the common electrode and the control electrode by a wire having a thickness of 500 μm to 300 μm.
【0003】IGBTモジュールを大電流化するため、
またインバータ装置に適用するためIGBTチップ,ダ
イオードチップを同一モジュール内に数個並列に配置さ
れる。しかし、大電流の繰り返し通電により、Siチッ
プ,ワイヤに温度上昇,下降が生じる。これに伴って、
SiとAlの熱膨張係数の差に基づく、繰り返し熱応力
がワイヤ/Si界面に発生する。熱応力は通電電流が大
きい程、すなわち温度上昇の程度が大きい程大きい。こ
の応力により、特に冷却時に、Alワイヤ/Al電極膜
界面の初期クラックが進展していき、ワイヤが破断する
という問題がある。To increase the current of an IGBT module,
Further, several IGBT chips and diode chips are arranged in parallel in the same module for application to the inverter device. However, due to the repetitive energization of a large current, the temperature of the Si chip and the wire rises and falls. Along with this,
Repeated thermal stress is generated at the wire / Si interface based on the difference between the thermal expansion coefficients of Si and Al. The thermal stress increases as the energizing current increases, that is, as the degree of temperature rise increases. Due to this stress, there is a problem that an initial crack at the interface of the Al wire / Al electrode film develops, particularly during cooling, and the wire breaks.
【0004】[0004]
【発明が解決しようとする課題】従来の太さのAlワイ
ヤではAlとAl膜の接合面積を充分に大きく出来ず接
合強度を充分に高くできなかった。500μm以下のワ
イヤでは接合強度を高くしようとしてつぶれ幅を大きく
しても、つぶれ幅Wに対する接合長さLの比が0.9 以
上になると、真実接合面積は増加せず、つぶれ幅のみが
増加し、接合形状不良になるという問題がある。またダ
メージもおこりやすい。接合面積が小さい、すなわち接
合強度が低いと、使用時の繰り返し熱応力により、Al
ワイヤ/Al膜界面の初期クラックが進行することによ
るワイヤ破断時間が短い、すなわち高い信頼性を保証で
き無くなる。さらに、500μm以下のワイヤ、特に30
0μmワイヤの場合は、繰り返し通電によるワイヤ発熱
により、ワイヤの温度は数十度上昇し、これが伝熱によ
りAlワイヤ接合部にも伝達される。接合部の温度が高
いほど、熱応力は高い、すなわちクラック進展速度は大
きくなる為、ワイヤは太い方が好ましい。With the conventional thick Al wire, the bonding area between the Al and the Al film cannot be made sufficiently large and the bonding strength cannot be made sufficiently high. For wires of 500 μm or less, even if the crushing width is increased to increase the bonding strength, if the ratio of the bonding length L to the crushing width W becomes 0.9 or more, the true bonding area does not increase, only the crushing width increases. However, there is a problem that the joint shape becomes poor. Damage is also easy to occur. When the bonding area is small, that is, when the bonding strength is low, due to repeated thermal stress during use, Al
The wire breakage time due to the progress of the initial crack at the wire / Al film interface is short, that is, high reliability cannot be guaranteed. Furthermore, wires of 500 μm or less, especially 30
In the case of a 0 μm wire, the temperature of the wire rises by several tens of degrees due to the heat generated by the repeated energization, and this is also transmitted to the Al wire joint by heat transfer. The higher the temperature of the joint, the higher the thermal stress, that is, the higher the rate of crack propagation.
【0005】本発明の目的は実使用時の大電流繰り返し
通電によってもAlワイヤ剥がれのない、高信頼性を有
するパワーモジュールを提供することにある。It is an object of the present invention to provide a highly reliable power module that does not peel off the Al wire even when a large current is repeatedly applied during actual use.
【0006】[0006]
【課題を解決するための手段】実使用時の繰り返し応力
による初期クラックの進展速度を小さくするとともに接
合面積をできるだけ大きくしてワイヤ破断までの時間を
できるだけ長くするために550μmのAlワイヤを使
用した点に本発明の特徴がある。すなわち、複数個のI
GBTチップ及びダイオードチップと、これらのチップ
が搭載された第1の共通電極と、前記第1の共通電極に
接続ないし一体化された第1の内部端子及び容器表面の
第1の外部主端子と、前記IGBTチップ及びダイオー
ドチップのAl電極表面に複数本のAlワイヤによって
接続された第2の共通電極と、前記第2の共通電極に接
続ないし一体化された第2の内部端子及び容器表面の第
2の外部端子と、前記パワー半導体チップのAl電極表
面に複数本のAlワイヤによって接続された制御電極
と、前記制御電極に接続ないし一体化された内部制御端
子及び容器表面の外部制御端子と、前記第2の共通電極
に接続ないし一体化された内部補助端子および容器表面
の外部補助端子と、これらの電極などを絶縁する絶縁
板,絶縁樹脂及び絶縁容器を有するパワー半導体におい
て、Alワイヤは直径550μmであり、接合長さは5
00から800μmの範囲でありかつつぶれ幅の接合部
長さに対する比が0.9 以上で、Al電極はAl−1w
t%合金膜であるようにした。In order to reduce the growth rate of the initial crack due to the repetitive stress in actual use, to increase the bonding area as much as possible, and to make the time until the wire break as long as possible, a 550 μm Al wire was used. There is a feature of the present invention in this point. That is, a plurality of I
A GBT chip and a diode chip, a first common electrode on which these chips are mounted, a first internal terminal connected to or integrated with the first common electrode, and a first external main terminal on the surface of the container. A second common electrode connected to the surface of the Al electrode of the IGBT chip and the diode chip by a plurality of Al wires; a second internal terminal connected to or integrated with the second common electrode; A second external terminal, a control electrode connected to the Al electrode surface of the power semiconductor chip by a plurality of Al wires, an internal control terminal connected to or integrated with the control electrode, and an external control terminal on the container surface. An internal auxiliary terminal connected to or integrated with the second common electrode and an external auxiliary terminal on the surface of the container; In the power semiconductor having a vessel, Al wire has a diameter of 550 .mu.m, the junction length is 5
In the range of 00 to 800 μm, the ratio of the wobble width to the joint length is 0.9 or more, and the Al electrode is Al-1w.
It was a t% alloy film.
【0007】[0007]
【作用】直径550μmワイヤを用い、つぶれ幅の接合
長さに対する比を0.9 以上にすることにより、500
μmワイヤに比べ接合強度を1.2 倍以上高く出来る。
これは、ワイヤを太くすることにより、Siチップへの
応力集中を緩和できるため、チップダメージを発生させ
ることなくワイヤつぶれを大きく出来、その結果接合強
度を高く出来る。さらに、ワイヤ径を太くすることによ
り、ワイヤ発熱による温度上昇をすくなく出来るため、
接合部に発生する熱応力を小さく出来る。このことによ
り、接合部の熱疲労寿命を従来に比べ一段と向上させる
ことが出来る。By using a 550 μm diameter wire and setting the ratio of the collapse width to the joint length to 0.9 or more, 500
The bonding strength can be 1.2 times or more higher than that of a μm wire.
This is because, by making the wire thicker, stress concentration on the Si chip can be reduced, so that the wire crush can be increased without causing chip damage, and as a result, the bonding strength can be increased. Furthermore, by increasing the wire diameter, the temperature rise due to the heat generated by the wire can be minimized,
Thermal stress generated at the joint can be reduced. As a result, the thermal fatigue life of the joint can be further improved as compared with the related art.
【0008】[0008]
【実施例】以下本発明の実施例を図面を用いて説明す
る。図1は各ボンデイングワイヤで超音波ボンデイング
したときのせん断強度に及ぼすW/L(W:つぶれ幅、
L:接合長さ)の影響を示している。ここでLは700
μmである。図2はダメージ発生率に及ぼすW/Lの影
響を示している。500μmワイヤの場合、W/Lが
0.8以上になると接合強度は飽和する傾向を示す。ま
た、W/Lが0.9以上になると、ダメージも発生す
る。このことから、500μmワイヤでの接合強度の最
大値は3.3kg 程度であることが解る。一方、550μ
mワイヤのばあい、ダメージはW/Lが1.3以上にな
らないと発生せず、1.2のときの接合強度は4.7kgに
も達する。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows the effect of W / L (W: collapse width, on the shear strength when ultrasonic bonding is performed with each bonding wire).
L: bond length). Where L is 700
μm. FIG. 2 shows the effect of W / L on the damage occurrence rate. In the case of a 500 μm wire, when W / L is 0.8 or more, the bonding strength tends to be saturated. When W / L is 0.9 or more, damage occurs. From this, it is understood that the maximum value of the bonding strength with a 500 μm wire is about 3.3 kg. On the other hand, 550μ
In the case of the m-wire, damage does not occur unless the W / L is 1.3 or more, and the bonding strength at 1.2 is as high as 4.7 kg.
【0009】また、550μmワイヤでは、W/Lが
0.9 以上でないと高い接合強度は得られない。従っ
て、最適W/Lとしては0.9−1.2がよい。550μ
mワイヤにおいてW/L大きくても、ダメージが発生し
ないのは、接合時におけるSiチップの応力集中の度合
が500μmの場合に比べ、小さいことによると考えら
れる。[0009] In the case of a 550 µm wire, high bonding strength cannot be obtained unless W / L is 0.9 or more. Therefore, 0.9-1.2 is preferable as the optimum W / L. 550μ
It is considered that the reason why no damage occurs even if the W / L is large in the m wire is that the degree of stress concentration of the Si chip at the time of bonding is smaller than that in the case of 500 μm.
【0010】図3はワイヤボンディング部を拡大した模
式図を示したものである。本発明で述べるつぶれ幅とは
Wをさし、接合長さとはLをさしている。550μmワ
イヤではこのWが大きく、接合面積が大きくなると共
に、ワイヤの長さ方向におけるクラック進展の抵抗にな
ると考えられる。FIG. 3 is an enlarged schematic view of the wire bonding portion. The collapse width described in the present invention refers to W, and the joint length refers to L. In the case of a 550 μm wire, this W is large, so that the bonding area is increased, and it is considered that this becomes a resistance to crack propagation in the length direction of the wire.
【0011】図4はW/Lが1.0 のときのせん断強度
に及ぼす接合長さの影響を示している。500μmから
800μmの範囲で最も高いせん断強度が得られること
がわかる。これは、800μm以上になるとツールから
Alワイヤにこれを十分に変形し、Al膜と十分に接合
するだけのエネルギーをワイヤに与えられないこと及び
500μm以下になると接合面積がかなり小さくなるこ
とによる。FIG. 4 shows the effect of the joint length on the shear strength when W / L is 1.0. It can be seen that the highest shear strength is obtained in the range of 500 μm to 800 μm. This is due to the fact that the tool is sufficiently deformed from a tool to an Al wire when the thickness is 800 μm or more, and energy cannot be given to the wire enough to bond to the Al film.
【0012】図5は本発明の一実施例であり、1個のモ
ジュール単位の平面図を示したものである。また、図6
は1個のモジュール単位の断面図を示したものである。
本実施例ではIGBTチップ101が6個、ダイオード
チップ102が2個、例えばCuからなるコレクタ共通
電極板103上に分散配置されている。各チップは例え
ばMoからなる緩衝板を挟んでコレクタ共通電極板10
3に接合されている。コレクタ共通電極板103は半田
接合部104を介してコレクタ内部端子105に接続さ
れる。コレクタ内部端子105は折れ曲がっており立ち
上がり部106から図1では紙面に垂直方向に内部端子
がある。エミッタ電極107は絶縁板108を介してコ
レクタ共通電極板103の周縁部に存在し、コレクタ内
部端子と対抗した位置で立上り部109からエミッタ内
部端子110に接続している。ダイオードチップ102
はIGBTチップ101よりエミッタ内部端子110に
近接して配置されている。また、ゲート電極111はコ
レクタ内部端子105とエミッタ内部端子110を結ぶ
軸上にあり、絶縁板112を介して接合されている。ゲ
ート内部端子は立上り部113で電極と接続している。
ゲート,エミッタ内部端子114,115は2本で、エ
ミッタ端子とコレクタ端子を結ぶ軸についてほぼ対称に
配置されている。6個のIGBTチップと2個のダイオ
ードチップはそれぞれ半分ずつゲート電極111の両側
に配置されている。また、チップ及び電極,端子などは
コレクタ内部端子105とエミッタ内部端子110を結
ぶ軸についてほぼ対称に配置されている。チップ表面と
各Niめっき層を有する電極は直径550μmAlワイ
ヤによって超音波接続されている。ここでつぶれ幅Wに
対する接合長さLの比は0.9−1.2の範囲にある。FIG. 5 shows an embodiment of the present invention, and shows a plan view of one module unit. FIG.
Is a sectional view of one module unit.
In this embodiment, six IGBT chips 101 and two diode chips 102 are dispersedly arranged on a collector common electrode plate 103 made of, for example, Cu. Each chip has a collector common electrode plate 10 with a buffer plate made of Mo interposed therebetween.
3. Collector common electrode plate 103 is connected to collector internal terminal 105 via solder joint 104. The collector internal terminal 105 is bent, and there is an internal terminal in a direction perpendicular to the plane of FIG. The emitter electrode 107 is present at the periphery of the collector common electrode plate 103 via the insulating plate 108, and is connected from the rising portion 109 to the emitter internal terminal 110 at a position opposed to the collector internal terminal. Diode chip 102
Are arranged closer to the emitter internal terminal 110 than the IGBT chip 101. Further, the gate electrode 111 is on an axis connecting the collector internal terminal 105 and the emitter internal terminal 110, and is joined via an insulating plate 112. The gate internal terminal is connected to the electrode at the rising portion 113.
There are two gate and emitter internal terminals 114 and 115, which are arranged substantially symmetrically about an axis connecting the emitter terminal and the collector terminal. Six IGBT chips and two diode chips are respectively arranged on both sides of the gate electrode 111 by half. The chip, electrodes, terminals and the like are arranged substantially symmetrically with respect to an axis connecting the collector internal terminal 105 and the emitter internal terminal 110. The chip surface and the electrode having each Ni plating layer are ultrasonically connected by a 550 μm diameter Al wire. Here, the ratio of the joint length L to the crush width W is in the range of 0.9-1.2.
【0013】図7は各ワイヤで超音波接続したモジュー
ルに正弦半波の大電流を与え、各サイクル毎に接続強度
を測定し、これらの結果をまとめたものである。ここで
電流の幅は10msであり、ピーク電流の値は300A
である。接合強度は、ワイヤをせん断試験機で横から静
かに押して、ワイヤが破断する強度とした。各ワイヤの
接合強度はサイクル数と共に低下して行くことが解る。
しかし20kサイクル後の強度は550μmのそれがも
っとも高く、例えば接合強度1.5kg で比較したときの
寿命は500μmの約2倍程度高いと推定される。FIG. 7 shows a result obtained by applying a large half-sine current to a module ultrasonically connected with each wire, measuring the connection strength at each cycle, and summing up the results. Here, the width of the current is 10 ms, and the value of the peak current is 300 A
It is. The bonding strength was determined as the strength at which the wire was broken by gently pushing the wire from the side with a shear tester. It can be seen that the bonding strength of each wire decreases with the number of cycles.
However, the strength after 20 k cycles is the highest at 550 μm, and for example, it is estimated that the life when compared with a bonding strength of 1.5 kg is about twice as long as 500 μm.
【0014】[0014]
【発明の効果】以上述べたように、本発明によれば、5
50μmの太さのワイヤを用い、接合長さを500〜8
00μmの範囲とし、かつ、つぶれ幅の接合長さに対す
る比を0.9−1.2にすることにより、従来に比べ接合
強度が高く、しかも実使用時におけるワイヤ発熱がすく
ないことによる接合部温度上昇のすくない、すなわち、
ワイヤボンデイング部が断線しにくい高信頼性のパワー
モジュールが得られる。さらに、接合面積が大きいた
め、接合部の電流密度もすくないので、Al電極膜のエ
レクトロマイグレーションによる断線がおこりにくい。
また、Siチップの応力集中も起こりにくく、ボンデイ
ングダメージが発生しにくいという効果がある。As described above, according to the present invention, 5
Using a wire having a thickness of 50 μm, the joining length is 500 to 8
By setting the ratio of the crushing width to the bonding length to 0.9-1.2 in the range of 00 μm, the bonding strength is higher than in the past, and the temperature of the bonding portion due to less wire heat generation in actual use. Not ascending, that is,
A highly reliable power module in which the wire bonding portion is hardly broken can be obtained. Furthermore, since the junction area is large, the current density at the junction is also low, so that the Al electrode film hardly breaks due to electromigration.
In addition, there is an effect that stress concentration of the Si chip hardly occurs and bonding damage hardly occurs.
【図1】せん断強度とつぶれ幅との関係を示す図であ
る。FIG. 1 is a diagram showing the relationship between shear strength and crush width.
【図2】ダメージ発生率を示す図である。FIG. 2 is a diagram showing a damage occurrence rate.
【図3】ワイヤボンデイング部の拡大摸式図である。FIG. 3 is an enlarged schematic diagram of a wire bonding unit.
【図4】接合長さとせん断強度の関係を示す図である。FIG. 4 is a diagram showing a relationship between a joining length and a shear strength.
【図5】本発明の一実施例であるパワー半導体装置を示
す図である。FIG. 5 is a diagram showing a power semiconductor device according to one embodiment of the present invention.
【図6】本発明の一実施例であるパワー半導体装置の断
面図である。FIG. 6 is a cross-sectional view of a power semiconductor device according to one embodiment of the present invention.
【図7】信頼性試験結果を示す図である。FIG. 7 is a diagram showing the results of a reliability test.
101…IGBT、102…ダイオード、103…コレ
クタ共通電極、104…半田接合部、105…コレクタ
内部端子、106,109,113…立ち上がり部、1
07…エミッタ電極、108…エミッタ,絶縁板、11
0…エミッタ内部端子、111…ゲート電極、112…
ゲート絶縁板、114,115…ゲートエミッタ内部端
子、116…550μmAlワイヤ、118…絶縁板。101: IGBT, 102: diode, 103: collector common electrode, 104: solder joint, 105: collector internal terminal, 106, 109, 113: rising part, 1
07 ... emitter electrode, 108 ... emitter, insulating plate, 11
0 ... emitter internal terminal, 111 ... gate electrode, 112 ...
Gate insulating plate, 114, 115: Gate emitter internal terminal, 116: 550 μm Al wire, 118: Insulating plate.
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平5−29371(JP,A) 特開 平1−319950(JP,A) 特開 昭52−87361(JP,A) 特開 昭60−95953(JP,A) 特開 平4−85843(JP,A) 特開 平4−94141(JP,A) 特開 昭60−148132(JP,A) (58)調査した分野(Int.Cl.7,DB名) H01L 21/60 301 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-5-29371 (JP, A) JP-A-1-319950 (JP, A) JP-A-52-87361 (JP, A) JP-A-60-1985 95953 (JP, A) JP-A-4-85843 (JP, A) JP-A-4-94141 (JP, A) JP-A-60-148132 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 21/60 301
Claims (2)
素子外部の電極とを複数本の金属ワイヤによって接続し
たパワー半導体において、前記金属ワイヤはアルミニウ
ムで、直径550μmであり、接合長さは500から8
00μmの範囲にあり、かつつぶれ幅の接合部長さに対
する比が0.9−1.2の範囲にあることを特徴とするパ
ワー半導体装置。An Al electrode surface on a power semiconductor chip;
In a power semiconductor in which electrodes outside the element are connected by a plurality of metal wires, the metal wires are made of aluminum, have a diameter of 550 μm, and have a bonding length of 500 to 8 mm.
A power semiconductor device, wherein the ratio is in the range of 00 μm, and the ratio of the width of the bumps to the length of the junction is in the range of 0.9 to 1.2.
ッカース硬度で25以下Al電極はAl−1wt%Si
合金膜であり、Al合金膜の平均結晶粒径は5μm以上
であることを特徴とするパワー半導体装置。2. The aluminum wire according to claim 1, wherein the hardness of the Al wire is 25 or less in Vickers hardness.
A power semiconductor device, which is an alloy film, wherein an average crystal grain size of the Al alloy film is 5 μm or more.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP05087080A JP3097383B2 (en) | 1993-04-14 | 1993-04-14 | Power semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP05087080A JP3097383B2 (en) | 1993-04-14 | 1993-04-14 | Power semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH06302639A JPH06302639A (en) | 1994-10-28 |
JP3097383B2 true JP3097383B2 (en) | 2000-10-10 |
Family
ID=13904974
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP05087080A Expired - Fee Related JP3097383B2 (en) | 1993-04-14 | 1993-04-14 | Power semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3097383B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009071043A (en) * | 2007-09-13 | 2009-04-02 | Toyota Motor Corp | Semiconductor device and wire bonding method |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005310844A (en) | 2004-04-16 | 2005-11-04 | Toshiba Corp | Power semiconductor module |
DE102005028951B4 (en) | 2005-06-22 | 2018-05-30 | Infineon Technologies Ag | Arrangement for the electrical connection of a semiconductor circuit arrangement with an external contact device |
JP4212641B1 (en) * | 2008-08-05 | 2009-01-21 | 田中電子工業株式会社 | Aluminum ribbon for ultrasonic bonding |
JP5577628B2 (en) * | 2009-06-05 | 2014-08-27 | トヨタ自動車株式会社 | Semiconductor device |
WO2011132670A1 (en) * | 2010-04-19 | 2011-10-27 | 本田技研工業株式会社 | Wire bonding method for power semiconductor device |
JP5804644B2 (en) * | 2012-02-21 | 2015-11-04 | 超音波工業株式会社 | Ultrasonic wire bonding apparatus and ultrasonic wire bonding method |
JP7305587B2 (en) | 2020-03-17 | 2023-07-10 | 株式会社東芝 | Semiconductor equipment and inspection equipment |
CN115662975A (en) * | 2022-10-27 | 2023-01-31 | 北京智慧能源研究院 | Power chip packaging structure |
-
1993
- 1993-04-14 JP JP05087080A patent/JP3097383B2/en not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009071043A (en) * | 2007-09-13 | 2009-04-02 | Toyota Motor Corp | Semiconductor device and wire bonding method |
JP4501977B2 (en) * | 2007-09-13 | 2010-07-14 | トヨタ自動車株式会社 | Semiconductor device and wire bonding method |
Also Published As
Publication number | Publication date |
---|---|
JPH06302639A (en) | 1994-10-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP2002110893A (en) | Semiconductor device | |
JP5214936B2 (en) | Semiconductor device | |
JP3630070B2 (en) | Semiconductor chip and semiconductor device | |
JP3097383B2 (en) | Power semiconductor device | |
JP2007109880A (en) | Semiconductor device | |
JP2016139635A (en) | Power semiconductor device | |
JP2000124398A (en) | Power semiconductor module | |
JPH088395A (en) | Mounting structure for power device chip | |
JPH0964258A (en) | Large power semiconductor device | |
JP4023032B2 (en) | Mounting structure and mounting method of semiconductor device | |
CN111326489A (en) | Power device packaging structure | |
JP2003045920A (en) | Power semiconductor device and method for manufacturing the same | |
JPH07221265A (en) | Power semiconductor module | |
JP3882734B2 (en) | Wire bonding method for power semiconductor device | |
JP2002222826A (en) | Semiconductor device and its manufacturing method | |
CN211350630U (en) | Power device packaging structure | |
JP3216305B2 (en) | Semiconductor device | |
JP2006196765A (en) | Semiconductor device | |
JP4586508B2 (en) | Semiconductor device and manufacturing method thereof | |
JPH088288A (en) | Semiconductor device | |
JP2000307043A (en) | Power semiconductor module | |
JPH09237868A (en) | Semiconductor module | |
JPH08250628A (en) | Semiconductor integrated circuit device and its manufacture | |
JP2002151646A (en) | Pressure-welding type semiconductor device | |
JPH10199923A (en) | Power semiconductor module |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20070811 Year of fee payment: 7 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080811 Year of fee payment: 8 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080811 Year of fee payment: 8 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090811 Year of fee payment: 9 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100811 Year of fee payment: 10 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100811 Year of fee payment: 10 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110811 Year of fee payment: 11 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120811 Year of fee payment: 12 |
|
LAPS | Cancellation because of no payment of annual fees |