JP3029398B2 - 半導体のチップと基板間の電気的連結構造 - Google Patents
半導体のチップと基板間の電気的連結構造Info
- Publication number
- JP3029398B2 JP3029398B2 JP8013488A JP1348896A JP3029398B2 JP 3029398 B2 JP3029398 B2 JP 3029398B2 JP 8013488 A JP8013488 A JP 8013488A JP 1348896 A JP1348896 A JP 1348896A JP 3029398 B2 JP3029398 B2 JP 3029398B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- substrate
- electrical connection
- connection structure
- conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 52
- 239000000758 substrate Substances 0.000 title claims description 48
- 229910052751 metal Inorganic materials 0.000 claims description 24
- 239000002184 metal Substances 0.000 claims description 24
- 239000000853 adhesive Substances 0.000 claims description 9
- 230000001070 adhesive effect Effects 0.000 claims description 9
- 238000007740 vapor deposition Methods 0.000 claims description 2
- 239000010949 copper Substances 0.000 description 3
- 230000003746 surface roughness Effects 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000002950 deficient Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01087—Francium [Fr]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
- H01L2924/07811—Extrinsic, i.e. with electrical conductive fillers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0347—Overplating, e.g. for reinforcing conductors or bumps; Plating over filled vias
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0364—Conductor shape
- H05K2201/0367—Metallic bump or raised conductor not used as solder bump
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0364—Conductor shape
- H05K2201/0373—Conductors having a fine structure, e.g. providing a plurality of contact points with a structured tool
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/04—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching
- H05K3/046—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching by selective transfer or selective detachment of a conductive layer
- H05K3/048—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching by selective transfer or selective detachment of a conductive layer using a lift-off resist pattern or a release layer pattern
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Description
板間の電気的連結構造に係るもので、詳しくは、基板上
のボンディングパッドにチップのバンプを確実に連結
し、電気的特性を改善して信頼性を向上し得る半導体チ
ップと基板間の電気的連結構造に関するものである。
を用いたベアーチップ(bear chip)を半導体基板上の
パッドに直接実装し電気的連結を行っている。そして、
該半導体チップに金属バンプを形成する技術は正常に広
用されていたが、該バンピングされたチップを基板上の
パッドに電気的連結する技術は未だ正常に適用されてい
ない。
的連結構造を説明すると次のようであった。即ち、図6
に示したように、FRー4ガラス叉はセラミックの基板
1が形成され、該基板1上にアルミニウムAl叉は銅C
uのボンディングパッド2が形成される。次いで、図4
に示したように、該基板1のボンディングパッド2上に
半導体チップ3の金属性バンプ4が電気的連結される
が、この場合、それら基板1のボンディングパッド2と
半導体チップ3のバンプ4間に、導電性ボール5aの包
含された異方性接着剤5のACA(anisotropic conduc
tive adhesive)叉はACF(anisotropic conductive
film)を注入し、該異方性接着剤5の温度及び圧力を調
節しながら熱硬化させ、それら導電性ボール5aのZー
軸方向への電気伝導を可能にさせる。即ち、前記基板1
上のパッド2と半導体チップ3のバンプ4間の電気的連
結が導電性ボール5aを介して行われるように半導体チ
ップと基板間の電気的連結構造が構成されていた。
基板1上のパッド2上面と半導体チップ3のバンプ下面
との表面粗度及び傾斜等に従い、それら基板のパッド2
と半導体チップのバンプ間の電気的連結が導電性ボール
5aを介して確実に行われない場合が発生していた。
来半導体のチップと基板間の電気的連結構造において
は、基板のパッド上面とチップのバンプ下面との表面粗
度及び傾斜等に従い、それらパッド上面とバンプ下面間
に導電性ボールが正確に接続されない場合が発生し半導
体のチップと基板間の電気的連結が確実に行われないと
いう不都合な点があった。
チップのバンプ下面と基板上パッドとの表面粗度及び傾
斜度には拘わりなく半導体チップと基板上パッドとの電
気的連結を確実に行い得る半導体チップと基板間の電気
的連結構造を提供しようとするものである。
間の電気的連結構造は、半導体基板上のボンディングパ
ッド上面に蒸着法を施して複数の微細な導電性金属突条
を夫々形成し、それら導電性金属突条上面に半導体チッ
プのバンプをボンディングしてなり、導電性金属突条と
半導体チップのバンプ間に導電性ボールを掛合させ、該
導電性ボールを介して電気的連結させる。請求項2の発
明による半導体チップと基板間の電気的連結構造は、請
求項1の発明の構成において、導電性ボールは、それら
導電性金属突条と半導体チップのバンプ間に導電性ボー
ルの包含された異方性接着剤を注入して形成掛合させ
る。請求項3の発明による半導体チップと基板間の電気
的連結構造は、請求項1または請求項2の発明の構成に
おいて、導電性金属突条は、高さが3μm程度に形成さ
れる。
図面を用いて説明する。本発明に係る半導体チップと基
板間の電気的連結構造においては、図1(A)に示した
ように、先ず、FRーガラス叉はセラミックを用いた基
板10が形成され、該基板10上所定部位にアルミニウ
ムAl叉は銅Cuを用いたボンディングパッド12が形
成される。次いで、図1(B)に示したように、該基板
10及びパッド12上に感光膜14がコーティングさ
れ、図1(c)に示したように、該感光膜14が感光性
マスクにより部分的に露出及び現像され、前記ボンディ
ングパッド12上に所望パターンの凹凸部位が形成され
る。次いで、図1(D)に示したように、それら感光膜
14及び基板10上に蒸着(evaporation)、スパッタ
リング及び電気鍍金中何れ一つの方法により導電性金属
16’が蒸着(deposition)される。次いで、図1
(E)に示したように、該感光膜14と該感光膜14上
の導電性金属16’とが夫々除去され、基板10のボン
ディングパッド12上面に所定パターンの微細な導電性
金属突条16が夫々形成される。この場合、該導電性金
属突条16の高さは、3μmの高さに形成することが好
ましい。
形成された半導体基板10のボンディング12上の各信
頼性金属突条16上面に、第1実施形態として、半導体
チップ13のバンプ24底面を熱圧着し、半導体のチッ
プと基板間の電気的連結構造を構成する。
間の電気的連結構造の第2実施形態として次のように構
成することもできる。即ち、図3に示したように、前記
第1実施形態と同様に形成された半導体基板10のボン
ディングパッド12上の各導電性金属突条16と、前記
半導体チップ13のバンプ24下面との間に、導電性ボ
ール15aの包含された異方性接着剤のACA叉はAC
Fを注入し、該異方性接着剤の温度及び圧力を調節しな
がら熱硬化させて導電性ボール15aをそれらの間に形
成掛合させ、該導電性ボール15aを介して導電性金属
突条16とバンプ24間の電気的連結が行われるように
半導体のチップと基板間の電気的連結構造を構成するこ
ともできる。この場合、それら導電性ボール15aは、
導電性金属突条16とバンプ24間に該導電性ボール1
5aの形が歪みながら掛合され、電気的に連結される。
体のチップと基板間の電気的連結構造においては、基板
上のボンディングパッド上面に複数の微細な導電性金属
突条を形成し、それら導電性金属突条上面に半導体チッ
プのバンプを直接ボンディングするか、叉は異方性接着
剤を用い導電性ボールを介してボンディングするように
なっているため、半導体チップと基板間の電気的連結を
接続不良無しに確実に行い電気的特性を改善させて製品
の信頼性を向上し得るという効果がある。
基板間の電気的連結構造形成説明図である。
連結構造の第1実施形態を示した縦断面図である。
連結構造の第2実施形態を示した縦断面図である。
を示した縦断面図である。
の不良状態表示図である。
面図である。
Claims (3)
- 【請求項1】 半導体チップと基板間の電気的連結構造
であって、 半導体基板上のボンディングパッド上面に蒸着法を施し
て複数の微細な導電性金属突条を夫々形成し、それら導
電性金属突条上面に半導体チップのバンプをボンディン
グしてなり、 前記導電性金属突条と前記半導体チップの前記バンプ間
に導電性ボールを掛合させ、該導電性ボールを介して電
気的連結させる、半導体チップと基板間の電気的連結構
造。 - 【請求項2】 前記導電性ボールは、それら導電性金属
突条と半導体チップのバンプ間に導電性ボールの包含さ
れた異方性接着剤を注入して形成掛合させる、請求項1
記載の半導体チップと基板間の電気的連結構造。 - 【請求項3】 前記導電性金属突条は、高さが3μm程
度に形成される、請求項1または請求項2に記載の半導
体チップと基板間の電気的連結構造。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR95P36166 | 1995-10-19 | ||
KR1019950036166A KR100206866B1 (ko) | 1995-10-19 | 1995-10-19 | 반도체 장치 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH09129669A JPH09129669A (ja) | 1997-05-16 |
JP3029398B2 true JP3029398B2 (ja) | 2000-04-04 |
Family
ID=19430679
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8013488A Expired - Fee Related JP3029398B2 (ja) | 1995-10-19 | 1996-01-30 | 半導体のチップと基板間の電気的連結構造 |
Country Status (3)
Country | Link |
---|---|
US (1) | US5731636A (ja) |
JP (1) | JP3029398B2 (ja) |
KR (1) | KR100206866B1 (ja) |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH10209210A (ja) | 1997-01-20 | 1998-08-07 | Sharp Corp | 半導体装置及びその製造方法並びにその検査方法 |
US6177729B1 (en) | 1999-04-03 | 2001-01-23 | International Business Machines Corporation | Rolling ball connector |
US6251694B1 (en) * | 1999-05-26 | 2001-06-26 | United Microelectronics Corp. | Method of testing and packaging a semiconductor chip |
US6853067B1 (en) | 1999-10-12 | 2005-02-08 | Microassembly Technologies, Inc. | Microelectromechanical systems using thermocompression bonding |
US6242815B1 (en) | 1999-12-07 | 2001-06-05 | Advanced Semiconductor Engineering, Inc. | Flexible substrate based ball grid array (BGA) package |
US20020096421A1 (en) * | 2000-11-29 | 2002-07-25 | Cohn Michael B. | MEMS device with integral packaging |
WO2003010813A2 (en) * | 2001-07-23 | 2003-02-06 | Clayton Gary A | Grid interposer |
US20030116346A1 (en) * | 2001-12-21 | 2003-06-26 | Forster James Allam | Low cost area array probe for circuits having solder-ball contacts are manufactured using a wire bonding machine |
US7015590B2 (en) | 2003-01-10 | 2006-03-21 | Samsung Electronics Co., Ltd. | Reinforced solder bump structure and method for forming a reinforced solder bump |
US8518304B1 (en) | 2003-03-31 | 2013-08-27 | The Research Foundation Of State University Of New York | Nano-structure enhancements for anisotropic conductive material and thermal interposers |
FR2866753B1 (fr) * | 2004-02-25 | 2006-06-09 | Commissariat Energie Atomique | Dispositif microelectronique d'interconnexion a tiges conductrices localisees |
US7692521B1 (en) | 2005-05-12 | 2010-04-06 | Microassembly Technologies, Inc. | High force MEMS device |
US20070045647A1 (en) * | 2005-09-01 | 2007-03-01 | Wintek Corporation | Display panel package |
KR101485105B1 (ko) * | 2008-07-15 | 2015-01-23 | 삼성전자주식회사 | 반도체 패키지 |
TWM408126U (en) * | 2010-12-10 | 2011-07-21 | Chunghwa Picture Tubes Ltd | Conductive pad structure, chip package structure and active device array substrate |
TWI462194B (zh) * | 2011-08-25 | 2014-11-21 | Chipmos Technologies Inc | 半導體封裝結構及其製作方法 |
KR20130076399A (ko) * | 2011-12-28 | 2013-07-08 | 삼성디스플레이 주식회사 | 디스플레이 장치 |
KR101513642B1 (ko) * | 2013-08-21 | 2015-04-20 | 엘지전자 주식회사 | 반도체 디바이스 |
US20160093583A1 (en) * | 2014-09-25 | 2016-03-31 | Micron Technology, Inc. | Bond pad with micro-protrusions for direct metallic bonding |
CN110430687A (zh) * | 2019-07-15 | 2019-11-08 | 宁波华远电子科技有限公司 | 一种精密对位电镀凸台的制作方法 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4731282A (en) * | 1983-10-14 | 1988-03-15 | Hitachi Chemical Co., Ltd. | Anisotropic-electroconductive adhesive film |
US4740657A (en) * | 1986-02-14 | 1988-04-26 | Hitachi, Chemical Company, Ltd | Anisotropic-electroconductive adhesive composition, method for connecting circuits using the same, and connected circuit structure thus obtained |
US5189507A (en) * | 1986-12-17 | 1993-02-23 | Raychem Corporation | Interconnection of electronic components |
JPS6420632A (en) * | 1987-07-15 | 1989-01-24 | Nitto Denko Corp | Conductive substrate |
US5001542A (en) * | 1988-12-05 | 1991-03-19 | Hitachi Chemical Company | Composition for circuit connection, method for connection using the same, and connected structure of semiconductor chips |
JPH06151507A (ja) * | 1992-11-10 | 1994-05-31 | Matsushita Electric Ind Co Ltd | 回路基板上の端子電極とその形成方法及び実装体 |
US5598036A (en) * | 1995-06-15 | 1997-01-28 | Industrial Technology Research Institute | Ball grid array having reduced mechanical stress |
-
1995
- 1995-10-19 KR KR1019950036166A patent/KR100206866B1/ko not_active IP Right Cessation
-
1996
- 1996-01-30 JP JP8013488A patent/JP3029398B2/ja not_active Expired - Fee Related
- 1996-04-12 US US08/631,245 patent/US5731636A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
KR970023907A (ko) | 1997-05-30 |
US5731636A (en) | 1998-03-24 |
JPH09129669A (ja) | 1997-05-16 |
KR100206866B1 (ko) | 1999-07-01 |
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