JPS6420632A - Conductive substrate - Google Patents

Conductive substrate

Info

Publication number
JPS6420632A
JPS6420632A JP17685387A JP17685387A JPS6420632A JP S6420632 A JPS6420632 A JP S6420632A JP 17685387 A JP17685387 A JP 17685387A JP 17685387 A JP17685387 A JP 17685387A JP S6420632 A JPS6420632 A JP S6420632A
Authority
JP
Japan
Prior art keywords
layer
chip
swelling
cracking
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17685387A
Other languages
Japanese (ja)
Inventor
Shozo Kawazoe
Masahide Toyooka
Yasushi Nakahira
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nitto Denko Corp
Original Assignee
Nitto Denko Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nitto Denko Corp filed Critical Nitto Denko Corp
Priority to JP17685387A priority Critical patent/JPS6420632A/en
Publication of JPS6420632A publication Critical patent/JPS6420632A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)
  • Non-Insulated Conductors (AREA)

Abstract

PURPOSE:To improve connecting operability in an electric connection of various types of packages, etc., and to prevent the package from swelling or cracking by laminating a conductive metal layer, a low melting point metal material layer on an insulating substrate. CONSTITUTION:A copper layer 3a of conductive metal is provided by vacuum vapor on an insulating substrate 1, and an indium layer 3a of low melting point metal material is laminated by vacuum depositing in response to a conductor pattern on a layer 2. When an IC chip 4 or the like is placed on the layer 3a, heated to approx. 160 deg.C, and then cooled, the chip 4 is electrically and mechanically rigidly connected to the substrate 1 through the aluminum electrode 4a of the chip 4 and a conductor pattern. With this configuration, connecting operability in the electric connection of various packages is enhanced, and it can prevent the package from swelling or cracking.
JP17685387A 1987-07-15 1987-07-15 Conductive substrate Pending JPS6420632A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17685387A JPS6420632A (en) 1987-07-15 1987-07-15 Conductive substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17685387A JPS6420632A (en) 1987-07-15 1987-07-15 Conductive substrate

Publications (1)

Publication Number Publication Date
JPS6420632A true JPS6420632A (en) 1989-01-24

Family

ID=16020975

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17685387A Pending JPS6420632A (en) 1987-07-15 1987-07-15 Conductive substrate

Country Status (1)

Country Link
JP (1) JPS6420632A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07226416A (en) * 1994-01-31 1995-08-22 Internatl Business Mach Corp <Ibm> Semiconductor chip package and its preparation
JPH09129669A (en) * 1995-10-19 1997-05-16 Lg Semicon Co Ltd Electric connection structure between semiconductor chip and substrate

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07226416A (en) * 1994-01-31 1995-08-22 Internatl Business Mach Corp <Ibm> Semiconductor chip package and its preparation
JPH09129669A (en) * 1995-10-19 1997-05-16 Lg Semicon Co Ltd Electric connection structure between semiconductor chip and substrate

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