JP2911644B2 - Circuit board - Google Patents

Circuit board

Info

Publication number
JP2911644B2
JP2911644B2 JP3142644A JP14264491A JP2911644B2 JP 2911644 B2 JP2911644 B2 JP 2911644B2 JP 3142644 A JP3142644 A JP 3142644A JP 14264491 A JP14264491 A JP 14264491A JP 2911644 B2 JP2911644 B2 JP 2911644B2
Authority
JP
Japan
Prior art keywords
metal
circuit
cracks
circuit board
ceramic substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP3142644A
Other languages
Japanese (ja)
Other versions
JPH04343287A (en
Inventor
康人 伏井
美幸 中村
好彦 辻村
克典 寺野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denka Co Ltd
Original Assignee
Denki Kagaku Kogyo KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
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Priority to JP3142644A priority Critical patent/JP2911644B2/en
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Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0201Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/38Improvement of the adhesion between the insulating substrate and the metal

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、回路基板、詳しくはセ
ラミックス基板のクラック発生とその進行を抑制するこ
とを目的とした金属回路とセラミックス基板との接合体
からなる回路基板に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board, and more particularly, to a circuit board comprising a joined body of a metal circuit and a ceramic substrate for the purpose of suppressing the occurrence and progress of cracks in a ceramic substrate.

【0002】[0002]

【従来の技術】近年、ロボットやモーター等の産業機器
の高性能化に伴い、大電力・高能率インバーターなど大
電力モジュールの変遷が進んでおり、半導体素子から発
生する熱も増加の一途をたどっている。この熱を効率よ
く放散するため、大電力モジュール基板では従来よりさ
まざまな方法がとられてきた。とくに最近、良好な熱伝
導率を有するセラミックス基板の出現により、基板上に
金属板を接合して回路を形成後、そのまま金属板上に半
導体素子を搭載する構造も採用されている。
2. Description of the Related Art In recent years, with the increase in performance of industrial equipment such as robots and motors, the transition of high-power modules such as high-power and high-efficiency inverters has been progressing, and the heat generated from semiconductor elements has been increasing steadily. ing. In order to efficiently dissipate this heat, various methods have been used for high power module substrates. Particularly, with the advent of ceramic substrates having good thermal conductivity, a structure in which a metal plate is joined to a substrate to form a circuit, and then a semiconductor element is mounted on the metal plate as it is, has recently been adopted.

【0003】従来より、金属とセラミックスを接合する
方法には様々な方法があるが、とくに回路基板の製造と
いう点からはMo−Mn法、活性金属ろう付法(以下、単に
活性金属法という)、硫化銅法、DBC 法、銅メタライズ
法があげられる。これらの中で大電力モジュール基板の
製造では、現在、金属として銅を用い、セラミックスと
の接合方法として活性金属法又はDBC 法を用いることが
主流となっており、さらに高熱伝導性を有する窒化アル
ミニウムを絶縁基板として使用することが普及しつつあ
る。
[0003] Conventionally, there are various methods for joining a metal and ceramics. In particular, from the viewpoint of manufacturing a circuit board, the Mo-Mn method and the active metal brazing method (hereinafter simply referred to as the active metal method). , Copper sulfide method, DBC method, copper metallization method. Among these, in the manufacture of high power module substrates, copper is currently used as the metal, and the active metal method or the DBC method is used as the bonding method with ceramics. It is becoming popular to use as an insulating substrate.

【0004】従来の銅板と窒化アルミニウム基板を接合
する方法としては、銅板と窒化アルミニウム基板との間
に活性金属を含むろう材を介在させ、加熱処理し接合体
を形成する活性金属法(たとえば特開昭60-177634 号公
報)や、銅板と表面を酸化処理してなる窒化アルミニウ
ム基板とを銅の融点以下、Cu2O-Oの共晶温度以上で加熱
接合するDBC 法(たとえば特開昭56-163093 号公報)な
どが知られている。
As a conventional method of joining a copper plate and an aluminum nitride substrate, an active metal method (for example, a special method) in which a brazing material containing an active metal is interposed between the copper plate and the aluminum nitride substrate and heat-treated to form a joined body. And a DBC method in which a copper plate and an aluminum nitride substrate whose surface is oxidized are heated and joined at a temperature lower than the melting point of copper and higher than the eutectic temperature of Cu 2 OO (see, for example, JP-A-56-177634). No. 163093).

【0005】活性金属法はDBC 法に比べて、 (1)接合処理温度が低いので、AlN-Cuの熱膨張差によ
って生じる残留応力が小さい。 (2)接合層が延性金属であるので、ヒートショックや
ヒートサイクルに対して耐久性が良好である。 などの利点があるが、最近のパワーモジュールの用途拡
大によって、使用条件が一段と厳しくなってきたのに伴
いさらに高い信頼性が要求されるにおよび、これまでの
ヒートサイクルとヒートショックの耐久性程度では十分
に対応しきれなくなってきている。
The active metal method has the following advantages: (1) Since the bonding temperature is lower than that of the DBC method, the residual stress caused by the difference in thermal expansion between AlN and Cu is small. (2) Since the joining layer is made of a ductile metal, it has good durability against heat shock and heat cycle. However, with the recent expansion of power module applications, the use conditions have become more severe and higher reliability has been required. Now it is not enough to respond.

【0006】そこで、金属回路とセラミックス基板との
接合体を形成するに際し、意図的に非接合部を設けるこ
とによって接合面積を減らし、もって界面に生じる熱応
力を小さくして上記耐久性を改善しようとする提案があ
る(特開昭61-176142 号公報)。しかし、この方法では
非接合部に溜まったエッチング液やメッキ液を除去する
のが困難なために歩留りが低下する上に、DBC法では非
接合部を設けるために金属板に特殊な加工をしなければ
ならないという問題がある。
Therefore, when forming a bonded body between a metal circuit and a ceramic substrate, the bonding area is reduced by intentionally providing a non-bonded portion, thereby reducing the thermal stress generated at the interface and improving the durability. (JP-A-61-176142). However, in this method, it is difficult to remove the etching solution and plating solution accumulated in the non-joined part, so that the yield is reduced.In addition, in the DBC method, a special processing is performed on the metal plate to provide the non-joined part. There is a problem that must be.

【0007】一方、セラミックス基板に近い熱膨張係数
を有する特殊な金属を用いる提案もあるが(例えば特開
昭63-140540 号公報など)、そのようなクラッド材やモ
リブデン等の金属は高価で加工が難しく、通常のエッチ
ングができないことを考えると、非常に限られた特殊用
途にしか使用できないという問題がある。
On the other hand, there is a proposal to use a special metal having a coefficient of thermal expansion close to that of a ceramic substrate (for example, Japanese Patent Application Laid-Open No. 63-140540). However, such a metal as a cladding material or molybdenum is expensive and is processed. Considering that it is difficult to perform ordinary etching, there is a problem that it can be used only for a very limited special purpose.

【0008】[0008]

【発明が解決しようとする課題】本発明者らは、上記問
題点を解決するために鋭意検討した結果、金属回路にス
リットを入れることによりクラックの発生とその進行を
抑制できることを見い出し本発明を完成したものであ
る。
The inventors of the present invention have conducted intensive studies to solve the above problems, and as a result, have found that the formation of cracks and their progression can be suppressed by forming slits in a metal circuit. It is completed.

【0009】[0009]

【課題を解決するための手段】すなわち、本発明は、ス
リットを有する金属回路とセラミックス基板との接合体
からなることを特徴とする回路基板である。
That is, the present invention provides a circuit board comprising a joined body of a metal circuit having a slit and a ceramic substrate.

【0010】以下、さらに詳しく本発明について説明す
る。
Hereinafter, the present invention will be described in more detail.

【0011】本発明の最大の特徴は、従来用いられてい
る材料や工程を殆んど変更することなしに、回路パター
ンの一部にスリットを加えるだけでクラックの発生とそ
の進行の抑制に大きな効果をあげたことである。
The most significant feature of the present invention is that the addition of a slit to a part of a circuit pattern can suppress cracks and suppress the progress of the cracks without changing the conventional materials and processes. It was effective.

【0012】本発明でいうスリットとは、金属回路に設
けられた切り込み部分のことであり、長さ1mm以上、幅
0.2mm以上であるものが望ましい。また端部から切り込
まれていない孔であってもよい。さらに好ましくは、長
さは1.5mm以上特に2mm以上であり、幅は厚さ100μ
m 以上の金属板の場合には0.3mm以上特に0.4mm以上で
ある。
In the present invention, the term "slit" refers to a cut portion provided in a metal circuit and has a length of 1 mm or more and a width of 1 mm or more.
It is desirable that the thickness be 0.2 mm or more. Alternatively, the hole may not be cut from the end. More preferably, the length is 1.5 mm or more, especially 2 mm or more, and the width is 100 μm or more.
In the case of a metal plate of m or more, it is 0.3 mm or more, especially 0.4 mm or more.

【0013】本発明において、スリットを設ける位置に
ついては特に限定しないが、熱応力が大きくなる部分、
例えば長い回路パターンの長手方向の端部や電極等の半
田付け部に設けるのが望ましい。
In the present invention, the position at which the slit is provided is not particularly limited.
For example, it is desirable to provide it at a longitudinal end of a long circuit pattern or at a soldered portion such as an electrode.

【0014】スリットの形成方法としては、打ち抜き金
属板を用いる方法やエッチングによる方法等が採用され
る。打ち抜き金属板を用いる場合はあまり細長いスリッ
トを設けることは難しいので、比較的形成容易な長さの
スリットを数個にして回路パターン端部や内部に設ける
のが望ましい。また、エッチング法によって回路パター
ンを形成する場合も同様であり、その際のスリットの数
や長さ、幅等の上限は必要に応じて適宜定めることがで
きる。
As a method of forming the slit, a method using a stamped metal plate, a method by etching, or the like is employed. When a stamped metal plate is used, it is difficult to provide a slit that is too long and thin, so it is preferable to provide several slits having a length that is relatively easy to form and provide them at the end or inside of the circuit pattern. The same applies to the case where a circuit pattern is formed by an etching method, and the upper limit of the number, length, width, and the like of the slits at that time can be appropriately determined as necessary.

【0015】金属回路を形成するのに使用される金属板
の材質については特に制限はなく、通常は、銅、ニッケ
ル、銅合金、ニッケル合金が用いられる。また、その厚
みについても特に制限はなく、通常、金属箔といわれて
いる肉厚の薄いものでも使用可能であり、0.1〜1.2mm
のものが好ましい。
The material of the metal plate used to form the metal circuit is not particularly limited, and copper, nickel, copper alloy, and nickel alloy are usually used. Also, there is no particular limitation on its thickness, and it is possible to use a thin metal foil, which is usually referred to as a metal foil, in a range of 0.1 to 1.2 mm.
Are preferred.

【0016】本発明で使用されるセラミックス基板の材
質についても特に制限はなく、窒化アルミニウム(Al
N)、窒化ケイ素(Si3N4)、酸化アルミニウム(Al2O3)、
ムライト等から選ばれた少なくとも一種又は二種以上を
主成分とするものがあげられ、中でも熱伝導率の大きい
窒化アルミニウムが好ましい。
The material of the ceramic substrate used in the present invention is not particularly limited.
N), silicon nitride (Si 3 N 4 ), aluminum oxide (Al 2 O 3 ),
Examples include those containing at least one or two or more selected from mullite and the like as a main component, and among them, aluminum nitride having high thermal conductivity is preferable.

【0017】金属回路又は金属板とセラミックス基板と
の接合体を得る際の接合方法としては、上記したDBC 法
や活性金属法等を採用することができる。
As a joining method for obtaining a joined body of a metal circuit or a metal plate and a ceramic substrate, the above-described DBC method, active metal method and the like can be adopted.

【0018】[0018]

【作用】スリットを加えた部分の金属回路は、回路が分
割された場合と同じ状態になり、熱膨張の絶対値も分割
されて小さくなるので、熱応力も小さくなる。従ってク
ラックの発生が抑制され、発生しても進行しにくくな
る。
The metal circuit in the portion where the slit is added is in the same state as when the circuit is divided, and the absolute value of thermal expansion is also divided and reduced, so that the thermal stress is also reduced. Therefore, generation of cracks is suppressed, and even if they occur, they do not easily progress.

【0019】一般に、発生するクラックには、セラミッ
クス基板の厚み方向にも進行する垂直クラックと、厚み
方向にはあまり進行せずに主にセラミックス基板面と平
行に進行する水平クラックとがある。垂直クラックは、
特に大きな応力が発生した場合や応力が急激に発生した
場合、さらには衝撃を受けた場合等に生じやすく、他の
場合には水平クラックが生じやすい。水平クラックは回
路パターンの端部に沿って発生・進行して行く。半田付
け部等特にクラックが発生しやすい箇所の周囲に回路パ
ターンの沿面に垂直方向にスリットを入れておけば、ク
ラックがパターン端部に沿って進行する際に、スリット
部を回り込むために進行のエネルギーが分散され、クラ
ックが進行しにくくなる。
In general, the cracks generated include a vertical crack that progresses also in the thickness direction of the ceramic substrate, and a horizontal crack that progresses mainly in parallel with the ceramic substrate surface without progressing much in the thickness direction. Vertical cracks
In particular, when a large stress is generated, when the stress is rapidly generated, or when an impact is applied, it is likely to occur. In other cases, a horizontal crack is likely to occur. Horizontal cracks occur and progress along the edge of the circuit pattern. If a slit is made in the vertical direction along the surface of the circuit pattern, especially around a place where cracks are likely to occur, such as a soldered part, when the crack progresses along the pattern edge, Energy is dispersed, and cracks do not easily progress.

【0020】[0020]

【実施例】以下、実施例と比較例をあげてさらに具体的
に説明する。
The present invention will be described more specifically with reference to examples and comparative examples.

【0021】実施例1〜9 比較例1〜5 市販の窒化アルミニウム基板とアルミナ基板(いずれも
35mm×60mm×0.5 mm)を用い、DBC 法の場合にはタフピ
ッチ銅板を、また活性金属法の場合には無酸素銅板を接
合し表1に示す接合体を製造した。
Examples 1 to 9 Comparative Examples 1 to 5 Commercially available aluminum nitride substrates and alumina substrates (both were used)
Using a 35 mm x 60 mm x 0.5 mm), a tough pitch copper plate was bonded in the case of the DBC method, and an oxygen-free copper plate was bonded in the case of the active metal method to produce a bonded body shown in Table 1.

【0022】接合条件は、DBC 法では温度1050℃、真空
度1.0 ×10-6torrとし、一方、活性金属法の実施例3
(Zr−Ag−Cu系ろう材を使用)では900 ℃の温度で、ま
た他の活性金属法(Ti−Ag−Cu系ろう材を使用)では88
0 ℃の温度で、それぞれ真空度を1.0 ×10-6torrとし
た。なお、DBC 法で用いた窒化アルミニウム基板はあら
かじめ大気中で加熱して表面酸化されたものである。
The bonding conditions were as follows: the temperature was 1050 ° C. and the degree of vacuum was 1.0 × 10 −6 torr in the DBC method.
(Using a Zr-Ag-Cu brazing material) at a temperature of 900 ° C, and 88 with other active metal methods (using a Ti-Ag-Cu brazing material).
At a temperature of 0 ° C., the degree of vacuum was set to 1.0 × 10 −6 torr. The aluminum nitride substrate used in the DBC method had been previously oxidized by heating in air.

【0023】DBC 法ではセラミックス基板と同じ大きさ
の銅板を両面に接合し、レジスト印刷後塩化第二鉄溶液
でエッチングし、図1に示す回路パターンを形成した。
スリットなしの比較例の場合は、図1(a)の回路面の
かわりに図2の回路を用いた。活性金属法では、活性金
属を含むろう材ペーストを打ち抜き銅板に塗布して100
℃で乾燥後セラミックス基板に接合して回路パターンと
した。回路はDBC 法と同じにした。
In the DBC method, a copper plate having the same size as the ceramic substrate was bonded to both surfaces, and after resist printing, etching was performed with a ferric chloride solution to form a circuit pattern shown in FIG.
In the case of the comparative example having no slit, the circuit of FIG. 2 was used instead of the circuit surface of FIG. In the active metal method, a brazing filler metal paste containing an active metal is punched and applied to a copper plate.
After drying at ℃, it was joined to a ceramic substrate to form a circuit pattern. The circuit was the same as the DBC method.

【0024】得られた接合体は、いずれも無電解Ni−P
メッキを5μm施してヒートショック及びヒートサイク
ルの試験をした。その結果を表2に示す。
Each of the obtained joined bodies was made of an electroless Ni-P
Heat shock and heat cycle were tested by plating 5 μm. Table 2 shows the results.

【0025】ヒートショック試験は、0℃の液中に10分
間浸漬後100℃に15分間浸漬するのを1サイクルとし、3
0サイクル実施した。ヒートサイクル試験の条件は、−4
0℃で30分間冷却後25℃に30分間放置、その後125 ℃の
気中で30分間加熱してから25℃に30分間放置するのを1
サイクルとし、50サイクル行なった。
In the heat shock test, one cycle of immersion in a liquid at 0 ° C. for 10 minutes and then immersion in 100 ° C. for 15 minutes was defined as one cycle.
0 cycles were performed. Heat cycle test conditions are -4
After cooling at 0 ° C for 30 minutes, leave it at 25 ° C for 30 minutes, then heat it at 125 ° C for 30 minutes, then leave it at 25 ° C for 30 minutes.
The cycle was 50 cycles.

【0026】上記試験終了後、外観を観察して垂直クラ
ックの有無や回路パターンの剥離を調べ、クラックや剥
離のないものについてはさらに硝酸とフッ酸の1:1の
混酸に浸漬して回路を溶解剥離してセラミックス基板の
水平クラックをカラーチェック法で調べた。
After completion of the test, the appearance is observed to check for the presence of vertical cracks and peeling of the circuit pattern. If there is no crack or peeling, the circuit is further immersed in a 1: 1 mixed acid of nitric acid and hydrofluoric acid. The horizontal cracks on the ceramic substrate were examined by a color check method after dissolution and peeling.

【0027】[0027]

【表1】 [Table 1]

【0028】[0028]

【表2】 [Table 2]

【0029】表1と表2から明らかなように、窒化アル
ミニウム基板を用いた実施例1〜5は、比較例1〜3に
比べて、ヒートショック試験、ヒートサイクル試験共に
クラックの発生とその進行が抑えられていることがわか
る。また、アルミナ基板を用いた実施例6〜9において
も比較例4と5に比べてクラックが生じにくくなってい
る。さらには特に重大な欠陥である垂直クラックについ
ては、実施例1〜9ではいずれも発生していない。
As is clear from Tables 1 and 2, in Examples 1 to 5 using an aluminum nitride substrate, the occurrence and progress of cracks in both the heat shock test and the heat cycle test were larger than those in Comparative Examples 1 to 3. It can be seen that is suppressed. Also, in Examples 6 to 9 using an alumina substrate, cracks are less likely to occur than in Comparative Examples 4 and 5. Further, in the case of the vertical cracks, which are particularly serious defects, none of Examples 1 to 9 occurred.

【0030】[0030]

【発明の効果】本発明によれば、特殊な材料の使用や工
程を変更することなしに、ヒートサイクルとヒートショ
ックの耐久性を著しく向上させた回路基板となる。
According to the present invention, there is provided a circuit board having significantly improved heat cycle and heat shock durability without using special materials or changing the steps.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 本発明の回路基板の一例を示す平面図であ
り、(a)は回路面、(b)は裏面である。
FIG. 1 is a plan view showing an example of a circuit board of the present invention, wherein (a) is a circuit surface and (b) is a back surface.

【図2】 比較例の回路基板の回路面を示す平面図であ
る。
FIG. 2 is a plan view showing a circuit surface of a circuit board of a comparative example.

【符号の説明】[Explanation of symbols]

1:セラミックス基板 2:金属回路 3:金属板 4:スリット 1: Ceramic substrate 2: Metal circuit 3: Metal plate 4: Slit

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平3−68157(JP,A) 特開 平1−120886(JP,A) 特開 平3−145748(JP,A) (58)調査した分野(Int.Cl.6,DB名) H05K 1/02 H01L 23/12 H01L 23/14 H01L 23/373 H05K 3/20 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-3-68157 (JP, A) JP-A 1-120886 (JP, A) JP-A 3-145748 (JP, A) (58) Field (Int.Cl. 6 , DB name) H05K 1/02 H01L 23/12 H01L 23/14 H01L 23/373 H05K 3/20

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 スリットを有する金属回路とセラミック
ス基板との接合体からなることを特徴とする回路基板。
1. A circuit board comprising a joined body of a metal circuit having a slit and a ceramic substrate.
JP3142644A 1991-05-20 1991-05-20 Circuit board Expired - Fee Related JP2911644B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3142644A JP2911644B2 (en) 1991-05-20 1991-05-20 Circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3142644A JP2911644B2 (en) 1991-05-20 1991-05-20 Circuit board

Publications (2)

Publication Number Publication Date
JPH04343287A JPH04343287A (en) 1992-11-30
JP2911644B2 true JP2911644B2 (en) 1999-06-23

Family

ID=15320150

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3142644A Expired - Fee Related JP2911644B2 (en) 1991-05-20 1991-05-20 Circuit board

Country Status (1)

Country Link
JP (1) JP2911644B2 (en)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100277204B1 (en) * 1998-07-24 2001-01-15 김충섭 Silicon nitride and carbon steel joining method
WO2003078353A1 (en) * 2002-03-13 2003-09-25 Schulz-Harder Juergen Method for the production of a metal-ceramic substrate, preferably a copper-ceramic substrate
DE10212495B4 (en) 2002-03-21 2004-02-26 Schulz-Harder, Jürgen, Dr.-Ing. Method for producing a metal-ceramic substrate, preferably a copper-ceramic substrate
JP4401096B2 (en) 2003-03-26 2010-01-20 Dowaホールディングス株式会社 Circuit board manufacturing method
JP2006028018A (en) * 2005-08-01 2006-02-02 Dowa Mining Co Ltd Aluminum-ceramic compound substrate
JP2007165588A (en) * 2005-12-14 2007-06-28 Omron Corp Power module structure, and solid-state relay using same
JP5167977B2 (en) * 2007-09-06 2013-03-21 日亜化学工業株式会社 Semiconductor device
JP5664517B2 (en) * 2011-10-06 2015-02-04 トヨタ自動車株式会社 Electric heating type catalytic device
JP5765221B2 (en) * 2011-12-28 2015-08-19 トヨタ自動車株式会社 Electric heating catalyst device and method for manufacturing the same
JP6456182B2 (en) * 2015-02-24 2019-01-23 株式会社三社電機製作所 Copper-clad substrate
CN108191449B (en) * 2018-01-03 2021-04-27 上海富乐华半导体科技有限公司 Copper-aluminum oxide ceramic substrate and preparation method thereof

Also Published As

Publication number Publication date
JPH04343287A (en) 1992-11-30

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