JP2910731B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2910731B2 JP2910731B2 JP9158249A JP15824997A JP2910731B2 JP 2910731 B2 JP2910731 B2 JP 2910731B2 JP 9158249 A JP9158249 A JP 9158249A JP 15824997 A JP15824997 A JP 15824997A JP 2910731 B2 JP2910731 B2 JP 2910731B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor chip
- external terminal
- pad
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Wire Bonding (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置に関し、
特に、電極パッドがセンタ部分に配置して設けられた半
導体チップを用いたメモリモジュール構造を有する半導
体装置に関する。The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor device having a memory module structure using a semiconductor chip provided with electrode pads arranged in a center portion.
【０００２】[0002]
【従来の技術】近年、マルチメディア化の進展に伴い、
オフィスコンピュータ、パーソナルコンピュータ、ゲー
ム機、自動化設備等の電子機器に対し、小型軽量化及び
メモリ容量の大容量化への要求が非常に強くなってきて
いる。これら要求に対応するためスタックメモリモジュ
ールが開発されている。2. Description of the Related Art In recent years, with the development of multimedia,
There has been an increasing demand for electronic devices such as office computers, personal computers, game machines, and automation equipment to be smaller and lighter and have a larger memory capacity. Stack memory modules have been developed to meet these demands.
【０００３】１９９５年電子情報通信学会エレクトロニ
クスソサイエティ大会講演論文集２（１９９５年８月１
５日発行、１７ページ、著者：仙波直治、嶋田勇三、得
能健市、森崎郁志）には、３次元メモリモジュールの構
造、製造工程、実験結果等が開示されている。図１２
は、３次元メモリモジュールの構造を示す断面図であ
る。図１２に示すように、３次元メモリモジュール２０
は、回路パターンが形成されている基板２１に、半導体
チップ２２をバンプ２３によって接続し、基板２１と半
導体チップ２２との間にエポキシ系の樹脂２４を注入し
て設けられた単品のメモリであるＣＳＰ（Chip Scale P
ackaging）を複数有し、ＣＳＰに設けられたパッドに多
段接続用のバンプ２５を取り付け、そのバンプ２５を介
して所望の多段構造にしている。Proceedings of the IEICE Electronics Society Conference 1995, 2 (August 1, 1995)
Published on the 5th, page 17, and authors: Naoji Senba, Yuzo Shimada, Kenichi Tokuno, Ikushi Morisaki) disclose the structure, manufacturing process, experimental results, and the like of a three-dimensional memory module. FIG.
FIG. 3 is a cross-sectional view illustrating a structure of a three-dimensional memory module. As shown in FIG. 12, the three-dimensional memory module 20
Is a unitary memory provided by connecting a semiconductor chip 22 to a substrate 21 on which a circuit pattern is formed by bumps 23 and injecting an epoxy resin 24 between the substrate 21 and the semiconductor chip 22. CSP (Chip Scale P)
and a plurality of bumps 25 for multi-stage connection are attached to pads provided on the CSP, and a desired multi-stage structure is formed via the bumps 25.
【０００４】なお、各基板２１の回路パターンは、電気
的にパラ接続の必要がある端子は、パラ接続でマザーボ
ードまで、その他の端子は同電位のものはまとめられて
マザーボードまで接続できる構造になっている。また、
各基板２１は、多段接続のために上下の同位置に同電位
のパッドが形成される。The circuit pattern of each board 21 has a structure in which terminals that need to be electrically connected in parallel can be connected to the motherboard in a parallel connection, and other terminals that have the same potential can be connected to the motherboard. ing. Also,
Pads of the same potential are formed at the same position on the upper and lower sides of each substrate 21 for multi-stage connection.
【０００５】実装する半導体チップ２２は、図９に示す
ように、電極パッド２６がセンタ部分に並んで設けられ
るものと、図１０に示すように、電極パッド２７が２辺
（又は４辺）に沿って端部に設けられるものとがある。[0005] The semiconductor chip 22 to be mounted has an electrode pad 26 provided side by side at the center as shown in FIG. 9 and an electrode pad 27 on two sides (or four sides) as shown in FIG. Some are provided along the edge.
【０００６】[0006]
【発明が解決しようとする課題】電極パッドがセンタ部
分に並んで設けられる半導体チップの場合、半導体チッ
プの端部に半導体チップと基板を繋ぐ構造物が存在しな
いため、基板のたわみが大きくなる。そのため、基板の
センタ部分に設けられた接続パッドに半導体チップを実
装したＣＳＰを３次元的にスタックすると、基板が一層
たわむため、基板間のギャップがばらつき、外部端子に
かかる応力に偏りがでる。その結果、外部端子の接続信
頼性が低下するという不都合が生じる。In the case of a semiconductor chip in which electrode pads are provided side by side at the center, there is no structure connecting the semiconductor chip and the substrate at the end of the semiconductor chip, so that the deflection of the substrate increases. Therefore, when a CSP in which a semiconductor chip is mounted on a connection pad provided in the center portion of a substrate is three-dimensionally stacked, the substrates are further bent, so that the gap between the substrates is varied, and the stress applied to the external terminals is biased. As a result, there is a disadvantage that the connection reliability of the external terminal is reduced.
【０００７】また、図１１に示すように、電極パッドが
２辺（又は４辺）に沿って端部に設けられる半導体チッ
プ２２を基板２１の両面に実装する場合、基板２１の表
面側の半導体チップ２２の電極パッド２７ａ、２７ｂと
裏面側の半導体チップ２２の電極パッド２７ａ、２７ｂ
の配置が反転する。そのため、例えば、アドレス用パッ
ドやデータ用パッド等の共通化や外部端子の共通化を行
うと、基板２１上での配線パターンの引き回りが複雑に
なる。その結果、性能の低下やコストアップ、場合によ
っては基板が形成できない等の不都合が生じる。Further, as shown in FIG. 11, when a semiconductor chip 22 having electrode pads provided at two ends (or four sides) along two sides (or four sides) is mounted on both sides of the substrate 21, a semiconductor chip on the front side of the substrate 21 is provided. Electrode pads 27a and 27b of chip 22 and electrode pads 27a and 27b of semiconductor chip 22 on the back side
Is reversed. Therefore, for example, when the address pads and the data pads are shared or the external terminals are shared, the routing of the wiring pattern on the substrate 21 becomes complicated. As a result, inconveniences such as a decrease in performance, an increase in cost, and a case where a substrate cannot be formed may occur.
【０００８】さらに、従来のスタックモジュールは、Ｃ
ＳＰを重ねるものであり、使用するメモリの数だけ基板
を必要とする。そのため、基板の原価を下げるには、基
板自身の原価を下げなくてはならないが、実際には大幅
な原価低減を基板に望むことができない。Further, the conventional stack module is C
The SPs are stacked, and require as many substrates as the number of memories to be used. Therefore, in order to lower the cost of the substrate, the cost of the substrate itself must be reduced, but in practice, it is not possible to expect a significant cost reduction for the substrate.
【０００９】本発明は、上記課題を解決するためになさ
れたものであり、電極パッドがセンタ部分に配置して設
けられた半導体チップを基板の表面及び裏面に実装する
ことにより、コストを削減し基板の反りを抑えて高い信
頼性を有する半導体装置を提供することを目的とする。SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and a semiconductor chip provided with electrode pads arranged at a center portion is mounted on the front and back surfaces of a substrate, thereby reducing costs. An object of the present invention is to provide a semiconductor device having high reliability by suppressing warpage of a substrate.
【００１０】[0010]
【課題を解決するための手段】本発明は、電極パッドが
センタ部分に設けられた一対の半導体チップと、表面に
前記一方の半導体チップが実装され、裏面に前記他方の
半導体チップが実装される基板と、を有する半導体装置
において、前記基板は、前記一方の半導体チップの電極
パッドに対応して表面のセンタ部分に設けられ、その電
極パッドに電気的に接続される接続パッドと、前記他方
の半導体チップの電極パッドに対応して裏面のセンタ部
分に設けられ、その電極パッドに電気的に接続される接
続パッドと、前記表面の接続パッドと裏面の接続パッド
との共通の外部端子として、スルーホール又はビアホー
ル及び配線を介して前記接続パッドに電気的に接続され
る外部端子パッドとを有する、ことを特徴とするもので
ある。According to the present invention, there is provided a pair of semiconductor chips having electrode pads provided in a center portion, the one semiconductor chip mounted on a front surface, and the other semiconductor chip mounted on a back surface. And a substrate, wherein the substrate is provided at a center portion of a surface corresponding to the electrode pad of the one semiconductor chip, and a connection pad electrically connected to the electrode pad; and A connection pad provided in the center portion of the back surface corresponding to the electrode pad of the semiconductor chip and electrically connected to the electrode pad, and a through-hole as a common external terminal of the connection pad on the front surface and the connection pad on the back surface. An external terminal pad electrically connected to the connection pad via a hole or a via hole and a wiring.
【００１１】[0011]
【００１２】上記外部端子パッドは、基板の表面と裏面
とに設けられてもよい。この場合、基板の表面に設けら
れる外部端子パッドと基板の裏面に設けられる外部端子
パッドとは、平面からみて重なる位置に配置されてもよ
い。The external terminal pads may be provided on the front surface and the back surface of the substrate. In this case, the external terminal pads provided on the front surface of the substrate and the external terminal pads provided on the back surface of the substrate may be arranged at positions overlapping each other when viewed from a plane.
【００１３】本発明の半導体装置は又、上記基板を３次
元的に重ねた構造を有し、重ねられた一方側の基板の外
部端子パッドと他方側の基板の外部端子パッドとを導体
を介して電気的に接続することを特徴とするものであ
る。The semiconductor device of the present invention also has a structure in which the above-mentioned substrates are three-dimensionally stacked, and the external terminal pads of the stacked one side substrate and the external terminal pads of the other side substrate are interposed via conductors. And electrical connection.
【００１４】上記重ねられた一方側の基板の裏面に実装
された半導体チップと他方側の基板の表面に実装された
半導体チップとは所定間隔を隔てているのが好ましい。It is preferable that the semiconductor chip mounted on the back surface of the one side substrate and the semiconductor chip mounted on the front surface of the other side substrate are separated by a predetermined distance.
【００１５】[0015]
【発明の実施の形態】以下、本発明の実施の形態を図面
を参照しながら説明する。図１及び図２は、センタ部分
に電極パッドが設けられた半導体チップの例を示す斜視
図である。Embodiments of the present invention will be described below with reference to the drawings. 1 and 2 are perspective views showing examples of a semiconductor chip having an electrode pad provided in a center portion.
【００１６】本発明の半導体装置に係る半導体チップ１
は、そのセンタ部分（端部を除いた内側の部分）だけに
電極パッド２が配置されており、各々の電極パッド２の
上下左右どの方向にも配線を引き回すことができる。例
えば、図１に示すように、電極パッド２がセンタ部分に
１直線又はジグザグ状に１列に並んでいる場合はもちろ
ん、図２に示すように、隣接して電極パッド２が並んで
いる場合も含む。Semiconductor chip 1 according to the semiconductor device of the present invention
The electrode pads 2 are arranged only in the center portion (the inner portion excluding the end portion), and wiring can be routed in any direction of up, down, left and right of each electrode pad 2. For example, as shown in FIG. 1, not only when the electrode pads 2 are arranged in a line in a straight line or zigzag at the center portion, but also when the electrode pads 2 are arranged adjacently as shown in FIG. Including.
【００１７】図３は、図１の半導体チップを実装する基
板の表面と裏面を示す斜視図、図４は、図２の半導体チ
ップを実装する基板の表面と裏面を示す斜視図である。FIG. 3 is a perspective view showing the front and back surfaces of the substrate on which the semiconductor chip of FIG. 1 is mounted, and FIG. 4 is a perspective view showing the front and back surfaces of the substrate on which the semiconductor chip of FIG. 2 is mounted.
【００１８】本発明の半導体装置に係る基板３は、表面
３ａと裏面３ｂとに半導体チップ１を実装するものであ
り、図３及び図４に示すように、半導体チップ１の電極
パッド２に対応した位置に配置され、表面３ａと裏面３
ｂにそれぞれ設けられた接続パッド４と、表面３ａと裏
面３ｂとを貫通する貫通孔５と、外部端子パッド６と、
を備えている。The substrate 3 according to the semiconductor device of the present invention has the semiconductor chip 1 mounted on the front surface 3a and the back surface 3b, and corresponds to the electrode pads 2 of the semiconductor chip 1 as shown in FIGS. Surface 3a and back surface 3
b, a through-hole 5 penetrating the front surface 3a and the back surface 3b, an external terminal pad 6,
It has.
【００１９】表面３ａに設けられた接続パッド４と裏面
３ｂに設けられた接続パッド４との共通端子は、貫通孔
５を介して配線によって電気的に接続される。貫通孔５
は、例えば、スルーホール又はビアホールである。The common terminals of the connection pads 4 provided on the front surface 3a and the connection pads 4 provided on the back surface 3b are electrically connected to each other through wiring through the through holes 5. Through hole 5
Is, for example, a through hole or a via hole.
【００２０】外部端子パッド６は、基板３の端部に設け
られ、配線によって接続パッド４と電気的に接続され
る。外部端子パッド６は、半導体チップ１を実装した基
板３を多段に重ねる場合には、基板３の表面３ａと裏面
３ｂとにそれぞれ設けられる。The external terminal pads 6 are provided at the ends of the substrate 3 and are electrically connected to the connection pads 4 by wiring. When the substrates 3 on which the semiconductor chips 1 are mounted are stacked in multiple stages, the external terminal pads 6 are provided on the front surface 3a and the rear surface 3b of the substrate 3, respectively.
【００２１】また、メモリモジュールのようにほぼすべ
てのピンを共通にできる場合には、図３及び図４に示す
ように、基板３の表面３ａに設けられる外部端子パッド
６と基板３の裏面３ｂに設けられる外部端子パッド６と
が平面からみて重なる位置に配置されるのが、スタック
の面から好ましい。しかし、片面にＲＩＳＫチップ、も
う片面にメモリチップ等を実装するように接続すべきピ
ン数が異なる場合には、必ずしも外部端子パッド６が重
なるように配置する必要はない。When almost all pins can be commonly used like a memory module, as shown in FIGS. 3 and 4, the external terminal pads 6 provided on the front surface 3a of the substrate 3 and the back surface 3b It is preferable from the viewpoint of the stack that the external terminal pad 6 provided in the stack is arranged at a position where the external terminal pad 6 overlaps when viewed from a plane. However, when the number of pins to be connected is different so that a RISK chip is mounted on one side and a memory chip or the like is mounted on the other side, it is not always necessary to arrange the external terminal pads 6 so as to overlap.
【００２２】なお、基板３に半導体チップ１を両面実装
した半導体装置自体を、重ねることなくそのままモジュ
ールとして使用する場合は、外部端子パッド６は必ずし
も基板３の両面に設ける必要はない。When the semiconductor device having the semiconductor chip 1 mounted on the substrate 3 on both sides is used as a module without being overlapped, the external terminal pads 6 are not necessarily provided on both sides of the substrate 3.
【００２３】図５は、基板の両面に半導体チップを実装
し、外部端子パッドに導電性バンプを設けたメモリモジ
ュールの半導体装置を示す斜視図、図６は、図５のVI−
VI線断面図である。FIG. 5 is a perspective view showing a semiconductor device of a memory module in which semiconductor chips are mounted on both sides of a substrate and conductive bumps are provided on external terminal pads. FIG.
FIG. 6 is a sectional view taken along line VI.
【００２４】図５及び図６に示すメモリモジュールの半
導体装置Ａは、半導体チップ１と基板３とをフェースダ
ウンで実装するために、半導体チップ１上の電極パッド
２に導電性バンプ７が設けられ、導電性バンプ７と基板
３上の接続パッド４とが異方導電性シート８を介して電
気的に接続される。これを基板３の表面３ａと裏面３ｂ
の両面に対して行う。実装方法は基板３の表面３ａと裏
面３ｂで必ずしも同一の方法を採用する必要はないが、
反りをより押えるには、同一の方法を採用して、構造が
対称になるようにするのが好ましい。In the semiconductor device A of the memory module shown in FIGS. 5 and 6, conductive bumps 7 are provided on the electrode pads 2 on the semiconductor chip 1 in order to mount the semiconductor chip 1 and the substrate 3 face down. The conductive bumps 7 and the connection pads 4 on the substrate 3 are electrically connected via the anisotropic conductive sheet 8. This is combined with the front surface 3a and the back surface 3b
For both sides. Although the mounting method does not necessarily need to adopt the same method for the front surface 3a and the back surface 3b of the substrate 3,
In order to further suppress the warpage, it is preferable to adopt the same method so that the structure becomes symmetric.
【００２５】具体的な実装方法としては、半導体チップ
１側に金バンプを形成し、基板３側に半田供給したもの
を接続し、封止樹脂（例えば、シリカを含有するエポキ
シ系、アミン系、酸無水系、フェノール系、フェキシ系
の樹脂）で封止する工法（一般に半田工法と呼ばれ
る）、半導体チップ１に半田バンプを形成し、基板３の
接続パッド４にフラックスを塗布して半導体チップ１を
搭載し、搭載後リフローにより接続して封止する工法、
半導体チップ１ー基板３間に異方導電性シートを挟み、
熱圧着することにより実装する工法、或いは導電性樹脂
のバンプを半導体チップ１または基板３の電極パッド２
上に形成し、基板３に半導体チップ１搭載後に導電性樹
脂を硬化させ樹脂封止する工法などが挙げられる。As a specific mounting method, a gold bump is formed on the semiconductor chip 1 side, a solder-supplied one is connected to the substrate 3 side, and a sealing resin (for example, epoxy-based, amine-based, A method of sealing with an acid anhydride-based, phenol-based, or fexic-based resin (generally called a soldering method); forming a solder bump on a semiconductor chip 1; applying a flux to a connection pad 4 of a substrate 3; A method of mounting and sealing by connecting and reflowing after mounting,
An anisotropic conductive sheet is sandwiched between the semiconductor chip 1 and the substrate 3,
A method of mounting by thermocompression bonding, or a method of mounting a bump of conductive resin on the electrode pad 2 of the semiconductor chip 1 or the substrate 3.
A method of curing the conductive resin after the semiconductor chip 1 is mounted on the substrate 3 after mounting the semiconductor chip 1 on the substrate 3 and sealing the resin with the resin.
【００２６】図５及び図６に示す半導体装置Ａは、半導
体チップ１ー基板３間は封止樹脂、異方導電性シート８
等で満たされており、空隙になっていない。外部端子パ
ッド６上には導電性バンプ９が設けられる。この導電性
バンプ９は、モジュール同士、或いはモジュールーマザ
ーボードを電気的に接続するために設けられたものであ
る。The semiconductor device A shown in FIGS. 5 and 6 has a sealing resin between the semiconductor chip 1 and the substrate 3 and an anisotropic conductive sheet 8.
Etc., and are not voids. A conductive bump 9 is provided on the external terminal pad 6. The conductive bumps 9 are provided for electrically connecting modules or a module-motherboard.
【００２７】図７は、図５に示すメモリモジュールを２
段に重ねたスタックメモリモジュールの半導体装置を示
す斜視図、図８は、図７のVIII−VIII線断面図である。FIG. 7 shows the memory module shown in FIG.
FIG. 8 is a perspective view showing a semiconductor device of a stacked memory module stacked on a tier, and FIG. 8 is a sectional view taken along line VIII-VIII of FIG.
【００２８】図７及び図８に示す半導体装置Ｂは、図５
及び図６に示すメモリモジュール同士を外部端子パッド
６上に設けられた導電性バンプ９によって電気的に接続
し、２段に重ねたスタックメモリモジュールである。外
部端子パッド６同士を電気的に接続する導電性バンプ９
としては、例えば、半田バンプ、銀エポキシ樹脂バン
プ、半田付き銅ボールなどが挙げられる。The semiconductor device B shown in FIG. 7 and FIG.
6 are electrically connected to each other by conductive bumps 9 provided on external terminal pads 6 to form a stacked memory module in which the memory modules shown in FIG. Conductive bump 9 for electrically connecting external terminal pads 6
Examples thereof include solder bumps, silver epoxy resin bumps, and soldered copper balls.
【００２９】図７及び図８に示す半導体装置Ｂはメモリ
モジュールを２段だけ重ねてあるが、３段以上重ねても
よい。また、モジュール同士を重ねる際、半導体チップ
１に応力をかけないように、あるいは放熱しやすいよう
に、重ねられた上側の基板３の裏面３ｂに実装された半
導体チップ１と下側の基板３の表面３ａに実装された半
導体チップ１とが所定間隔を隔てているのが好ましい。
この場合、上側及び下側の半導体チップ１同士が接触し
ないように、外部端子パッド６上の導電性バンプ９の径
が選択して決定される。なお、スタックするモジュール
は、同一種類のモジュールでなくてもよい。Although the semiconductor device B shown in FIG. 7 and FIG. 8 has only two memory modules stacked, three or more memory modules may be stacked. When the modules are stacked, the semiconductor chip 1 mounted on the back surface 3b of the upper substrate 3 and the lower substrate 3 are stacked so as not to apply stress to the semiconductor chip 1 or to easily radiate heat. It is preferable that the semiconductor chip 1 mounted on the front surface 3a is separated by a predetermined distance.
In this case, the diameter of the conductive bump 9 on the external terminal pad 6 is selected and determined so that the upper and lower semiconductor chips 1 do not contact each other. Note that the modules to be stacked need not be the same type of module.
【００３０】本発明によれば、半導体チップ１のセンタ
部分に電極パッド２が設けられ、基板３の表面と裏面に
半導体チップ１の電極パッド２に対応した位置に接続パ
ッド４が設けられるので、基板３の表面と裏面とに半導
体チップ１を実装しても、外部端子等を共通化するため
の配線の引き回しを容易に行うことができる。According to the present invention, the electrode pads 2 are provided at the center portion of the semiconductor chip 1, and the connection pads 4 are provided on the front and back surfaces of the substrate 3 at positions corresponding to the electrode pads 2 of the semiconductor chip 1. Even if the semiconductor chip 1 is mounted on the front surface and the back surface of the substrate 3, it is possible to easily perform wiring routing for sharing external terminals and the like.
【００３１】また、半導体チップ１を基板３の表面３ａ
と裏面３ｂの両面に実装するので、従来よりも基板３の
数が半分でよく、製造コストを大幅に削減できる。Further, the semiconductor chip 1 is placed on the surface 3a of the substrate 3.
Since the semiconductor device is mounted on both sides of the substrate 3 and the back surface 3b, the number of the substrates 3 may be half that of the conventional case, and the manufacturing cost can be greatly reduced.
【００３２】さらに、基板３に対して対称に半導体チッ
プ１が実装されるので、基板３にかかる応力が表面３ａ
と裏面３ｂとで相殺され、基板３の反り量が低減する。
また、個々の基板３の反り量が低減することにより、ス
タックする際の基板３間の距離のばらつきも低減される
ため、外部端子の導電性物質にかかる応力も均一化され
る。その結果、外部端子の接続信頼性が向上する。Further, since the semiconductor chip 1 is mounted symmetrically with respect to the substrate 3, the stress applied to the substrate 3 is reduced by the surface 3a.
And the back surface 3b, and the amount of warpage of the substrate 3 is reduced.
In addition, since the amount of warpage of each substrate 3 is reduced, the variation in the distance between the substrates 3 during stacking is also reduced, so that the stress applied to the conductive material of the external terminals is also made uniform. As a result, the connection reliability of the external terminals is improved.
【００３３】本発明は、上記実施の形態に限定されるこ
とはなく、特許請求の範囲に記載された技術的事項の範
囲内において、種々の変更が可能である。The present invention is not limited to the above embodiment, and various changes can be made within the scope of the technical matters described in the claims.
【００３４】[0034]
【実施例】本発明者は、上述した半導体装置を実際に製
造した。この場合、半導体チップ１として１６Ｍｂのメ
モリチップを使用した。このメモリチップのチップ厚は
０．３ｍｍである。半導体チップ１上の電極パッド２は
アルミニウムで作られ、一辺が１１０μｍの大きさの正
方形の形状に形成される。また、基板３には厚さ０．４
ｍｍのガラエポ板を用い、基板３の裏表で共通の端子は
径０．３ｍｍのスルーホール５で接続した。配線層は銅
である。モジュールの構造は、図６に示すように、半導
体チップ１の電極パッド２上の導電性バンプ７に径１０
０μｍ程度の金バンプを形成し、厚さ３０μｍ程度の異
方導電性シート８を介してバンプ７と基板３の接続パッ
ド４を電気的に接続した。DESCRIPTION OF THE PREFERRED EMBODIMENTS The inventor actually manufactured the above-described semiconductor device. In this case, a 16 Mb memory chip was used as the semiconductor chip 1. The chip thickness of this memory chip is 0.3 mm. The electrode pad 2 on the semiconductor chip 1 is made of aluminum and is formed in a square shape having a side of 110 μm. The substrate 3 has a thickness of 0.4
A common terminal on the front and back of the substrate 3 was connected by a through-hole 5 having a diameter of 0.3 mm using a glass epoxy plate having a thickness of 2 mm. The wiring layer is copper. As shown in FIG. 6, the structure of the module is such that conductive bumps 7 on electrode pads 2 of semiconductor chip 1 have diameters of 10 mm.
A gold bump having a thickness of about 0 μm was formed, and the bump 7 was electrically connected to the connection pad 4 of the substrate 3 via an anisotropic conductive sheet 8 having a thickness of about 30 μm.
【００３５】外部端子パッド６の径は０．８ｍｍで、外
部端子パッド６上に形成した導電性バンプ９には径０．
７ｍｍの銅ボールの周りに半田をメッキで付けた半田付
き銅ボールを用いた。The external terminal pad 6 has a diameter of 0.8 mm, and the conductive bump 9 formed on the external terminal pad 6 has a diameter of 0.8 mm.
A copper ball with solder in which solder was plated around a 7 mm copper ball was used.
【００３６】本発明者は又、前述のメモリモジュール
を、導電性バンプ９に半田付き銅ボールを使用してスタ
ックした。半田付き銅ボールの銅ポール径は０．７ｍｍ
である。The inventor has also stacked the above-described memory module on the conductive bumps 9 using soldered copper balls. The copper pole diameter of the soldered copper ball is 0.7mm
It is.
【００３７】これによりモジュール間を０．７ｍｍ間隔
に規定し、メモリモジュールをスタックした際に、半導
体チップ１間を０．０４μｍ（銅ボール径０．７μｍー
チップ厚０．３μｍ×２ー異方導電性シート厚０．０３
μｍ×２）間隔をあけた。Thus, the spacing between the modules is defined as 0.7 mm, and when the memory modules are stacked, the spacing between the semiconductor chips 1 is 0.04 μm (copper ball diameter 0.7 μm-chip thickness 0.3 μm × 2—anisotropic conductive). Sheet thickness 0.03
μm × 2) An interval was provided.
【００３８】[0038]
【発明の効果】本発明によれば、次のような優れた効果
を奏する。 （１）半導体チップのセンタ部分に電極パッドが設けら
れ、基板の表面と裏面に半導体チップの電極パッドに対
応した位置に接続パッドが設けられるので、基板の表面
と裏面とに半導体チップを実装しても、外部端子等を共
通化するための配線の引き回しを容易に行うことができ
る。 （２）半導体チップを基板の表面と裏面の両面に実装す
るので、従来よりも基板の数が半分ですみ、製造コスト
を大幅に削減できる。 （３）基板に対して対称に半導体チップが実装されるの
で、基板にかかる応力が表面と裏面とで相殺され、基板
の反り量が低減する。また、個々の基板の反り量が低減
することにより、スタックする際の基板間の距離のばら
つきも低減されるため、外部端子の導電性物質にかかる
応力も均一化される。その結果、外部端子の接続信頼性
が向上する。According to the present invention, the following excellent effects can be obtained. (1) Since an electrode pad is provided in the center portion of the semiconductor chip and connection pads are provided on the front and back surfaces of the substrate at positions corresponding to the electrode pads of the semiconductor chip, the semiconductor chip is mounted on the front and back surfaces of the substrate. Even so, wiring can be easily routed to share external terminals and the like. (2) Since the semiconductor chip is mounted on both the front surface and the rear surface of the substrate, the number of substrates is reduced by half compared to the conventional case, and the manufacturing cost can be greatly reduced. (3) Since the semiconductor chip is mounted symmetrically with respect to the substrate, the stress applied to the substrate is offset between the front surface and the back surface, and the amount of warpage of the substrate is reduced. In addition, since the amount of warpage of each substrate is reduced, the variation in the distance between the substrates during stacking is also reduced, so that the stress applied to the conductive material of the external terminals is also made uniform. As a result, the connection reliability of the external terminals is improved.
【図１】センタ部分に電極パッドが設けられた半導体チ
ップの一例を示す斜視図である。FIG. 1 is a perspective view showing an example of a semiconductor chip provided with an electrode pad in a center portion.
【図２】センタ部分に電極パッドが設けられた半導体チ
ップの他の例を示す斜視図である。FIG. 2 is a perspective view showing another example of a semiconductor chip provided with an electrode pad in a center portion.
【図３】図１の半導体チップを実装する基板の表面と裏
面を示す斜視図である。FIG. 3 is a perspective view showing a front surface and a back surface of a substrate on which the semiconductor chip of FIG. 1 is mounted;
【図４】図２の半導体チップを実装する基板の表面と裏
面を示す斜視図である。FIG. 4 is a perspective view showing a front surface and a back surface of a substrate on which the semiconductor chip of FIG. 2 is mounted;
【図５】基板の両面に半導体チップを実装し、外部端子
パッドに導電性バンプを設けたメモリモジュールの半導
体装置を示す斜視図である。FIG. 5 is a perspective view showing a semiconductor device of a memory module in which semiconductor chips are mounted on both surfaces of a substrate and conductive bumps are provided on external terminal pads.
【図６】図５のVI−VI線断面図である。6 is a sectional view taken along line VI-VI of FIG.
【図７】図５のメモリモジュールを２段重ねたスタック
メモリモジュールの半導体装置を示す斜視図である。7 is a perspective view showing a semiconductor device of a stack memory module in which the memory modules of FIG. 5 are stacked in two stages.
【図８】図７のVIII−VIII線断面図である。8 is a sectional view taken along line VIII-VIII in FIG.
【図９】電極パッドがセンタ部分に並んで設けられる半
導体チップを示す斜視図である。FIG. 9 is a perspective view showing a semiconductor chip in which electrode pads are provided side by side in a center portion.
【図１０】電極パッドが２辺に沿って端部に設けられる
半導体チップを示す斜視図である。FIG. 10 is a perspective view showing a semiconductor chip in which electrode pads are provided at ends along two sides.
【図１１】電極パッドが２辺に沿って端部に設けられる
半導体チップを基板の両面に実装する場合を説明する説
明図である。FIG. 11 is an explanatory diagram illustrating a case where a semiconductor chip having electrode pads provided at ends along two sides is mounted on both surfaces of a substrate.
【図１２】３次元メモリモジュールの構造を示す断面図
である。FIG. 12 is a cross-sectional view illustrating a structure of a three-dimensional memory module.
Ａ：半導体装置 Ｂ：半導体装置 １：半導体チップ ２：電極パッド ３：基板 ３ａ：表面 ３ｂ：裏面 ４：接続パッド ５：貫通孔 ６：外部端子パッド ７：導電性バンプ ８：異方導電性シート ９：導電性バンプ A: Semiconductor device B: Semiconductor device 1: Semiconductor chip 2: Electrode pad 3: Substrate 3a: Front surface 3b: Back surface 4: Connection pad 5: Through hole 6: External terminal pad 7: Conductive bump 8: Anisotropic conductive sheet 9: conductive bump
───────────────────────────────────────────────────── フロントページの続き (72)発明者 仙波 直治 東京都港区芝五丁目７番１号 日本電気 株式会社内 (56)参考文献 特開 平６−216182（ＪＰ，Ａ) 特開 平３−16252（ＪＰ，Ａ) (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 25/065 ────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Naoji Senba 5-7-1 Shiba, Minato-ku, Tokyo Within NEC Corporation (56) References JP-A-6-216182 (JP, A) JP-A-3 -16252 (JP, A) (58) Fields investigated (Int. Cl. 6 , DB name) H01L 25/065
Claims (5)
の半導体チップと、 表面に前記一方の半導体チップが実装され、裏面に前記
他方の半導体チップが実装される基板と、を有する半導
体装置において、 前記基板は、前記一方の半導体チップの電極パッドに対
応して表面のセンタ部分に設けられ、その電極パッドに
電気的に接続される接続パッドと、前記他方の半導体チ
ップの電極パッドに対応して裏面のセンタ部分に設けら
れ、その電極パッドに電気的に接続される接続パッド
と、前記表面の接続パッドと裏面の接続パッドとの共通
の外部端子として、スルーホール又はビアホール及び配
線を介して前記接続パッドに電気的に接続される外部端
子パッドとを有する、ことを特徴とする半導体装置。1. A semiconductor device comprising: a pair of semiconductor chips each having an electrode pad provided at a center portion; and a substrate having the one semiconductor chip mounted on a front surface and the other semiconductor chip mounted on a back surface. The substrate is provided at a center portion of the surface corresponding to the electrode pad of the one semiconductor chip, and corresponds to a connection pad electrically connected to the electrode pad and a electrode pad of the other semiconductor chip. Through a through-hole or via-hole and wiring as a connection pad provided at the center portion of the back surface and electrically connected to the electrode pad, and as a common external terminal of the connection pad on the front surface and the connection pad on the back surface. A semiconductor device having an external terminal pad electrically connected to the connection pad.
とに設けられることを特徴とする請求項１に記載の半導
体装置。2. The semiconductor device according to claim 1, wherein said external terminal pads are provided on a front surface and a back surface of a substrate.
ドと基板の裏面に設けられる外部端子パッドとは、平面
からみて重なる位置に配置されることを特徴とする請求
項２に記載の半導体装置。3. The semiconductor device according to claim 2, wherein the external terminal pads provided on the front surface of the substrate and the external terminal pads provided on the back surface of the substrate are arranged at positions overlapping when viewed from a plane. .
重ねられた一方側の基板の外部端子パッドと他方側の基
板の外部端子パッドとが導体を介して電気的に接続され
ることを特徴とする請求項１乃至３のいずれか１つの項
に記載の半導体装置。4. It has a structure in which the substrates are three-dimensionally stacked,
4. The external terminal pad on the one side substrate and the external terminal pad on the other side substrate which are overlapped are electrically connected via a conductor. Semiconductor device.
された半導体チップと他方側の基板の表面に実装された
半導体チップとは所定間隔を隔てていることを特徴とす
る請求項４に記載の半導体装置。5. The semiconductor chip mounted on the back surface of one of the stacked substrates and the semiconductor chip mounted on the front surface of the other substrate are separated by a predetermined distance. 3. The semiconductor device according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9158249A JP2910731B2 (en) | 1997-06-16 | 1997-06-16 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9158249A JP2910731B2 (en) | 1997-06-16 | 1997-06-16 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH118347A JPH118347A (en) | 1999-01-12 |
| JP2910731B2 true JP2910731B2 (en) | 1999-06-23 |
Family
ID=15667515
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9158249A Expired - Fee Related JP2910731B2 (en) | 1997-06-16 | 1997-06-16 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2910731B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4811585A (en) * | 1986-04-02 | 1989-03-14 | Nissan Motor Co., Ltd. | Device for forming asymmetrical articles by rolling |
| JP2002151648A (en) | 2000-11-07 | 2002-05-24 | Mitsubishi Electric Corp | Semiconductor module |
| JP4622469B2 (en) * | 2004-11-12 | 2011-02-02 | ソニー株式会社 | Circuit board, circuit board manufacturing method, and semiconductor device |
| JP5068133B2 (en) * | 2007-10-17 | 2012-11-07 | 新光電気工業株式会社 | Semiconductor chip laminated structure and semiconductor device |
| JP2017122625A (en) * | 2016-01-06 | 2017-07-13 | 株式会社豊田中央研究所 | Data logging device |
-
1997
- 1997-06-16 JP JP9158249A patent/JP2910731B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH118347A (en) | 1999-01-12 |
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