JPH0493093A - Forming method for electronic component containing recess of circuit board - Google Patents
Forming method for electronic component containing recess of circuit boardInfo
- Publication number
- JPH0493093A JPH0493093A JP21074990A JP21074990A JPH0493093A JP H0493093 A JPH0493093 A JP H0493093A JP 21074990 A JP21074990 A JP 21074990A JP 21074990 A JP21074990 A JP 21074990A JP H0493093 A JPH0493093 A JP H0493093A
- Authority
- JP
- Japan
- Prior art keywords
- film
- peelable resin
- circuit board
- resin film
- inner layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 15
- 239000011347 resin Substances 0.000 claims abstract description 38
- 229920005989 resin Polymers 0.000 claims abstract description 38
- 239000004020 conductor Substances 0.000 claims abstract description 23
- 239000011888 foil Substances 0.000 claims abstract description 20
- 239000002184 metal Substances 0.000 claims abstract description 18
- 229910052751 metal Inorganic materials 0.000 claims abstract description 18
- 238000005520 cutting process Methods 0.000 claims abstract description 17
- 239000000853 adhesive Substances 0.000 claims description 8
- 230000001070 adhesive effect Effects 0.000 claims description 8
- 238000009824 pressure lamination Methods 0.000 claims 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 21
- 239000011889 copper foil Substances 0.000 abstract description 20
- 238000010438 heat treatment Methods 0.000 abstract description 5
- 239000007788 liquid Substances 0.000 abstract description 5
- 230000002093 peripheral effect Effects 0.000 abstract description 5
- 238000007772 electroless plating Methods 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000000465 moulding Methods 0.000 description 3
- 235000013405 beer Nutrition 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000003486 chemical etching Methods 0.000 description 1
- 230000035606 childbirth Effects 0.000 description 1
- 238000005253 cladding Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 239000007858 starting material Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
この発明はプリント配線基板の電子部品収納用凹部を形
成する方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method of forming a recess for housing an electronic component in a printed wiring board.
［従来の技術およびその問題点］
プリント配線基板における電子部品収納用凹部には不透
気性や熱放散性と云ったことを目的に凹部の底面或いは
壁面の全体に無電解鍍金が施されている。その電子部品
収納用凹部は、一般に、第４図に示ずように、先ず両面
金属張積層板の所定位置にザグリ加工により凹部１０を
形成し、この凹部１０の底面或いは壁面全体に無電解鍍
金により鍍金膜１１を形成して電子部品収納用凹部が形
成されている。そして、凹部の鍍金膜厚１１の厚みが不
足する場合はその上面に更に電解鍍金による鍍金膜］１
を形成して膜厚を厚くすることも一般に行われている。[Prior art and its problems] Electroless plating is applied to the entire bottom or wall of the recessed portion of a printed wiring board for housing electronic components for the purpose of air impermeability and heat dissipation. . Generally, as shown in FIG. 4, the electronic component housing recess is formed by first forming a recess 10 at a predetermined position in a double-sided metal-clad laminate by counterboring, and then electroless plating is applied to the entire bottom or wall surface of the recess 10. A plating film 11 is formed to form a recess for accommodating electronic components. If the thickness of the plating film 11 in the recess is insufficient, an additional plating film by electrolytic plating on the upper surface]1
It is also common practice to increase the film thickness by forming.
この従来法による電子部品収納用凹部は、■凹部１０の
底面がザグリ加工のために粗くなり、無電解鍍金の鍍金
膜の表面にその粗さがあられれて凹部１０の底面の平滑
性が良くないと云う問題点がある。また、
■凹部１０底面の無電解鍍金による鍍金膜１１は基板材
料との密着性に劣り、特にビール強度や耐熱性が悪いと
云う問題点がある。The concave part for storing electronic components made by this conventional method is as follows: (1) The bottom surface of the concave part 10 is rough due to the counterbore process, and the surface of the electroless plating film is smoothed, so that the bottom surface of the concave part 10 has good smoothness. There is a problem that there is no such thing. In addition, (1) the plating film 11 formed by electroless plating on the bottom surface of the recess 10 has poor adhesion to the substrate material, and there is a problem in that the beer strength and heat resistance are particularly poor.
［問題点を解決するための手段］
この発明の配線基板の電子部品収納用凹部形成方法は、
上記問題点を解決するために、多層金属張積層基板に成
形の際に内層回路板の少なくとも電子部品搭載用導体部
分の上面に予め加熱硬化した剥離可能な樹脂膜［剥離型
樹脂膜］を形成しておき、電子部品搭載用金属導体箔部
の上面を切削加工する際に剥離型樹脂膜まで切削し、剥
離型樹脂膜を剥離除去して電子部品収納用凹部を形成す
るようにしたのである。[Means for Solving the Problems] A method for forming a recess for housing electronic components in a wiring board of the present invention includes:
In order to solve the above problems, a peelable resin film (peelable resin film) that is heated and hardened in advance is formed on the upper surface of at least the conductor portion for mounting electronic components of the inner layer circuit board during molding of the multilayer metal-clad laminate board. Then, when cutting the top surface of the metal conductor foil portion for mounting electronic components, the peelable resin film was also cut, and the peelable resin film was peeled off to form a recess for storing electronic components. .
この発明の配線基板の電子部品収納用凹部形成方法は、
多層化積層一体成形する前に、内層回路板の電子部品搭
載用導体部分の表面に、予め剥離型樹脂膜を形成するこ
とを除き通常の多層回路基板の多層化積層一体化成形方
法がその才ま使用できる。The method for forming a recess for housing electronic components in a wiring board according to the present invention includes:
Except for forming a peelable resin film in advance on the surface of the conductor portion for mounting electronic components on the inner layer circuit board before performing multilayer lamination integral molding, the conventional multilayer lamination integral molding method for multilayer circuit boards has its advantages. Yes, you can use it.
剥離型樹脂膜は未硬化状態の樹脂液を電子部品搭載用導
体部分の上面に印刷法等により印刷し、その後の多層化
積層一体化の際に形状変化を起こさない程度に十分に加
熱硬化させた樹脂膜で、硬化後の樹脂膜は接着性に乏し
く機械的に容易に剥離できるもので、例えば■アサヒ化
学研究所ストリップマスク＃２２８−Ｔ、＃４４８−Ｔ
より形成することができる。The peelable resin film is made by printing an uncured resin liquid on the top surface of the conductor part for mounting electronic components using a printing method, etc., and heating and curing it sufficiently to prevent the shape from changing during subsequent multi-layer integration. After curing, the resin film has poor adhesion and can be easily peeled off mechanically. For example, Asahi Chemical Research Institute Strip Mask #228-T, #448-T
It can be formed more easily.
［作用］
内層回路板の電子部品搭載用金属導体箔を含む金属導体
箔パターンの接着強度は、金属導体箔を接着用のプリプ
レグと重ね合わせ全体を加熱加圧して積層一体化した金
属導体箔張積層板の金属導体箔面をエツチングすること
により形成したものであるから、強いものになる。[Function] The adhesive strength of the metal conductor foil pattern, including the metal conductor foil for mounting electronic components on the inner layer circuit board, is determined by the metal conductor foil cladding, which is made by laminating the metal conductor foil with adhesive prepreg and heating and pressurizing the entire layer. Since it is formed by etching the metal conductor foil surface of the laminate, it is strong.
この内層回路基板は多層金属張積層板に積層−体止する
際に、電子部品搭載用金属導体箔部分の上面に剥離型樹
脂膜を形成した後に接着用プリプレグを介して多層用回
路基板または金属導体箔を重ね合わせ全体を加熱加圧し
て形成するので、剥離型樹脂膜と電子部品搭載用金属導
体箔との間、剥離型樹脂膜とプリプレグ樹脂との間の接
合箇所の接着力は弱く、剥離型樹脂膜を除く他の接合箇
所の接着強度は強固に接着する。When this inner layer circuit board is laminated and fixed to a multilayer metal-clad laminate, a peelable resin film is formed on the top surface of the metal conductor foil portion for mounting electronic components, and then the multilayer circuit board or metal Since the conductor foil is formed by heating and pressurizing the entire stack, the adhesive strength at the joints between the peelable resin film and the metal conductor foil for mounting electronic components, and between the peelable resin film and the prepreg resin is weak. The adhesive strength of the joints other than the peelable resin film is strong.
電子部品搭載用金属導体箔の上部の外層金属箔やプリプ
レグ樹脂硬化物等を切削加工により削除する際に、剥離
型樹脂膜と電子部品搭載用金属導体箔との密着は弱いた
め、剥離型樹脂膜の外周端縁部を露出させるだけで容易
に中心部を剥離でき、切削加工時間を短くして凹部を形
成することが可能となる。When removing the outer layer metal foil or cured prepreg resin on the top of the metal conductor foil for mounting electronic components by cutting, the adhesion between the peelable resin film and the metal conductor foil for mounting electronic components is weak, so the peelable resin is By simply exposing the outer peripheral edge of the film, the center can be easily peeled off, making it possible to shorten the cutting time and form the recess.
［実施例］ この発明の実施例を第１図〜第３図を用いて説明する。[Example] An embodiment of this invention will be explained using FIGS. 1 to 3.
第１図〜第３図はそれぞれ工程説明図で第１図は内層回
路板３の片面に外層用の銅箔６ａを形成する場合の例を
示し、第２図は内層回路板３の両面に外層用の銅箔６ｂ
、６ｃを形成する場合の例を示し、第３図は内層回路板
３の両面に外層用の銅箔６ｂと多層用回路基板６ｄを形
成する場合の例を示している。1 to 3 are process explanatory diagrams, and FIG. 1 shows an example of forming an outer layer copper foil 6a on one side of the inner layer circuit board 3, and FIG. Copper foil 6b for outer layer
, 6c is shown, and FIG. 3 shows an example where an outer layer copper foil 6b and a multilayer circuit board 6d are formed on both sides of the inner layer circuit board 3.
先ず、内層回路板３を製作する。この内層回路板３は、
両面銅張積層板］を出発材料にしてこの両面銅張積層板
１に電子部品搭載用銅箔２ａを含む所望の銅箔回路パタ
ーン２をケミカルエツチング等の常套手段により形成す
ることにより製作する。First, the inner layer circuit board 3 is manufactured. This inner layer circuit board 3 is
A desired copper foil circuit pattern 2 including a copper foil 2a for mounting electronic components is formed on the double-sided copper-clad laminate 1 using a double-sided copper-clad laminate 1 as a starting material by conventional means such as chemical etching.
次に、この内層回路板３の少なくとも電子部品搭載用銅
箔２ａの部分に、印刷法などにより剥離型樹脂液の膜４
′を１００μｍ程度の厚みに印刷し、この剥離型樹脂液
の膜４′を１８０’Ｃ６０分間加熱して十分に反応硬化
させ剥離型樹脂膜４に形成する。この剥離型樹脂膜４は
銅箔やプリプレグ樹脂と接着力が弱く機械的に容易に剥
離できるもので、例えば■アサヒ化学研究所ストリップ
マスク＃２２８−Ｔ、＃４４８−Ｔを用いて形成する。Next, a film 4 of a removable resin liquid is applied to at least the part of the copper foil 2a for mounting electronic components on the inner layer circuit board 3 by a printing method or the like.
' is printed to a thickness of about 100 .mu.m, and this peelable resin liquid film 4' is heated at 180'C for 60 minutes to fully react and cure, forming the peelable resin film 4. This peelable resin film 4 has a weak adhesion to copper foil or prepreg resin and can be easily peeled off mechanically, and is formed using, for example, Asahi Chemical Research Institute strip mask #228-T or #448-T.
その後、片面に接着用の適数枚のプリプレグ５ａと銅箔
６ａを重ね合せ（第１図（ポ）参照）、あるいは両面に
接着用の適数枚のプリプレグ５ｂ５ｃと銅箔６ｂ、６ｃ
を重ね合せ（第２図（ポ）参照）、あるいは両面に接着
用の適数枚のプリ一
プレグ５ｂ、５ｃと銅箔６ｂ、多層用回路基板６ｄを重
ね合せ（第３図（ホ）参照）で、全体を加熱加圧により
積層一体成形して内層に電子部品搭載用銅箔２ａを含む
銅箔回路パターン２を有する多層銅張積層板（７ａ、７
ｂ、７ｃ）を得る。After that, an appropriate number of sheets of prepreg 5a for adhesion and copper foil 6a are superimposed on one side (see Figure 1 (Po)), or an appropriate number of sheets of prepreg 5b and copper foil 6b, 6c for adhesion are placed on both sides.
(See Figure 2 (Po)), or stack an appropriate number of pre-pregs 5b, 5c for adhesion on both sides, copper foil 6b, and multilayer circuit board 6d (see Figure 3 (E)). ), the whole is laminated and integrally molded by heating and pressing, and the inner layer has a copper foil circuit pattern 2 including a copper foil 2a for mounting electronic components (7a, 7).
b, 7c) are obtained.
次に、この多層銅張積層板（７ａ、７ｂ、７ｃ）の表面
より切削加工する際に、予め設けておいた基準マークを
基準にして内層の電子部品搭載用銅箔２ａの上面に反応
硬化している剥離型樹脂膜４の位置を算出して、剥離型
樹脂膜４の外周縁部を上部より切削加工により除去する
が、剥離型樹脂Ｊｌ！４の外周縁部が露出すると、その
内側の剥離型樹脂膜４やプリプレグ樹脂硬化物を機械的
に剥離して除去できる。Next, when cutting the surface of this multilayer copper-clad laminate (7a, 7b, 7c), the upper surface of the inner layer copper foil 2a for mounting electronic components is subjected to reaction hardening using the reference mark provided in advance as a reference. The position of the peelable resin film 4 is calculated, and the outer peripheral edge of the peelable resin film 4 is removed by cutting from the upper part, but the peelable resin Jl! When the outer peripheral edge of 4 is exposed, the peelable resin film 4 and the cured prepreg resin inside thereof can be mechanically peeled off and removed.
このようにして内層の電子部品搭載用銀箔部分を露出さ
せた凹部８を形成することができる。In this way, it is possible to form the recess 8 in which the silver foil portion of the inner layer for mounting electronic components is exposed.
その後、必要により上面の銅箔等に回路パターンの形成
や外径の切断等々の工程を経て所望の電子部品収納用凹
部を有するプリント配線基板が製造されることになる。Thereafter, if necessary, steps such as forming a circuit pattern on the copper foil or the like on the upper surface and cutting the outer diameter are performed to manufacture a printed wiring board having a desired electronic component housing recess.
尚、先に外層の回路パタンの形成を行い、その後に切削
加工により凹部を形成してもよい。Note that the circuit pattern of the outer layer may be formed first, and then the recessed portions may be formed by cutting.
［発明の効果］
この発明の配線基板の電子部品収納用凹部形成方法は、
凹部底面の銀箔パターンは接着用プリプレグ樹脂により
基板に接着したものであるので、凹部底面の銅箔パター
ンの接着強度が大となり、延いては回路基板の電子部品
収納用凹部のビール強度や耐熱性に優れた配線基板を得
ることかできる効果がある。[Effects of the Invention] The method for forming a recess for housing electronic components in a wiring board of the present invention includes the following steps:
Since the silver foil pattern on the bottom of the recess is bonded to the board using adhesive prepreg resin, the adhesive strength of the copper foil pattern on the bottom of the recess is high, which in turn increases the beer strength and heat resistance of the recess for storing electronic components on the circuit board. This has the effect of making it possible to obtain an excellent wiring board.
また、切削加工の際の切削刃先の切削深さ寸法の許容範
囲が剥離型樹脂膜の厚みの範囲まで拡大するので、電子
部品搭載用導体部分の過剰切削による傷の発生が少なく
なる効果がある。In addition, the allowable range of the cutting depth of the cutting edge during cutting is expanded to the thickness of the peelable resin film, which has the effect of reducing the occurrence of scratches due to excessive cutting of the conductor portion for mounting electronic components. .
また更に、電子部品搭載用導体部分の上面に形成した剥
離型樹脂膜の外周端縁部に沿って切削することにより、
中心部を機械的に容易に剥離除去できるので、切削時間
が短くなり出産性が向上する効果がある。Furthermore, by cutting along the outer peripheral edge of the peelable resin film formed on the top surface of the electronic component mounting conductor part,
Since the center part can be easily peeled off and removed mechanically, cutting time is shortened and childbirth performance is improved.
第１−図、第２図、第３図はそれぞれこの発明の詳細な
説明する工程図、第４図は従来例を説明する工程図であ
ることを示す。
１・・・両面銅張積層板、２ａ・・・電子部品搭載用銀
箔、３・・・内層用回路基板、４′・・・剥離型樹脂液
の膜、４・・・剥離型樹脂膜、５ａ、５ｂ、５ｃ・・・
接着用プリプレグ、６ａ、６ｂ、６ｃ・・・銅箔、６ｄ
・・・多層用回路基板、７ａ、７ｂ、７ｃ・・・多層銅
張積層板、８・・・凹部。1-, 2, and 3 are process diagrams for explaining the present invention in detail, and FIG. 4 is a process diagram for explaining a conventional example. DESCRIPTION OF SYMBOLS 1... Double-sided copper-clad laminate, 2a... Silver foil for mounting electronic components, 3... Circuit board for inner layer, 4'... Peelable resin liquid film, 4... Peelable resin film, 5a, 5b, 5c...
Adhesive prepreg, 6a, 6b, 6c...Copper foil, 6d
...Multilayer circuit board, 7a, 7b, 7c...Multilayer copper clad laminate, 8...Recessed portion.
Claims (1)
路パターンを形成した内層回路板の少なくとも１表面に
接着用プリプレグを介して多層用回路基板または金属導
体箔を重ね合わせ全体を加熱加圧積層一体化してなる多
層金属張積層基板の前記電子部品搭載用金属導体箔部の
上面を切削加工により除去してなる電子部品収納用凹部
形成方法であって、内層回路板の少なくとも電子部品搭
載用導体部分の上面に予め加熱硬化した剥離可能な樹脂
膜（以後、単に剥離型樹脂膜と云う）を形成しておき、
前記電子部品搭載用金属導体箔部の上面を切削加工する
際に剥離型樹脂膜まで切削して剥離型樹脂膜を剥離除去
することを特徴とする配線基板の電子部品収納用凹部形
成方法。(1) A multilayer circuit board or metal conductor foil is superimposed on at least one surface of the inner layer circuit board on which a metal conductor foil circuit pattern is formed, including a metal conductor foil portion for mounting electronic components, with an adhesive prepreg interposed therebetween, and the whole is heated. A method for forming a recess for housing an electronic component by removing by cutting the upper surface of the metal conductor foil portion for mounting an electronic component of a multilayer metal-clad laminate board formed by integrated pressure lamination, the method comprising: A heat-cured peelable resin film (hereinafter simply referred to as a peelable resin film) is formed in advance on the upper surface of the conductor portion,
A method for forming a recess for housing electronic components in a wiring board, characterized in that when cutting the upper surface of the metal conductor foil portion for mounting electronic components, the peelable resin film is also cut and the peelable resin film is peeled off.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21074990A JPH0493093A (en) | 1990-08-08 | 1990-08-08 | Forming method for electronic component containing recess of circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21074990A JPH0493093A (en) | 1990-08-08 | 1990-08-08 | Forming method for electronic component containing recess of circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0493093A true JPH0493093A (en) | 1992-03-25 |
Family
ID=16594491
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21074990A Pending JPH0493093A (en) | 1990-08-08 | 1990-08-08 | Forming method for electronic component containing recess of circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0493093A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2364828A (en) * | 2000-06-14 | 2002-02-06 | Murata Manufacturing Co | Method for making a multilayer board having a cavity |
| JP2002270991A (en) * | 2001-03-13 | 2002-09-20 | Ibiden Co Ltd | Printed wiring board and manufacturing method therefor |
| JP2011243751A (en) * | 2010-05-18 | 2011-12-01 | Unimicron Technology Corp | Circuit substrate and manufacturing method thereof |
| JP2014197596A (en) * | 2013-03-29 | 2014-10-16 | 京セラサーキットソリューションズ株式会社 | Multilayer wiring board and manufacturing method of the same |
| JP2016066799A (en) * | 2014-09-25 | 2016-04-28 | 株式会社イースタン | Semiconductor package substrate and manufacturing method of the same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61239693A (en) * | 1985-04-15 | 1986-10-24 | 松下電工株式会社 | Multilayer interconnection board and making thereof |
| JPS6392091A (en) * | 1986-10-07 | 1988-04-22 | 三菱瓦斯化学株式会社 | Manufacture of ic chip mounting multilayer board |
-
1990
- 1990-08-08 JP JP21074990A patent/JPH0493093A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61239693A (en) * | 1985-04-15 | 1986-10-24 | 松下電工株式会社 | Multilayer interconnection board and making thereof |
| JPS6392091A (en) * | 1986-10-07 | 1988-04-22 | 三菱瓦斯化学株式会社 | Manufacture of ic chip mounting multilayer board |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2364828A (en) * | 2000-06-14 | 2002-02-06 | Murata Manufacturing Co | Method for making a multilayer board having a cavity |
| GB2364828B (en) * | 2000-06-14 | 2002-07-24 | Murata Manufacturing Co | Method for making multilayer board having a cavity |
| JP2002270991A (en) * | 2001-03-13 | 2002-09-20 | Ibiden Co Ltd | Printed wiring board and manufacturing method therefor |
| JP2011243751A (en) * | 2010-05-18 | 2011-12-01 | Unimicron Technology Corp | Circuit substrate and manufacturing method thereof |
| JP2014197596A (en) * | 2013-03-29 | 2014-10-16 | 京セラサーキットソリューションズ株式会社 | Multilayer wiring board and manufacturing method of the same |
| JP2016066799A (en) * | 2014-09-25 | 2016-04-28 | 株式会社イースタン | Semiconductor package substrate and manufacturing method of the same |
| JP2016184752A (en) * | 2014-09-25 | 2016-10-20 | 株式会社イースタン | Semiconductor package substrate |
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