JP2891234B2 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP2891234B2
JP2891234B2 JP9109293A JP10929397A JP2891234B2 JP 2891234 B2 JP2891234 B2 JP 2891234B2 JP 9109293 A JP9109293 A JP 9109293A JP 10929397 A JP10929397 A JP 10929397A JP 2891234 B2 JP2891234 B2 JP 2891234B2
Authority
JP
Japan
Prior art keywords
semiconductor device
resin film
insulating resin
terminating resistor
opening
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP9109293A
Other languages
Japanese (ja)
Other versions
JPH10303247A (en
Inventor
政司 八野田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP9109293A priority Critical patent/JP2891234B2/en
Publication of JPH10303247A publication Critical patent/JPH10303247A/en
Application granted granted Critical
Publication of JP2891234B2 publication Critical patent/JP2891234B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance
    • H01L2924/30111Impedance matching

Landscapes

  • Wire Bonding (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は半導体装置に関し、
特に高周波用信号を扱う半導体装置に関する。
The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor device that handles high frequency signals.

【0002】[0002]

【従来の技術】近年、半導体装置の高速化に伴い、半導
体装置を搭載するパッケージ(PKG)自体の構造、あ
るいはパッケージを実装する際の問題が重要視されてい
る。特に、高周波信号を扱う場合には、実装した装置の
各接続部における信号の反射、伝送波形の劣化、あるい
は振幅の減衰などが無視できなくなるからである。
2. Description of the Related Art In recent years, as the speed of semiconductor devices has increased, the structure of the package (PKG) itself on which the semiconductor device is mounted, or the problem of mounting the package, has been emphasized. In particular, when handling high-frequency signals, signal reflection, transmission waveform deterioration, amplitude attenuation, and the like at each connection of the mounted device cannot be ignored.

【0003】このため、例えば入力信号の接続部におけ
る反射を防止するために、信号ラインの特性インピーダ
ンスとマッチングを取った終端抵抗(通常、50オー
ム)を設けることが行われている。
For this reason, for example, in order to prevent reflection at a connection portion of an input signal, a terminating resistor (usually 50 ohm) matched with the characteristic impedance of a signal line is provided.

【0004】図2は従来の一例を説明するための半導体
PKGの等価回路図である。図2に示すように、従来の
半導体PKG8は、外部入力端子9を備え、上述した終
端抵抗4aを実装基板側、すなわち半導体PKG8の外
部に取り付け、インピーダンスのマッチングを取るよう
にしている。
FIG. 2 is an equivalent circuit diagram of a semiconductor PKG for explaining an example of the related art. As shown in FIG. 2, the conventional semiconductor PKG 8 has an external input terminal 9, and the above-described terminating resistor 4a is mounted on the mounting substrate side, that is, outside the semiconductor PKG 8, so that impedance matching is performed.

【0005】図3は従来の他の例を説明するための半導
体PKの等価回路図である。図3に示すように、別の終
端抵抗の取り方としては、フィードスルーと呼ばれる方
式もある。この方式は、半導体ペレット3を備えたPK
G8の外部入力端子9Aからの信号配線を半導体ペレッ
ト3の外部で分岐させ、PKG8の他の端子部9Bに引
き出し、PKG8の外部に終端抵抗4aを設けるという
ものである。
FIG. 3 is an equivalent circuit diagram of a semiconductor PK for explaining another conventional example. As shown in FIG. 3, another method of obtaining a terminating resistor is a method called feedthrough. This method uses a PK with a semiconductor pellet 3
The signal wiring from the external input terminal 9A of G8 is branched outside the semiconductor pellet 3 and led out to another terminal 9B of the PKG 8, and a terminating resistor 4a is provided outside the PKG 8.

【0006】これらの他に、終端抵抗を設ける半導体装
置は、例えば特開平5−206202号公報などでも知
られている。
In addition to these, a semiconductor device provided with a terminating resistor is also known, for example, from Japanese Patent Application Laid-Open No. 5-206202.

【0007】図4(a),(b)はそれぞれかかる従来
のまた別の一例を説明するための半導体装置の平面図お
よびそのA−A’線断面図である。図4(a),(b)
に示すように、従来の半導体装置としては、中央に開孔
部6を形成した絶縁樹脂フィルム1と、この絶縁樹脂フ
ィルム1の一方の面(ここでは、下の面)に配列して設
けるとともに、先端を開孔部6の内部に突出させた金属
リード10と、開孔部6内に位置させ、バンプ12を介
して金属リード10の先端と接続させる半導体ペレット
3と、フィルム1の他方の面(ここでは、上の面)に設
けるとともに、フィルム1に形成したスルーホール11
を介して金属リード10の途中に接続する終端抵抗4a
とから構成されている。この例は、要するにパッケージ
内部に終端抵抗を取り込んだものである。
FIGS. 4A and 4B are a plan view and a cross-sectional view taken along the line AA 'of the semiconductor device, respectively, for explaining another conventional example. FIG. 4 (a), (b)
As shown in FIG. 1, as a conventional semiconductor device, an insulating resin film 1 having an opening 6 formed in the center and an insulating resin film 1 provided on one surface (here, a lower surface) of the insulating resin film 1 are provided. A metal lead 10 having a tip protruding into the opening 6, a semiconductor pellet 3 positioned in the opening 6 and connected to the tip of the metal lead 10 via the bump 12, and the other of the film 1. Surface (here, the upper surface) and the through holes 11 formed in the film 1.
Terminating resistor 4a connected in the middle of metal lead 10 through
It is composed of In this example, a terminating resistor is incorporated in the package.

【0008】[0008]

【発明が解決しようとする課題】上述した従来の図2に
示す半導体装置は、終端抵抗を実装基板側すなわちパッ
ケージの外部に取り付けることにより、インピーダンス
のマッチングを取るようにしているが、この手法ではパ
ッケージの内部に信号ラインやボンディングワイヤが存
在するため、終端抵抗は入力信号ラインの完全な終端部
に位置していない。このため、高速の入力信号に対して
は、波形の劣化などを生ずるという欠点がある。
In the above-described conventional semiconductor device shown in FIG. 2, impedance matching is achieved by attaching a terminating resistor to the mounting substrate side, that is, outside the package. Due to the presence of signal lines and bonding wires inside the package, the terminating resistor is not located at the complete end of the input signal line. For this reason, there is a disadvantage that the waveform is deteriorated for a high-speed input signal.

【0009】また、従来の図3に示す半導体装置は、図
2に比べて終端抵抗がほぼ入力信号の終端部に位置する
ことになるが、パッケージ内の信号入力配線数が2倍に
なる。したがって、入力端子数が増加し、ボンディング
パッドの高密度化を必要とするため、パッケージ内部の
配線が非常に困難になるという欠点がある。
Further, in the conventional semiconductor device shown in FIG. 3, the terminating resistor is located almost at the end of the input signal as compared with FIG. 2, but the number of signal input wirings in the package is doubled. Therefore, the number of input terminals increases, and the density of the bonding pads needs to be increased, so that there is a disadvantage that wiring inside the package becomes extremely difficult.

【0010】さらに、従来の図4に示す半導体装置は、
TABテープを用いて終端抵抗をパッケージ内部に取り
込んでいる。しかし、このTABテープは、片面側に終
端抵抗を形成し、反対側の面に外部端子との接続のため
の金属リードを形成するとともに、その両側をスルーホ
ールで接続することにより実現しているが、TABテー
プの製造工程が複雑になり、加工が困難になるという欠
点がある。特に、その分コストが上昇してしまうという
問題がある。
Further, the conventional semiconductor device shown in FIG.
Terminating resistors are incorporated into the package using a TAB tape. However, this TAB tape is realized by forming a terminating resistor on one side, forming metal leads for connection to external terminals on the opposite side, and connecting both sides of the TAB tape with through holes. However, there is a drawback that the manufacturing process of the TAB tape becomes complicated and processing becomes difficult. In particular, there is a problem that the cost increases accordingly.

【0011】本発明の目的は、高周波信号を扱う半導体
装置において、信号線の接続部における反射を防止し、
伝送波形の劣化や振幅の減衰を防ぐとともに、パッケー
ジ内配線を簡略化し、TABテープの製造を容易にする
ことのできる半導体装置を提供することにある。
An object of the present invention is to prevent reflection at a connection portion of a signal line in a semiconductor device handling a high-frequency signal,
It is an object of the present invention to provide a semiconductor device capable of preventing transmission waveform deterioration and amplitude attenuation, simplifying wiring in a package, and facilitating the manufacture of a TAB tape.

【0012】[0012]

【課題を解決するための手段】本発明の半導体装置は、
開孔部を形成した絶縁樹脂フィルム1と、前記開孔部内
に位置させるとともに、周辺に接続端子を形成した半導
体ペレットと、前記絶縁樹脂フィルムの上面に直接被着
して配列させ且つ一端を前記開孔部の内部まで突出させ
た終端抵抗用の抵抗層とを有し、前記開孔部内に位置す
る前記終端抵抗用の抵抗層の先端を前記接続端子に接続
すると共に、外部信号線用のボンディングワイヤを前記
接続端子に接続して構成される。
According to the present invention, there is provided a semiconductor device comprising:
An insulating resin film 1 having an opening formed therein, a semiconductor pellet having a connection terminal formed in the periphery while being positioned in the opening, and a semiconductor pellet directly attached to and arranged on the upper surface of the insulating resin film, and one end thereof being A resistance layer for a terminating resistor protruding to the inside of the opening, and connecting the tip of the resistance layer for the terminating resistor located in the opening to the connection terminal, and for an external signal line. It is configured by connecting a bonding wire to the connection terminal.

【0013】また、本発明の半導体装置における終端抵
抗用の抵抗層は、TABテープ上に単層構造で形成され
る。
The resistance layer for the terminating resistor in the semiconductor device of the present invention is formed in a single layer structure on a TAB tape.

【0014】さらに、本発明の半導体装置における半導
体ペレットおよび絶縁樹脂フィルムは、前記半導体ペレ
ットの4隅の一部および前記絶縁樹脂フィルムにまたが
る補強部材で補強して形成される。
Further, the semiconductor pellet and the insulating resin film in the semiconductor device of the present invention are formed by reinforcing with a reinforcing member extending over a part of four corners of the semiconductor pellet and the insulating resin film.

【0015】[0015]

【発明の実施の形態】次に、本発明の実施の形態につい
て図面を参照して説明する。
Next, embodiments of the present invention will be described with reference to the drawings.

【0016】図1(a),(b)はそれぞれ本発明の一
実施の形態を説明するための半導体装置の平面図および
そのA−A’線断面図である。図1(a),(b)に示
すように、本実施の形態の半導体装置は、中央部に開孔
部6を形成したポリイミドあるいはガラスエポキシなど
からなる絶縁樹脂フィルム1と、開孔部6内に位置させ
るとともに、周辺に接続端子2を形成した半導体ペレッ
ト3と、絶縁樹脂フィルム1の上面に直接被着して配列
させ且つ一端を開孔部6の内部まで突出させた終端抵抗
用の抵抗層4と、半導体ペレット3の4隅の一部および
絶縁樹脂フィルム1にまたがる補強部材7とを有してい
る。また、この開孔部6内に位置する終端抵抗用の抵抗
層4の先端は半導体ペレット3の接続端子2に接続する
と共に、外部信号線用のボンディングワイヤ5を接続端
子2に接続している。
FIGS. 1A and 1B are a plan view and a cross-sectional view taken along the line AA 'of a semiconductor device, respectively, for explaining an embodiment of the present invention. As shown in FIGS. 1A and 1B, a semiconductor device according to the present embodiment includes an insulating resin film 1 made of polyimide or glass epoxy having an opening 6 formed in the center, and an opening 6. And a semiconductor pellet 3 having connection terminals 2 formed therearound, and a terminal resistor for a terminal resistor which is directly attached to and arranged on the upper surface of the insulating resin film 1 and has one end protruding into the opening 6. It has a resistance layer 4 and a reinforcing member 7 extending over a part of four corners of the semiconductor pellet 3 and the insulating resin film 1. The tip of the resistor layer 4 for the terminating resistor located in the opening 6 is connected to the connection terminal 2 of the semiconductor pellet 3 and the bonding wire 5 for the external signal line is connected to the connection terminal 2. .

【0017】ここで、終端抵抗用の抵抗層4は金属材か
らなる薄膜又は厚膜でTABテープ上に単層構造で形成
され、伝送路の特性インピーダンスとマッチングさせて
おり、その抵抗層4の他端は終端電圧が供給されてい
る。
Here, the resistor layer 4 for the terminating resistor is a thin film or a thick film made of a metal material, is formed in a single layer structure on a TAB tape, and is matched with the characteristic impedance of the transmission line. The other end is supplied with a termination voltage.

【0018】また、補強部材7は、ボンディングワイヤ
5の接続に先立って、半導体ペレット3の4隅の一部と
絶縁樹脂フィルム1との間に接着され、その材質は絶縁
樹脂フィルム1と同一の材質で形成される。この補強部
材7は、半導体ペレット3の保持と、抵抗層4のずれ防
止との役目を果しているが、半導体ペレット3の保持が
抵抗層4のみで十分な場合には、半導体ペレット3の4
隅にかからないように、すなわち四角形状の補強部材と
することなく、絶縁樹脂フィルム1上のみにL型形状の
補強材として形成することができる。
The reinforcing member 7 is bonded between a part of the four corners of the semiconductor pellet 3 and the insulating resin film 1 prior to the connection of the bonding wire 5, and is made of the same material as the insulating resin film 1. It is formed of a material. The reinforcing member 7 serves to hold the semiconductor pellet 3 and to prevent the displacement of the resistance layer 4. However, when the holding of the semiconductor pellet 3 is sufficient only with the resistance layer 4, the semiconductor pellet 3 4
It can be formed as an L-shaped reinforcing material only on the insulating resin film 1 so as not to cover a corner, that is, without forming a rectangular reinforcing member.

【0019】さらに、外部信号線用のボンディングワイ
ヤ5は、前述したように、半導体ペレット3の接続端子
2と終端抵抗用の抵抗層4の先端とが接続されている部
分の上部にボンディング接続される。
Further, as described above, the bonding wire 5 for the external signal line is bonded to the upper part of the portion where the connection terminal 2 of the semiconductor pellet 3 and the tip of the resistor layer 4 for the terminating resistor are connected. You.

【0020】上述したように、本実施の形態によれば、
TABテープ上に終端抵抗を形成することにより、素子
に近接した位置で終端を取ることができるので、高速入
力信号の波形歪みを十分に小さくすることができる。ま
た、外部信号線側には、ボンディングワイヤを用いるこ
とにより、TABテープ自体は単面構成にできるので、
ボンディングの工程が追加になっても、2層構造のTA
Bテープを用いた場合と比較して、コスト的に低く抑え
ることができる。
As described above, according to the present embodiment,
By forming the terminating resistor on the TAB tape, it is possible to terminate at a position close to the element, so that the waveform distortion of the high-speed input signal can be sufficiently reduced. Also, by using a bonding wire on the external signal line side, the TAB tape itself can have a single-sided configuration,
Even if the bonding process is added, a two-layered TA
As compared with the case where the B tape is used, the cost can be reduced.

【0021】[0021]

【発明の効果】以上説明したように、本発明の半導体装
置は、絶縁樹脂フィルムの開孔部内に接続端子を形成し
た半導体ペレットを位置させ、フィルムの上面に終端抵
抗用の抵抗層を直接被着して配列させるとともに、先端
を開孔部の内部まで突出させ且つ抵抗層の先端と接続端
子を接続すると共に、外部信号線用のボンディングワイ
ヤを接続端子に接続することにより、信号線の接続部に
おける反射を防止し、伝送波形の劣化や振幅の減衰を防
ぐとともに、パッケージ内配線を簡略化し、TABテー
プの製造を容易にすることができるという効果がある。
As described above, in the semiconductor device of the present invention, the semiconductor pellet having the connection terminals formed therein is located in the opening of the insulating resin film, and the resistance layer for the terminating resistor is directly covered on the upper surface of the film. The connection of the signal lines is performed by connecting and connecting the connection terminals with the ends of the resistive layer and connecting the connection terminals to the ends of the resistive layer, and connecting the connection wires to the connection terminals. In addition to preventing reflection at the section, deterioration of transmission waveforms and attenuation of amplitude are prevented, wiring within the package is simplified, and the TAB tape can be easily manufactured.

【0022】特に、反射の影響を受けがたい終端抵抗を
単層のTABテープを用いて形成し、また外部との接続
は通常のワイヤボンディング方式を用いることにより、
抵コストで半導体装置をパッケージ内に納めることが可
能になる。
In particular, by using a single-layer TAB tape to form a terminating resistor that is not easily affected by reflection, and to connect to the outside by using a normal wire bonding method,
The semiconductor device can be housed in the package at low cost.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施の形態を説明するための半導体
装置の平面およびA−A’線断面を表わす図である。
FIG. 1 is a diagram illustrating a plane and a cross section taken along line AA ′ of a semiconductor device for describing an embodiment of the present invention;

【図2】従来の一例を説明するための半導体PKGの等
価回路図である。
FIG. 2 is an equivalent circuit diagram of a semiconductor PKG for explaining an example of the related art.

【図3】従来の他の例を説明するための半導体PKGの
等価回路図である。
FIG. 3 is an equivalent circuit diagram of a semiconductor PKG for explaining another conventional example.

【図4】従来のまた別の一例を説明するための半導体装
置の平面およびA−A’線断面を表わす図である。
FIG. 4 is a diagram showing a plane and a cross section taken along line AA ′ of a semiconductor device for explaining another conventional example.

【符号の説明】[Explanation of symbols]

1 絶縁樹脂フィルム 2 接続端子 3 半導体ペレット 4 終端抵抗層 5 ボンディングワイヤ 6 開孔部 7 補強部材 DESCRIPTION OF SYMBOLS 1 Insulating resin film 2 Connection terminal 3 Semiconductor pellet 4 Termination resistance layer 5 Bonding wire 6 Opening part 7 Reinforcement member

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6,DB名) H01L 21/60 311 H01L 21/60 301 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 6 , DB name) H01L 21/60 311 H01L 21/60 301

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 開孔部を形成した絶縁樹脂フィルムと、
前記開孔部内に位置させるとともに、周辺に接続端子を
形成した半導体ペレットと、前記絶縁樹脂フィルムの上
面に直接被着して配列させ且つ一端を前記開孔部の内部
まで突出させた終端抵抗用の抵抗層とを有し、前記開孔
部内に位置する前記終端抵抗用の抵抗層の先端を前記接
続端子に接続すると共に、外部信号線用のボンディング
ワイヤを前記接続端子に接続したことを特徴とする半導
体装置。
An insulating resin film having an opening formed therein,
A semiconductor pellet having a connection terminal formed in the periphery while being located in the opening, and a terminating resistor having one end protruding into the opening and being directly attached and arranged on the upper surface of the insulating resin film. And a tip of the resistor layer for the terminating resistor located in the opening is connected to the connection terminal, and a bonding wire for an external signal line is connected to the connection terminal. Semiconductor device.
【請求項2】 前記終端抵抗用の抵抗層は、TABテー
プ上に単層構造で形成される請求項1記載の半導体装
置。
2. The semiconductor device according to claim 1, wherein the resistance layer for the terminating resistor is formed in a single-layer structure on a TAB tape.
【請求項3】 前記半導体ペレットおよび前記絶縁樹脂
フィルムは、前記半導体ペレットの4隅の一部および前
記絶縁樹脂フィルムにまたがる補強部材で補強した請求
項1記載の半導体装置。
3. The semiconductor device according to claim 1, wherein the semiconductor pellet and the insulating resin film are reinforced by a reinforcing member extending over a part of four corners of the semiconductor pellet and the insulating resin film.
JP9109293A 1997-04-25 1997-04-25 Semiconductor device Expired - Lifetime JP2891234B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9109293A JP2891234B2 (en) 1997-04-25 1997-04-25 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9109293A JP2891234B2 (en) 1997-04-25 1997-04-25 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH10303247A JPH10303247A (en) 1998-11-13
JP2891234B2 true JP2891234B2 (en) 1999-05-17

Family

ID=14506511

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9109293A Expired - Lifetime JP2891234B2 (en) 1997-04-25 1997-04-25 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2891234B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4760509B2 (en) * 2006-04-21 2011-08-31 サンケン電気株式会社 Lead frame assembly

Also Published As

Publication number Publication date
JPH10303247A (en) 1998-11-13

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