JP2800761B2 - Multi-chip semiconductor device - Google Patents
Multi-chip semiconductor deviceInfo
- Publication number
- JP2800761B2 JP2800761B2 JP8036040A JP3604096A JP2800761B2 JP 2800761 B2 JP2800761 B2 JP 2800761B2 JP 8036040 A JP8036040 A JP 8036040A JP 3604096 A JP3604096 A JP 3604096A JP 2800761 B2 JP2800761 B2 JP 2800761B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- wiring
- semiconductor device
- chip
- island
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は１つのパッケージ内
に複数の半導体チップを搭載したマルチチップ半導体装
置に関する。The present invention relates to a multi-chip semiconductor device having a plurality of semiconductor chips mounted in one package.
【０００２】[0002]
【従来の技術】近年における半導体装置の高集積化およ
び高機能化に伴い、１つのパッケージ内に複数の半導体
チップを搭載したマルチチップ半導体装置が提案されて
いる。例えば、バイポーラ素子チップとＭＯＳ素子チッ
プとを１つのパッケージに搭載したもの、あるいはＳｉ
素子チップとＧａＡｓ素子チップを１つのパッケージに
搭載したものがある。このため、パッケージ内に異なる
複数の素子チップを封止させる必要があり、したがっ
て、パッケージ内における素子チップの搭載構造と、リ
ードフレームに対する電気接続構造が複雑なものにな
る。2. Description of the Related Art With the recent increase in the degree of integration and function of semiconductor devices, a multi-chip semiconductor device in which a plurality of semiconductor chips are mounted in one package has been proposed. For example, a device in which a bipolar device chip and a MOS device chip are mounted in one package,
There is one in which an element chip and a GaAs element chip are mounted in one package. For this reason, it is necessary to seal a plurality of different element chips in the package, so that the mounting structure of the element chips in the package and the electrical connection structure to the lead frame are complicated.
【０００３】図４はこの種のマルチチップ半導体装置の
一例を示す図であり、リードフレーム２１に２つのアイ
ランド２２Ａ，２２Ｂを並んで形成し、各アイランドに
それぞれ素子チップ２３Ａ，２３Ｂを搭載し、各素子チ
ップ２３Ａ，２３Ｂとインナリード２４とを金属細線２
５により電気接続し、これらを図外の樹脂等によりモー
ルドしてパッケージを形成している。しかしながら、こ
の構成では、素子チップの数が増加されると、これに伴
ってリード数も増加され、さらにアイランドの数も増加
されるために、これらアイランドの周囲に確保し得るス
ペースに制約を受け、素子チップとリードとを接続する
金属細線の本数やリード数の増大に限界が生じ、この限
界によって高集積化の実現が困難になるという問題が生
じている。このため、リードの形状や位置等を考慮した
特異なリードフレームが要求されることになり、リード
フレームの設計が煩雑かつ困難なものになる。FIG. 4 is a view showing an example of this type of multi-chip semiconductor device. Two islands 22A and 22B are formed side by side on a lead frame 21, and element chips 23A and 23B are mounted on each island. Each element chip 23A, 23B and the inner lead 24 are
5, and these are molded with a resin or the like (not shown) to form a package. However, in this configuration, when the number of element chips is increased, the number of leads is also increased, and the number of islands is also increased. Therefore, the space that can be secured around these islands is limited. However, there is a limit to the increase in the number of metal wires connecting the element chip and the lead and the number of leads, and this limit poses a problem that it is difficult to achieve high integration. For this reason, a unique lead frame in consideration of the shape and position of the lead is required, and the design of the lead frame becomes complicated and difficult.
【０００４】このような、素子チップおよびリードとの
間の電気接続におけるスペース上の問題を解消するため
には、特開平４−１６７５３１号公報に提案されている
ようなフィルムを利用することが考えられる。この技術
は、図５に示すように、リードフレーム等に搭載されて
いる素子チップ３１の表面に絶縁フィルム３２を貼り付
け、この絶縁フィルム３２に形成されている中間配線３
３の一端に素子チップ３１の電極を金属細線３４で接続
し、中間配線３３の他端をリード３５に直接的に電気接
続することで、素子チップ３１回りのスペースを有効に
利用して高集積化に対処しようとするものである。In order to solve such a space problem in electrical connection between the element chip and the leads, it is conceivable to use a film as proposed in Japanese Patent Application Laid-Open No. 4-167531. Can be In this technique, as shown in FIG. 5, an insulating film 32 is attached to the surface of an element chip 31 mounted on a lead frame or the like, and an intermediate wiring 3 formed on the insulating film 32 is formed.
The electrode of the element chip 31 is connected to one end of the element chip 3 by a thin metal wire 34, and the other end of the intermediate wiring 33 is directly electrically connected to the lead 35, so that the space around the element chip 31 is effectively used to achieve high integration. Is to deal with the change.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、図５に
示した技術をそのまま図４のマルチチップ半導体装置に
適用した場合、個々のアイランドにそれぞれ搭載される
素子チップ上の各絶縁フィルムはあくまでも素子チップ
とリードとを接続するためのものであるため、リードの
位置や形状を各素子チップに対応させたリードフレーム
の設計を行うことは必要であり、各リードの位置や形状
の制約によってその設計が困難になるという前記した問
題を解消することは難しい。However, when the technique shown in FIG. 5 is applied to the multi-chip semiconductor device of FIG. 4 as it is, each insulating film on the element chip mounted on each island is merely an element chip. It is necessary to design the lead frame so that the position and shape of the lead correspond to each element chip, and the design is restricted by the position and shape of each lead. It is difficult to solve the above-mentioned problem of becoming difficult.
【０００６】また、素子チップ相互間の電気接続を行う
ためには、結局各素子チップ上に貼り付けられる絶縁フ
ィルムの中間配線間を金属細線等により相互に電気接続
する必要があり、そのためのスペースが必要である上
に、その接続作業が極めて煩雑なものとなり、しかも金
属細線同士の短絡等の問題が生じることがあり、結果と
してマルチチップ半導体装置全体の高集積化を実現する
ことは難しい。また、絶縁フィルムは、素子チップ上に
貼り付けられるため、これに形成される中間配線の特性
インピーダンスがその貼り付け状態によって変動され易
く、高周波信号の伝達特性が劣化され、高周波用半導体
装置の実現が難しいものとなる。Further, in order to make electrical connection between the element chips, it is necessary to electrically connect the intermediate wirings of the insulating film pasted on each of the element chips with a thin metal wire or the like. In addition, the connection work becomes extremely complicated, and a problem such as a short circuit between the thin metal wires may occur. As a result, it is difficult to achieve high integration of the entire multi-chip semiconductor device. In addition, since the insulating film is attached on the element chip, the characteristic impedance of the intermediate wiring formed thereon is likely to fluctuate depending on the attached state, the transmission characteristics of high-frequency signals are degraded, and a high-frequency semiconductor device is realized. Is difficult.
【０００７】本発明の目的は、リードフレームの設計を
困難なものにすることなく、しかも電気的な接続を容易
に行い、しかも高周波特性に優れたマルチチップ半導体
装置を提供することにある。An object of the present invention is to provide a multi-chip semiconductor device which facilitates electrical connection without making the design of a lead frame difficult, and which is excellent in high frequency characteristics.
【０００８】[0008]
【課題を解決するための手段】本発明のマルチチップ半
導体装置では、リードフレームのアイランド上に複数個
の素子チップと、中間配線を設けたフィルム回路とを搭
載し、各素子チップと中間配線との間、および中間配線
とリードフレームの外部導出リードとの間をそれぞれ金
属細線で接続したことを特徴とする。ここで、フィルム
回路は、絶縁フィルムの表面に薄膜導体で中間配線が形
成されており、この中間配線は上層、下層の各配線膜が
形成された多層構造とされ、上層配線膜とアイランドと
をグラウンド接続し、下層配線膜のインピーダンス整合
をとるように構成される。In the multi-chip semiconductor device according to the present invention, a plurality of element chips and a film circuit provided with intermediate wiring are mounted on an island of a lead frame. And the intermediate wiring and the lead out of the lead frame are connected by thin metal wires. Here, the film circuit has an intermediate wiring formed of a thin film conductor on the surface of an insulating film, and the intermediate wiring has a multilayer structure in which upper and lower wiring films are formed. It is configured to be connected to ground and to match the impedance of the lower wiring film.
【０００９】[0009]
【発明の実施の形態】次に、本発明の実施形態を図面を
参照して説明する。図１は本発明をＱＦＰ（Quadrature
Flat Package)型のマルチチップ半導体装置に適用した
パッケージの一部を破断した平面図である。リードフレ
ーム１には、複数の素子チップを搭載可能な大きさの矩
形のアイランド２が形成されており、吊りリード３によ
り保持される。また、このアイランド２の周囲には多数
本のインナリード４が配列される。これらのインナリー
ド４は図外のアウタリードと一体に形成されて外部導出
リードを構成していることは言うまでもない。そして、
前記アイランド２には、フィルム回路５と複数の素子チ
ップ６が搭載されている。Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a QFP (Quadrature) according to the present invention.
FIG. 3 is a plan view in which a part of a package applied to a (Flat Package) type multi-chip semiconductor device is partially broken. A rectangular island 2 large enough to mount a plurality of element chips is formed on a lead frame 1, and is held by suspension leads 3. A number of inner leads 4 are arranged around the island 2. Needless to say, these inner leads 4 are formed integrally with outer leads (not shown) to form external leads. And
On the island 2, a film circuit 5 and a plurality of element chips 6 are mounted.
【００１０】前記フィルム回路５は、図２にその拡大平
面図とＡＡ線断面図を示すように、前記アイランド２の
形状に沿った矩形の絶縁フィルム膜１１を主体に形成さ
れ、その複数箇所には素子チップをアイランドに搭載す
るための窓１２が開口される。また、この絶縁フィルム
膜１１の表面には、各窓１２の周縁に沿う箇所と、絶縁
フィルム膜１１の周辺部には、それぞれ導電薄膜で形成
された内部電極部１３と外部電極部１４が形成されてお
り、各電極部１３，１４は同じく導電薄膜で形成された
配線部１５により電気接続され、これらで中間配線１６
が形成される。The film circuit 5 is formed mainly of a rectangular insulating film film 11 conforming to the shape of the island 2 as shown in an enlarged plan view and a sectional view taken along the line AA in FIG. A window 12 for mounting an element chip on an island is opened. Further, on the surface of the insulating film film 11, an internal electrode portion 13 and an external electrode portion 14 each formed of a conductive thin film are formed on a portion along the periphery of each window 12 and on a peripheral portion of the insulating film film 11. The electrode portions 13 and 14 are electrically connected by a wiring portion 15 also formed of a conductive thin film.
Is formed.
【００１１】そして、このフィルム回路５は、前記アイ
ランド２に接着剤により接着固定される。また、このフ
ィルム回路５の窓１２内に露呈されたアイランド２の表
面にはそれぞれ前記素子チップ６が搭載される。しかる
上で、素子チップ６の各電極パッドと中間配線の内部電
極部１３とが金属細線７で相互に電気接続され、同様に
中間配線の外部電極部１４とリードフレーム１のインナ
リード４とが金属細線７で相互に電気接続される。これ
により、各素子チップ６はフィルム回路５の中間配線を
介してそれぞれインナリード４に電気接続されることに
なる。The film circuit 5 is fixed to the island 2 with an adhesive. The element chips 6 are mounted on the surfaces of the islands 2 exposed in the windows 12 of the film circuit 5, respectively. Thereafter, each electrode pad of the element chip 6 and the internal electrode portion 13 of the intermediate wiring are electrically connected to each other by the thin metal wire 7, and similarly, the external electrode portion 14 of the intermediate wiring and the inner lead 4 of the lead frame 1 are connected. The metal wires 7 are electrically connected to each other. As a result, each element chip 6 is electrically connected to the inner lead 4 via the intermediate wiring of the film circuit 5.
【００１２】なお、前記アイランド２、フィルム回路
５、素子チップ６、金属細線７、インナリード４はその
一部が図示されている樹脂８によりモールド封止され、
パッケージが形成される。したがって、このマルチチッ
プ半導体装置では、フィルム回路５の窓１２の配列や中
間配線１６のパターンを任意に設計することで、汎用構
造のリードフレームを用いても種々の機能の半導体装置
を構成することができる。したがって、配置スペース等
の制約が多いリードフレームの設計は不要であり、その
代わりに設計自由度の高いフィルム回路を設計すればよ
いため、結果として半導体装置の設計を容易なものにで
きる。また、個々の素子チップ６とインナリード４との
電気接続はもとより、素子チップ６の相互間の電気接続
をフィルム回路５の中間配線１６によって行うため、各
素子チップ間に金属細線を接続する必要は殆どなく、金
属細線の相互短絡や、相互干渉による断線等の不具合が
生じることもない。The island 2, the film circuit 5, the element chip 6, the fine metal wire 7, and the inner lead 4 are partly molded and sealed with a resin 8 shown in FIG.
A package is formed. Therefore, in this multi-chip semiconductor device, by arbitrarily designing the arrangement of the windows 12 of the film circuit 5 and the pattern of the intermediate wiring 16, it is possible to configure semiconductor devices having various functions even with a general-purpose lead frame. Can be. Therefore, it is not necessary to design a lead frame having many restrictions such as an arrangement space and the like, and instead, it is only necessary to design a film circuit having a high degree of freedom in design, and as a result, it is possible to easily design a semiconductor device. Further, since not only the individual element chips 6 and the inner leads 4 are electrically connected but also the element chips 6 are electrically connected to each other by the intermediate wiring 16 of the film circuit 5, it is necessary to connect thin metal wires between the element chips. There are almost no problems, such as mutual short-circuiting of fine metal wires and disconnection due to mutual interference.
【００１３】図３は本発明の第２の実施形態に用いられ
るフィルム回路５Ａの平面図とそのＢＢ線断面図であ
る。ここでは、フィルム回路５Ａは多層回路構造として
構成されており、下層フィルム膜２１の表面に下層配線
膜２２によって中間配線１６が形成されており、この中
間配線１６を被覆するように上層フィルム膜２３が被着
され、この上層フィルム膜２３の表面に上層配線膜２４
が形成されている。高周波用の半導体装置では、特に信
号線路において高周波信号の減衰が生じ易く、これを防
止するためにインピーダンスの整合が不可欠である。特
に、半導体装置が小型であればそれほど問題にならない
が、大型のパッケージに素子チップを搭載する場合に
は、金属細線の長さも無視できなくなり、パッケージ内
での金属細線のインピーダンスの整合が問題となる。FIG. 3 is a plan view of a film circuit 5A used in a second embodiment of the present invention and a sectional view taken along the line BB. Here, the film circuit 5A is configured as a multilayer circuit structure, and an intermediate wiring 16 is formed on a surface of a lower film film 21 by a lower wiring film 22. An upper film film 23 is formed so as to cover the intermediate wiring 16. Is adhered, and the upper wiring film 24 is formed on the surface of the upper film film 23.
Are formed. In a high-frequency semiconductor device, high-frequency signals tend to be attenuated, particularly in signal lines, and impedance matching is indispensable to prevent this. In particular, if the semiconductor device is small, this is not a problem, but if the element chip is mounted on a large package, the length of the thin metal wire cannot be ignored, and the impedance matching of the thin metal wire in the package is a problem. Become.
【００１４】図３に示したフィルム回路５Ａでは、下層
配線膜２２と上層配線膜２４とで多層構造とされている
ため、下層配線膜２２からなる中間配線１６の幅Ｗと、
上下層の各フィルム膜２１，２３の厚さｔ１，ｔ２を適
切に設定し、かつこのフィルム回路５Ａを搭載するアイ
ランド２（図１参照）と上層配線膜２４とをそれぞれ接
地電位に設定することで、マイクロストリップ構造が構
成され、信号配線としての中間配線１６におけるインピ
ーダンス整合を取り、高周波信号の伝達特性を最適化す
ることが可能となる。In the film circuit 5A shown in FIG. 3, since the lower wiring film 22 and the upper wiring film 24 have a multilayer structure, the width W of the intermediate wiring 16 composed of the lower wiring film 22,
The thicknesses t1 and t2 of the upper and lower film films 21 and 23 are appropriately set, and the island 2 (see FIG. 1) on which the film circuit 5A is mounted and the upper wiring film 24 are each set to the ground potential. Thus, a microstrip structure is formed, and impedance matching in the intermediate wiring 16 as a signal wiring can be achieved, and the transmission characteristics of a high-frequency signal can be optimized.
【００１５】[0015]
【発明の効果】以上説明したように本発明は、リードフ
レームのアイランドに複数の素子チップとフィルム回路
を搭載し、フィルム回路に設けられた中間配線と素子チ
ップおよびリードフレームの外部導出リードとを金属細
線で接続しているので、フィルム回路の中間配線を任意
に設計することで複数の素子チップ間の電気接続が可能
となり、かつ各素子チップと外部導出リードとの間の金
属細線による複雑な接続が不要となる。これにより、設
計の自由度の高いフィルム回路の設計を行うことで、設
計に際しての制約の多いリードフレームの設計が不要と
なり、マルチチップ半導体装置全体の設計を容易に行う
ことができる。As described above, according to the present invention, a plurality of element chips and a film circuit are mounted on an island of a lead frame, and the intermediate wiring provided on the film circuit and the external leads of the element chip and the lead frame are formed. Since the connection is made with thin metal wires, electrical connection between a plurality of device chips is possible by arbitrarily designing the intermediate wiring of the film circuit, and complicated metal thin wires between each device chip and external leads are used. No connection is required. Thus, by designing a film circuit having a high degree of freedom in designing, it is not necessary to design a lead frame which has many restrictions in designing, and it is possible to easily design the entire multi-chip semiconductor device.
【００１６】また、フィルム回路の中間配線を介して複
数の素子チップと外部導出リードとが相互に電気接続さ
れ、かつ複数の素子チップが相互に電気接続されるの
で、素子チップとリードとの金属細線による電気接続を
簡単化でき、金属細線の短絡や相互干渉による断線を防
止することができ、半導体装置の信頼性を高めることが
できる。さらに、フィルム回路の中間配線を多層構造と
し、その一部の配線をグラウンド接続することで、中間
配線におけるインピーダンス整合を取ることができ、高
周波信号の伝達特性を最適化し、高周波特性に優れた半
導体装置を得ることができる。Further, since the plurality of element chips and the external lead are electrically connected to each other via the intermediate wiring of the film circuit, and the plurality of element chips are electrically connected to each other, the metal of the element chip and the leads is formed. The electrical connection using the thin wires can be simplified, the short circuit of the thin metal wires and the disconnection due to mutual interference can be prevented, and the reliability of the semiconductor device can be improved. In addition, the intermediate wiring of the film circuit has a multi-layer structure, and by connecting some of the wiring to the ground, impedance matching in the intermediate wiring can be achieved, the transmission characteristics of high-frequency signals are optimized, and semiconductors with excellent high-frequency characteristics A device can be obtained.
【図１】本発明の第１の実施形態の一部を破断した平面
図である。FIG. 1 is a partially cutaway plan view of a first embodiment of the present invention.
【図２】図１の半導体装置に用いられるフィルム回路の
拡大平面図とＡＡ線断面図である。FIG. 2 is an enlarged plan view and a cross-sectional view taken along line AA of a film circuit used in the semiconductor device of FIG.
【図３】本発明の第２の実施形態に用いられるフィルム
回路の平面図とＢＢ線断面図である。FIG. 3 is a plan view and a cross-sectional view taken along the line BB of a film circuit used in a second embodiment of the present invention.
【図４】従来のマルチチップ半導体装置の一例の内部構
造の平面図である。FIG. 4 is a plan view of an internal structure of an example of a conventional multichip semiconductor device.
【図５】従来の絶縁フィルムを利用した半導体装置の一
部の平面図である。FIG. 5 is a plan view of a part of a semiconductor device using a conventional insulating film.
１ リードフレーム ２ アイランド ４ インナリード ５，５Ａ フィルム回路 ６ 素子チップ ７ 金属細線 ８ 樹脂 １１ 絶縁フィルム膜 １２ 窓 １６ 中間配線 ２１ 下層フィルム膜 ２２ 下層配線膜 ２３ 上層フィルム膜 ２４ 上層配線膜 DESCRIPTION OF SYMBOLS 1 Lead frame 2 Island 4 Inner lead 5, 5A Film circuit 6 Element chip 7 Fine metal wire 8 Resin 11 Insulating film film 12 Window 16 Intermediate wiring 21 Lower film film 22 Lower wiring film 23 Upper film film 24 Upper wiring film
Claims (2)
を搭載するマルチチップ半導体装置において、リードフ
レームのアイランド上に複数個の素子チップと、中間配
線を設けたフィルム回路とを搭載し、前記フィルム回路
の前記中間配線は、上層、下層の各配線膜が形成された
多層構造とされ、前記素子チップと前記下層配線膜との
間、前記下層配線膜と前記リードフレームの外部導出リ
ードとの間をそれぞれ金属細線で接続し、かつ前記上層
配線膜と前記アイランドとをグラウンド接続して前記下
層配線膜のインピーダンス整合をとるように構成される
ことを特徴とするマルチチップ半導体装置。1. A multi-chip semiconductor device that has multiple device chips in one package, mounted a plurality of device chips, and a film circuit provided intermediate wiring on the leadframe island, said film circuit
In the intermediate wiring, upper and lower wiring films are formed.
The device chip and the lower wiring film have a multilayer structure.
Between the lower wiring film and the lead-out frame.
Between the upper layer and the upper layer.
Connect the wiring film and the island to ground and
A multi-chip semiconductor device configured to match impedance of a layer wiring film .
面に薄膜導体で前記下層配線膜を形成し、さらにその上
の絶縁フィルムの表面に薄膜導体で前記上層配線膜を形
成している請求項１に記載のマルチチップ半導体装置。Wherein said film circuit, the lower wiring layer in the thin film conductor is formed on the surface of the insulating film, further thereon
The upper wiring film is formed with a thin conductor on the surface of the insulating film
Multi-chip semiconductor device according to claim 1 which forms.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8036040A JP2800761B2 (en) | 1996-02-23 | 1996-02-23 | Multi-chip semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8036040A JP2800761B2 (en) | 1996-02-23 | 1996-02-23 | Multi-chip semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09232500A JPH09232500A (en) | 1997-09-05 |
| JP2800761B2 true JP2800761B2 (en) | 1998-09-21 |
Family
ID=12458604
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8036040A Expired - Fee Related JP2800761B2 (en) | 1996-02-23 | 1996-02-23 | Multi-chip semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2800761B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102082137A (en) * | 2009-10-26 | 2011-06-01 | 佳能株式会社 | Semiconductor device, print plate and semiconductor package |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4031333B2 (en) | 2002-09-26 | 2008-01-09 | 株式会社ルネサステクノロジ | Semiconductor device |
| JP2010034386A (en) | 2008-07-30 | 2010-02-12 | Fibest Ltd | Optical semiconductor device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62265734A (en) * | 1986-05-13 | 1987-11-18 | Nec Corp | Hybrid integrated circuit device |
| JPS63244747A (en) * | 1987-03-31 | 1988-10-12 | Toshiba Corp | Resin sealed integrated circuit device and manufacture thereof |
| JPH06334114A (en) * | 1993-03-25 | 1994-12-02 | Toppan Printing Co Ltd | Multichip semiconductor device |
-
1996
- 1996-02-23 JP JP8036040A patent/JP2800761B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102082137A (en) * | 2009-10-26 | 2011-06-01 | 佳能株式会社 | Semiconductor device, print plate and semiconductor package |
| CN102082137B (en) * | 2009-10-26 | 2013-11-06 | 佳能株式会社 | Semiconductor device, print plate and semiconductor package |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH09232500A (en) | 1997-09-05 |
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